tjh.dev
+16
-10
arch/x86/kvm/lapic.c
+16
-10
arch/x86/kvm/lapic.c
···
1090
1090
apic->divide_count);
1091
1091
}
1092
1092
1093
+
static void apic_update_lvtt(struct kvm_lapic *apic)
1094
+
{
1095
+
u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1096
+
apic->lapic_timer.timer_mode_mask;
1097
+
1098
+
if (apic->lapic_timer.timer_mode != timer_mode) {
1099
+
apic->lapic_timer.timer_mode = timer_mode;
1100
+
hrtimer_cancel(&apic->lapic_timer.timer);
1101
+
}
1102
+
}
1103
+
1093
1104
static void apic_timer_expired(struct kvm_lapic *apic)
1094
1105
{
1095
1106
struct kvm_vcpu *vcpu = apic->vcpu;
···
1309
1298
apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1310
1299
lvt_val | APIC_LVT_MASKED);
1311
1300
}
1301
+
apic_update_lvtt(apic);
1312
1302
atomic_set(&apic->lapic_timer.pending, 0);
1313
1303
1314
1304
}
···
1342
1330
1343
1331
break;
1344
1332
1345
-
case APIC_LVTT: {
1346
-
u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1347
-
1348
-
if (apic->lapic_timer.timer_mode != timer_mode) {
1349
-
apic->lapic_timer.timer_mode = timer_mode;
1350
-
hrtimer_cancel(&apic->lapic_timer.timer);
1351
-
}
1352
-
1333
+
case APIC_LVTT:
1353
1334
if (!kvm_apic_sw_enabled(apic))
1354
1335
val |= APIC_LVT_MASKED;
1355
1336
val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1356
1337
apic_set_reg(apic, APIC_LVTT, val);
1338
+
apic_update_lvtt(apic);
1357
1339
break;
1358
-
}
1359
1340
1360
1341
case APIC_TMICT:
1361
1342
if (apic_lvtt_tscdeadline(apic))
···
1581
1576
1582
1577
for (i = 0; i < APIC_LVT_NUM; i++)
1583
1578
apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1584
-
apic->lapic_timer.timer_mode = 0;
1579
+
apic_update_lvtt(apic);
1585
1580
apic_set_reg(apic, APIC_LVT0,
1586
1581
SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1587
1582
···
1807
1802
1808
1803
apic_update_ppr(apic);
1809
1804
hrtimer_cancel(&apic->lapic_timer.timer);
1805
+
apic_update_lvtt(apic);
1810
1806
update_divide_count(apic);
1811
1807
start_apic_timer(apic);
1812
1808
apic->irr_pending = true;