Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/amdgpu: imu fw loading support

support imu related function for gfx v12.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Kenneth Feng and committed by
Alex Deucher
32d16376 af204b76

+337 -3
+2 -1
drivers/gpu/drm/amd/amdgpu/Makefile
··· 168 168 gfx_v11_0.o \ 169 169 gfx_v11_0_3.o \ 170 170 imu_v11_0_3.o \ 171 - gfx_v12_0.o 171 + gfx_v12_0.o \ 172 + imu_v12_0.o 172 173 173 174 # add async DMA block 174 175 amdgpu-y += \
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 30 30 #include "amdgpu_psp.h" 31 31 #include "amdgpu_smu.h" 32 32 #include "amdgpu_atomfirmware.h" 33 + #include "imu_v12_0.h" 33 34 #include "soc24.h" 34 35 #include "nvd.h" 35 36 ··· 4524 4523 else 4525 4524 adev->gfx.imu.mode = DEBUG_MODE; 4526 4525 4527 - /* TODO */ 4528 - //adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 4526 + adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 4529 4527 } 4530 4528 4531 4529 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)
+303
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
··· 1 + /* 2 + * Copyright 2023 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + 24 + #include <linux/firmware.h> 25 + #include "amdgpu.h" 26 + #include "amdgpu_imu.h" 27 + #include "amdgpu_dpm.h" 28 + 29 + #include "imu_v12_0.h" 30 + 31 + #include "gc/gc_12_0_0_offset.h" 32 + #include "gc/gc_12_0_0_sh_mask.h" 33 + 34 + MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin"); 35 + 36 + static int imu_v12_0_init_microcode(struct amdgpu_device *adev) 37 + { 38 + char fw_name[40]; 39 + char ucode_prefix[30]; 40 + int err; 41 + const struct imu_firmware_header_v1_0 *imu_hdr; 42 + struct amdgpu_firmware_info *info = NULL; 43 + 44 + DRM_DEBUG("\n"); 45 + 46 + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 47 + 48 + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix); 49 + err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name); 50 + if (err) 51 + goto out; 52 + imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; 53 + adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); 54 + 55 + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 56 + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I]; 57 + info->ucode_id = AMDGPU_UCODE_ID_IMU_I; 58 + info->fw = adev->gfx.imu_fw; 59 + adev->firmware.fw_size += 60 + ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE); 61 + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D]; 62 + info->ucode_id = AMDGPU_UCODE_ID_IMU_D; 63 + info->fw = adev->gfx.imu_fw; 64 + adev->firmware.fw_size += 65 + ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE); 66 + } 67 + 68 + out: 69 + if (err) { 70 + dev_err(adev->dev, 71 + "gfx12: Failed to load firmware \"%s\"\n", 72 + fw_name); 73 + amdgpu_ucode_release(&adev->gfx.imu_fw); 74 + } 75 + 76 + return err; 77 + } 78 + 79 + static int imu_v12_0_load_microcode(struct amdgpu_device *adev) 80 + { 81 + const struct imu_firmware_header_v1_0 *hdr; 82 + const __le32 *fw_data; 83 + unsigned i, fw_size; 84 + 85 + if (!adev->gfx.imu_fw) 86 + return -EINVAL; 87 + 88 + hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; 89 + 90 + fw_data = (const __le32 *)(adev->gfx.imu_fw->data + 91 + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 92 + fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4; 93 + 94 + WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); 95 + 96 + for (i = 0; i < fw_size; i++) 97 + WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); 98 + 99 + WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); 100 + 101 + fw_data = (const __le32 *)(adev->gfx.imu_fw->data + 102 + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 103 + le32_to_cpu(hdr->imu_iram_ucode_size_bytes)); 104 + fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4; 105 + 106 + WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); 107 + 108 + for (i = 0; i < fw_size; i++) 109 + WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); 110 + 111 + WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); 112 + 113 + return 0; 114 + } 115 + 116 + static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev) 117 + { 118 + int i, imu_reg_val = 0; 119 + 120 + for (i = 0; i < adev->usec_timeout; i++) { 121 + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); 122 + if ((imu_reg_val & 0x1f) == 0x1f) 123 + break; 124 + udelay(1); 125 + } 126 + 127 + if (i >= adev->usec_timeout) { 128 + dev_err(adev->dev, "init imu: IMU start timeout\n"); 129 + return -ETIMEDOUT; 130 + } 131 + 132 + return 0; 133 + } 134 + 135 + static void imu_v12_0_setup(struct amdgpu_device *adev) 136 + { 137 + int imu_reg_val; 138 + 139 + WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); 140 + WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); 141 + 142 + if (adev->gfx.imu.mode == DEBUG_MODE) { 143 + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); 144 + imu_reg_val |= 0x1; 145 + WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); 146 + } 147 + } 148 + 149 + static int imu_v12_0_start(struct amdgpu_device *adev) 150 + { 151 + int imu_reg_val; 152 + 153 + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); 154 + imu_reg_val &= 0xfffffffe; 155 + WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); 156 + 157 + if (adev->flags & AMD_IS_APU) 158 + amdgpu_dpm_set_gfx_power_up_by_imu(adev); 159 + 160 + return imu_v12_0_wait_for_reset_status(adev); 161 + } 162 + 163 + static const struct imu_rlc_ram_golden imu_rlc_ram_golden_12_0_1[] = { 164 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCH_PIPE_STEER, 0x1e4, 0x1c0000), 165 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1X_PIPE_STEER, 0x1e4, 0x1c0000), 166 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1_PIPE_STEER, 0x1e4, 0x1c0000), 167 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13571357, 0x1c0000), 168 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x64206420, 0x1c0000), 169 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x2460246, 0x1c0000), 170 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x75317531, 0x1c0000), 171 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xc0d41183, 0x1c0000), 172 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_CHICKEN_BITS, 0x507d1c0, 0x1c0000), 173 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_CHICKEN_BITS, 0x507d1c0, 0x1c0000), 174 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_RB_WPTR_POLL_CNTL, 0x600100, 0x1c0000), 175 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_CREDITS, 0x3f7fff, 0x1c0000), 176 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_CREDITS, 0x3f7ebf, 0x1c0000), 177 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE0, 0x2e00000, 0x1c0000), 178 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE1, 0x1a078, 0x1c0000), 179 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE2, 0x0, 0x1c0000), 180 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE0, 0x0, 0x1c0000), 181 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE1, 0x12030, 0x1c0000), 182 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE2, 0x0, 0x1c0000), 183 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE0, 0x19041000, 0x1c0000), 184 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000), 185 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE0, 0x1e080000, 0x1c0000), 186 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000), 187 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_PRIORITY, 0x880, 0x1c0000), 188 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_PRIORITY, 0x8880, 0x1c0000), 189 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ARB_FINAL, 0x17, 0x1c0000), 190 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ARB_FINAL, 0x77, 0x1c0000), 191 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ENABLE, 0x00000001, 0x1c0000), 192 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ENABLE, 0x00000001, 0x1c0000), 193 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x20000, 0x1c0000), 194 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0c, 0x1c0000), 195 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xfffff, 0x1c0000), 196 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_MISC, 0x0091, 0x1c0000), 197 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_MISC, 0x0091, 0x1c0000), 198 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000), 199 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x00008500, 0x1c0000), 200 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0x00880007, 0x1c0000), 201 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regTD_CNTL, 0x00000001, 0x1c0000), 202 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000), 203 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 204 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000), 205 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 206 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000), 207 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 208 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000), 209 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 210 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000), 211 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x08200545, 0x1c0000), 212 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBMH_CP_PERFMON_CNTL, 0x00000000, 0x1c0000), 213 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCB_PERFCOUNTER0_SELECT1, 0x000fffff, 0x1c0000), 214 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_DEBUG_2, 0x00020000, 0x1c0000), 215 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_CPC_DEBUG, 0x00500010, 0x1c0000), 216 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0x1c0000), 217 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0x1c0000), 218 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0x1c0000), 219 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0x1c0000), 220 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x0000000f, 0x1c0000), 221 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0x1c0000), 222 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x0000600f, 0x1c0000), 223 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0x1c0000), 224 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0x1c0000), 225 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000), 226 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0x1c0000), 227 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x0000ffff, 0x1c0000), 228 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0x1c0000), 229 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0x1c0000), 230 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0x1c0000), 231 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0x1c0000), 232 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0x1c0000), 233 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000), 234 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0x1c0000), 235 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000), 236 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0x1c0000), 237 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x0003d000, 0x1c0000), 238 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x0003d7ff, 0x1c0000), 239 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x1c0000), 240 + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0x1c0000) 241 + }; 242 + 243 + static void program_imu_rlc_ram(struct amdgpu_device *adev, 244 + const struct imu_rlc_ram_golden *regs, 245 + const u32 array_size) 246 + { 247 + const struct imu_rlc_ram_golden *entry; 248 + u32 reg, data; 249 + int i; 250 + 251 + for (i = 0; i < array_size; ++i) { 252 + entry = &regs[i]; 253 + reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 254 + reg |= entry->addr_mask; 255 + data = entry->data; 256 + if (entry->reg == regGCMC_VM_AGP_BASE) 257 + data = 0x00ffffff; 258 + else if (entry->reg == regGCMC_VM_AGP_TOP) 259 + data = 0x0; 260 + else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE) 261 + data = adev->gmc.vram_start >> 24; 262 + else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP) 263 + data = adev->gmc.vram_end >> 24; 264 + 265 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); 266 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg); 267 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); 268 + } 269 + //Indicate the latest entry 270 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); 271 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); 272 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0); 273 + } 274 + 275 + static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev) 276 + { 277 + u32 reg_data; 278 + 279 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2); 280 + 281 + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 282 + case IP_VERSION(12, 0, 1): 283 + program_imu_rlc_ram(adev, imu_rlc_ram_golden_12_0_1, 284 + (const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1)); 285 + break; 286 + default: 287 + BUG(); 288 + break; 289 + } 290 + 291 + reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX); 292 + reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK; 293 + WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data); 294 + } 295 + 296 + const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs = { 297 + .init_microcode = imu_v12_0_init_microcode, 298 + .load_microcode = imu_v12_0_load_microcode, 299 + .setup_imu = imu_v12_0_setup, 300 + .start_imu = imu_v12_0_start, 301 + .program_rlc_ram = imu_v12_0_program_rlc_ram, 302 + .wait_for_reset_status = imu_v12_0_wait_for_reset_status, 303 + };
+30
drivers/gpu/drm/amd/amdgpu/imu_v12_0.h
··· 1 + /* 2 + * Copyright 2021 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + 24 + #ifndef __IMU_V12_0_H__ 25 + #define __IMU_V12_0_H__ 26 + 27 + extern const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs; 28 + 29 + #endif 30 +