clk: amlogic: remove unnecessary headers

+30 -1

drivers/clk/meson/a1-peripherals.c

··· 10 10 #include <linux/clk-provider.h> 11 11 #include <linux/mod_devicetable.h> 12 12 #include <linux/platform_device.h> 13 - #include "a1-peripherals.h" 14 13 #include "clk-dualdiv.h" 15 14 #include "clk-regmap.h" 16 15 #include "meson-clkc-utils.h" 17 16 18 17 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 18 + 19 + #define SYS_OSCIN_CTRL 0x0 20 + #define RTC_BY_OSCIN_CTRL0 0x4 21 + #define RTC_BY_OSCIN_CTRL1 0x8 22 + #define RTC_CTRL 0xc 23 + #define SYS_CLK_CTRL0 0x10 24 + #define SYS_CLK_EN0 0x1c 25 + #define SYS_CLK_EN1 0x20 26 + #define AXI_CLK_EN 0x24 27 + #define DSPA_CLK_EN 0x28 28 + #define DSPB_CLK_EN 0x2c 29 + #define DSPA_CLK_CTRL0 0x30 30 + #define DSPB_CLK_CTRL0 0x34 31 + #define CLK12_24_CTRL 0x38 32 + #define GEN_CLK_CTRL 0x3c 33 + #define SAR_ADC_CLK_CTRL 0xc0 34 + #define PWM_CLK_AB_CTRL 0xc4 35 + #define PWM_CLK_CD_CTRL 0xc8 36 + #define PWM_CLK_EF_CTRL 0xcc 37 + #define SPICC_CLK_CTRL 0xd0 38 + #define TS_CLK_CTRL 0xd4 39 + #define SPIFC_CLK_CTRL 0xd8 40 + #define USB_BUSCLK_CTRL 0xdc 41 + #define SD_EMMC_CLK_CTRL 0xe0 42 + #define CECA_CLK_CTRL0 0xe4 43 + #define CECA_CLK_CTRL1 0xe8 44 + #define CECB_CLK_CTRL0 0xec 45 + #define CECB_CLK_CTRL1 0xf0 46 + #define PSRAM_CLK_CTRL 0xf4 47 + #define DMC_CLK_CTRL 0xf8 19 48 20 49 static struct clk_regmap xtal_in = { 21 50 .data = &(struct clk_regmap_gate_data){

-46

drivers/clk/meson/a1-peripherals.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Amlogic A1 Peripherals Clock Controller internals 4 - * 5 - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 6 - * Author: Jian Hu <jian.hu@amlogic.com> 7 - * 8 - * Copyright (c) 2023, SberDevices. All Rights Reserved. 9 - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 10 - */ 11 - 12 - #ifndef __A1_PERIPHERALS_H 13 - #define __A1_PERIPHERALS_H 14 - 15 - /* peripherals clock controller register offset */ 16 - #define SYS_OSCIN_CTRL 0x0 17 - #define RTC_BY_OSCIN_CTRL0 0x4 18 - #define RTC_BY_OSCIN_CTRL1 0x8 19 - #define RTC_CTRL 0xc 20 - #define SYS_CLK_CTRL0 0x10 21 - #define SYS_CLK_EN0 0x1c 22 - #define SYS_CLK_EN1 0x20 23 - #define AXI_CLK_EN 0x24 24 - #define DSPA_CLK_EN 0x28 25 - #define DSPB_CLK_EN 0x2c 26 - #define DSPA_CLK_CTRL0 0x30 27 - #define DSPB_CLK_CTRL0 0x34 28 - #define CLK12_24_CTRL 0x38 29 - #define GEN_CLK_CTRL 0x3c 30 - #define SAR_ADC_CLK_CTRL 0xc0 31 - #define PWM_CLK_AB_CTRL 0xc4 32 - #define PWM_CLK_CD_CTRL 0xc8 33 - #define PWM_CLK_EF_CTRL 0xcc 34 - #define SPICC_CLK_CTRL 0xd0 35 - #define TS_CLK_CTRL 0xd4 36 - #define SPIFC_CLK_CTRL 0xd8 37 - #define USB_BUSCLK_CTRL 0xdc 38 - #define SD_EMMC_CLK_CTRL 0xe0 39 - #define CECA_CLK_CTRL0 0xe4 40 - #define CECA_CLK_CTRL1 0xe8 41 - #define CECB_CLK_CTRL0 0xec 42 - #define CECB_CLK_CTRL1 0xf0 43 - #define PSRAM_CLK_CTRL 0xf4 44 - #define DMC_CLK_CTRL 0xf8 45 - 46 - #endif /* __A1_PERIPHERALS_H */

+11 -1

drivers/clk/meson/a1-pll.c

··· 10 10 #include <linux/clk-provider.h> 11 11 #include <linux/mod_devicetable.h> 12 12 #include <linux/platform_device.h> 13 - #include "a1-pll.h" 13 + #include "clk-pll.h" 14 14 #include "clk-regmap.h" 15 15 #include "meson-clkc-utils.h" 16 + 17 + #define ANACTRL_FIXPLL_CTRL0 0x0 18 + #define ANACTRL_FIXPLL_CTRL1 0x4 19 + #define ANACTRL_FIXPLL_STS 0x14 20 + #define ANACTRL_HIFIPLL_CTRL0 0xc0 21 + #define ANACTRL_HIFIPLL_CTRL1 0xc4 22 + #define ANACTRL_HIFIPLL_CTRL2 0xc8 23 + #define ANACTRL_HIFIPLL_CTRL3 0xcc 24 + #define ANACTRL_HIFIPLL_CTRL4 0xd0 25 + #define ANACTRL_HIFIPLL_STS 0xd4 16 26 17 27 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> 18 28

-28

drivers/clk/meson/a1-pll.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Amlogic A1 PLL Clock Controller internals 4 - * 5 - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 6 - * Author: Jian Hu <jian.hu@amlogic.com> 7 - * 8 - * Copyright (c) 2023, SberDevices. All Rights Reserved. 9 - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 10 - */ 11 - 12 - #ifndef __A1_PLL_H 13 - #define __A1_PLL_H 14 - 15 - #include "clk-pll.h" 16 - 17 - /* PLL register offset */ 18 - #define ANACTRL_FIXPLL_CTRL0 0x0 19 - #define ANACTRL_FIXPLL_CTRL1 0x4 20 - #define ANACTRL_FIXPLL_STS 0x14 21 - #define ANACTRL_HIFIPLL_CTRL0 0xc0 22 - #define ANACTRL_HIFIPLL_CTRL1 0xc4 23 - #define ANACTRL_HIFIPLL_CTRL2 0xc8 24 - #define ANACTRL_HIFIPLL_CTRL3 0xcc 25 - #define ANACTRL_HIFIPLL_CTRL4 0xd0 26 - #define ANACTRL_HIFIPLL_STS 0xd4 27 - 28 - #endif /* __A1_PLL_H */

+55 -1

drivers/clk/meson/axg-audio.c

··· 16 16 #include <linux/slab.h> 17 17 18 18 #include "meson-clkc-utils.h" 19 - #include "axg-audio.h" 20 19 #include "clk-regmap.h" 21 20 #include "clk-phase.h" 22 21 #include "sclk-div.h" 23 22 24 23 #include <dt-bindings/clock/axg-audio-clkc.h> 24 + 25 + /* Audio clock register offsets */ 26 + #define AUDIO_CLK_GATE_EN 0x000 27 + #define AUDIO_MCLK_A_CTRL 0x004 28 + #define AUDIO_MCLK_B_CTRL 0x008 29 + #define AUDIO_MCLK_C_CTRL 0x00C 30 + #define AUDIO_MCLK_D_CTRL 0x010 31 + #define AUDIO_MCLK_E_CTRL 0x014 32 + #define AUDIO_MCLK_F_CTRL 0x018 33 + #define AUDIO_MST_PAD_CTRL0 0x01c 34 + #define AUDIO_MST_PAD_CTRL1 0x020 35 + #define AUDIO_SW_RESET 0x024 36 + #define AUDIO_MST_A_SCLK_CTRL0 0x040 37 + #define AUDIO_MST_A_SCLK_CTRL1 0x044 38 + #define AUDIO_MST_B_SCLK_CTRL0 0x048 39 + #define AUDIO_MST_B_SCLK_CTRL1 0x04C 40 + #define AUDIO_MST_C_SCLK_CTRL0 0x050 41 + #define AUDIO_MST_C_SCLK_CTRL1 0x054 42 + #define AUDIO_MST_D_SCLK_CTRL0 0x058 43 + #define AUDIO_MST_D_SCLK_CTRL1 0x05C 44 + #define AUDIO_MST_E_SCLK_CTRL0 0x060 45 + #define AUDIO_MST_E_SCLK_CTRL1 0x064 46 + #define AUDIO_MST_F_SCLK_CTRL0 0x068 47 + #define AUDIO_MST_F_SCLK_CTRL1 0x06C 48 + #define AUDIO_CLK_TDMIN_A_CTRL 0x080 49 + #define AUDIO_CLK_TDMIN_B_CTRL 0x084 50 + #define AUDIO_CLK_TDMIN_C_CTRL 0x088 51 + #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 52 + #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 53 + #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 54 + #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 55 + #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 56 + #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 57 + #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 58 + #define AUDIO_CLK_LOCKER_CTRL 0x0A8 59 + #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 60 + #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 61 + #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 62 + 63 + /* SM1 introduce new register and some shifts :( */ 64 + #define AUDIO_CLK_GATE_EN1 0x004 65 + #define AUDIO_SM1_MCLK_A_CTRL 0x008 66 + #define AUDIO_SM1_MCLK_B_CTRL 0x00C 67 + #define AUDIO_SM1_MCLK_C_CTRL 0x010 68 + #define AUDIO_SM1_MCLK_D_CTRL 0x014 69 + #define AUDIO_SM1_MCLK_E_CTRL 0x018 70 + #define AUDIO_SM1_MCLK_F_CTRL 0x01C 71 + #define AUDIO_SM1_MST_PAD_CTRL0 0x020 72 + #define AUDIO_SM1_MST_PAD_CTRL1 0x024 73 + #define AUDIO_SM1_SW_RESET0 0x028 74 + #define AUDIO_SM1_SW_RESET1 0x02C 75 + #define AUDIO_CLK81_CTRL 0x030 76 + #define AUDIO_CLK81_EN 0x034 77 + #define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 78 + #define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 25 79 26 80 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ 27 81 .data = &(struct clk_regmap_gate_data){ \

-70

drivers/clk/meson/axg-audio.h

··· 1 - /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 - /* 3 - * Copyright (c) 2018 BayLibre, SAS. 4 - * Author: Jerome Brunet <jbrunet@baylibre.com> 5 - */ 6 - 7 - #ifndef __AXG_AUDIO_CLKC_H 8 - #define __AXG_AUDIO_CLKC_H 9 - 10 - /* 11 - * Audio Clock register offsets 12 - * 13 - * Register offsets from the datasheet must be multiplied by 4 before 14 - * to get the right offset 15 - */ 16 - #define AUDIO_CLK_GATE_EN 0x000 17 - #define AUDIO_MCLK_A_CTRL 0x004 18 - #define AUDIO_MCLK_B_CTRL 0x008 19 - #define AUDIO_MCLK_C_CTRL 0x00C 20 - #define AUDIO_MCLK_D_CTRL 0x010 21 - #define AUDIO_MCLK_E_CTRL 0x014 22 - #define AUDIO_MCLK_F_CTRL 0x018 23 - #define AUDIO_MST_PAD_CTRL0 0x01c 24 - #define AUDIO_MST_PAD_CTRL1 0x020 25 - #define AUDIO_SW_RESET 0x024 26 - #define AUDIO_MST_A_SCLK_CTRL0 0x040 27 - #define AUDIO_MST_A_SCLK_CTRL1 0x044 28 - #define AUDIO_MST_B_SCLK_CTRL0 0x048 29 - #define AUDIO_MST_B_SCLK_CTRL1 0x04C 30 - #define AUDIO_MST_C_SCLK_CTRL0 0x050 31 - #define AUDIO_MST_C_SCLK_CTRL1 0x054 32 - #define AUDIO_MST_D_SCLK_CTRL0 0x058 33 - #define AUDIO_MST_D_SCLK_CTRL1 0x05C 34 - #define AUDIO_MST_E_SCLK_CTRL0 0x060 35 - #define AUDIO_MST_E_SCLK_CTRL1 0x064 36 - #define AUDIO_MST_F_SCLK_CTRL0 0x068 37 - #define AUDIO_MST_F_SCLK_CTRL1 0x06C 38 - #define AUDIO_CLK_TDMIN_A_CTRL 0x080 39 - #define AUDIO_CLK_TDMIN_B_CTRL 0x084 40 - #define AUDIO_CLK_TDMIN_C_CTRL 0x088 41 - #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 42 - #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 43 - #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 44 - #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 45 - #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 46 - #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 47 - #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 48 - #define AUDIO_CLK_LOCKER_CTRL 0x0A8 49 - #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 50 - #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 51 - #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 52 - 53 - /* SM1 introduce new register and some shifts :( */ 54 - #define AUDIO_CLK_GATE_EN1 0x004 55 - #define AUDIO_SM1_MCLK_A_CTRL 0x008 56 - #define AUDIO_SM1_MCLK_B_CTRL 0x00C 57 - #define AUDIO_SM1_MCLK_C_CTRL 0x010 58 - #define AUDIO_SM1_MCLK_D_CTRL 0x014 59 - #define AUDIO_SM1_MCLK_E_CTRL 0x018 60 - #define AUDIO_SM1_MCLK_F_CTRL 0x01C 61 - #define AUDIO_SM1_MST_PAD_CTRL0 0x020 62 - #define AUDIO_SM1_MST_PAD_CTRL1 0x024 63 - #define AUDIO_SM1_SW_RESET0 0x028 64 - #define AUDIO_SM1_SW_RESET1 0x02C 65 - #define AUDIO_CLK81_CTRL 0x030 66 - #define AUDIO_CLK81_EN 0x034 67 - #define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 68 - #define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 69 - 70 - #endif /*__AXG_AUDIO_CLKC_H */

+86 -1

drivers/clk/meson/axg.c

··· 18 18 #include "clk-regmap.h" 19 19 #include "clk-pll.h" 20 20 #include "clk-mpll.h" 21 - #include "axg.h" 22 21 #include "meson-eeclk.h" 23 22 24 23 #include <dt-bindings/clock/axg-clkc.h> 24 + 25 + #define HHI_GP0_PLL_CNTL 0x40 26 + #define HHI_GP0_PLL_CNTL2 0x44 27 + #define HHI_GP0_PLL_CNTL3 0x48 28 + #define HHI_GP0_PLL_CNTL4 0x4c 29 + #define HHI_GP0_PLL_CNTL5 0x50 30 + #define HHI_GP0_PLL_STS 0x54 31 + #define HHI_GP0_PLL_CNTL1 0x58 32 + #define HHI_HIFI_PLL_CNTL 0x80 33 + #define HHI_HIFI_PLL_CNTL2 0x84 34 + #define HHI_HIFI_PLL_CNTL3 0x88 35 + #define HHI_HIFI_PLL_CNTL4 0x8C 36 + #define HHI_HIFI_PLL_CNTL5 0x90 37 + #define HHI_HIFI_PLL_STS 0x94 38 + #define HHI_HIFI_PLL_CNTL1 0x98 39 + 40 + #define HHI_XTAL_DIVN_CNTL 0xbc 41 + #define HHI_GCLK2_MPEG0 0xc0 42 + #define HHI_GCLK2_MPEG1 0xc4 43 + #define HHI_GCLK2_MPEG2 0xc8 44 + #define HHI_GCLK2_OTHER 0xd0 45 + #define HHI_GCLK2_AO 0xd4 46 + #define HHI_PCIE_PLL_CNTL 0xd8 47 + #define HHI_PCIE_PLL_CNTL1 0xdC 48 + #define HHI_PCIE_PLL_CNTL2 0xe0 49 + #define HHI_PCIE_PLL_CNTL3 0xe4 50 + #define HHI_PCIE_PLL_CNTL4 0xe8 51 + #define HHI_PCIE_PLL_CNTL5 0xec 52 + #define HHI_PCIE_PLL_CNTL6 0xf0 53 + #define HHI_PCIE_PLL_STS 0xf4 54 + 55 + #define HHI_MEM_PD_REG0 0x100 56 + #define HHI_VPU_MEM_PD_REG0 0x104 57 + #define HHI_VIID_CLK_DIV 0x128 58 + #define HHI_VIID_CLK_CNTL 0x12c 59 + 60 + #define HHI_GCLK_MPEG0 0x140 61 + #define HHI_GCLK_MPEG1 0x144 62 + #define HHI_GCLK_MPEG2 0x148 63 + #define HHI_GCLK_OTHER 0x150 64 + #define HHI_GCLK_AO 0x154 65 + #define HHI_SYS_CPU_CLK_CNTL1 0x15c 66 + #define HHI_SYS_CPU_RESET_CNTL 0x160 67 + #define HHI_VID_CLK_DIV 0x164 68 + #define HHI_SPICC_HCLK_CNTL 0x168 69 + 70 + #define HHI_MPEG_CLK_CNTL 0x174 71 + #define HHI_VID_CLK_CNTL 0x17c 72 + #define HHI_TS_CLK_CNTL 0x190 73 + #define HHI_VID_CLK_CNTL2 0x194 74 + #define HHI_SYS_CPU_CLK_CNTL0 0x19c 75 + #define HHI_VID_PLL_CLK_DIV 0x1a0 76 + #define HHI_VPU_CLK_CNTL 0x1bC 77 + 78 + #define HHI_VAPBCLK_CNTL 0x1F4 79 + 80 + #define HHI_GEN_CLK_CNTL 0x228 81 + 82 + #define HHI_VDIN_MEAS_CLK_CNTL 0x250 83 + #define HHI_NAND_CLK_CNTL 0x25C 84 + #define HHI_SD_EMMC_CLK_CNTL 0x264 85 + 86 + #define HHI_MPLL_CNTL 0x280 87 + #define HHI_MPLL_CNTL2 0x284 88 + #define HHI_MPLL_CNTL3 0x288 89 + #define HHI_MPLL_CNTL4 0x28C 90 + #define HHI_MPLL_CNTL5 0x290 91 + #define HHI_MPLL_CNTL6 0x294 92 + #define HHI_MPLL_CNTL7 0x298 93 + #define HHI_MPLL_CNTL8 0x29C 94 + #define HHI_MPLL_CNTL9 0x2A0 95 + #define HHI_MPLL_CNTL10 0x2A4 96 + 97 + #define HHI_MPLL3_CNTL0 0x2E0 98 + #define HHI_MPLL3_CNTL1 0x2E4 99 + #define HHI_PLL_TOP_MISC 0x2E8 100 + 101 + #define HHI_SYS_PLL_CNTL1 0x2FC 102 + #define HHI_SYS_PLL_CNTL 0x300 103 + #define HHI_SYS_PLL_CNTL2 0x304 104 + #define HHI_SYS_PLL_CNTL3 0x308 105 + #define HHI_SYS_PLL_CNTL4 0x30c 106 + #define HHI_SYS_PLL_CNTL5 0x310 107 + #define HHI_SYS_PLL_STS 0x314 108 + #define HHI_DPLL_TOP_I 0x318 109 + #define HHI_DPLL_TOP2_I 0x31C 25 110 26 111 static struct clk_regmap axg_fixed_pll_dco = { 27 112 .data = &(struct meson_clk_pll_data){

-105

drivers/clk/meson/axg.h

··· 1 - /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 - /* 3 - * Copyright (c) 2016 AmLogic, Inc. 4 - * Author: Michael Turquette <mturquette@baylibre.com> 5 - * 6 - * Copyright (c) 2017 Amlogic, inc. 7 - * Author: Qiufang Dai <qiufang.dai@amlogic.com> 8 - * 9 - */ 10 - #ifndef __AXG_H 11 - #define __AXG_H 12 - 13 - /* 14 - * Clock controller register offsets 15 - * 16 - * Register offsets from the data sheet must be multiplied by 4 before 17 - * adding them to the base address to get the right value. 18 - */ 19 - #define HHI_GP0_PLL_CNTL 0x40 20 - #define HHI_GP0_PLL_CNTL2 0x44 21 - #define HHI_GP0_PLL_CNTL3 0x48 22 - #define HHI_GP0_PLL_CNTL4 0x4c 23 - #define HHI_GP0_PLL_CNTL5 0x50 24 - #define HHI_GP0_PLL_STS 0x54 25 - #define HHI_GP0_PLL_CNTL1 0x58 26 - #define HHI_HIFI_PLL_CNTL 0x80 27 - #define HHI_HIFI_PLL_CNTL2 0x84 28 - #define HHI_HIFI_PLL_CNTL3 0x88 29 - #define HHI_HIFI_PLL_CNTL4 0x8C 30 - #define HHI_HIFI_PLL_CNTL5 0x90 31 - #define HHI_HIFI_PLL_STS 0x94 32 - #define HHI_HIFI_PLL_CNTL1 0x98 33 - 34 - #define HHI_XTAL_DIVN_CNTL 0xbc 35 - #define HHI_GCLK2_MPEG0 0xc0 36 - #define HHI_GCLK2_MPEG1 0xc4 37 - #define HHI_GCLK2_MPEG2 0xc8 38 - #define HHI_GCLK2_OTHER 0xd0 39 - #define HHI_GCLK2_AO 0xd4 40 - #define HHI_PCIE_PLL_CNTL 0xd8 41 - #define HHI_PCIE_PLL_CNTL1 0xdC 42 - #define HHI_PCIE_PLL_CNTL2 0xe0 43 - #define HHI_PCIE_PLL_CNTL3 0xe4 44 - #define HHI_PCIE_PLL_CNTL4 0xe8 45 - #define HHI_PCIE_PLL_CNTL5 0xec 46 - #define HHI_PCIE_PLL_CNTL6 0xf0 47 - #define HHI_PCIE_PLL_STS 0xf4 48 - 49 - #define HHI_MEM_PD_REG0 0x100 50 - #define HHI_VPU_MEM_PD_REG0 0x104 51 - #define HHI_VIID_CLK_DIV 0x128 52 - #define HHI_VIID_CLK_CNTL 0x12c 53 - 54 - #define HHI_GCLK_MPEG0 0x140 55 - #define HHI_GCLK_MPEG1 0x144 56 - #define HHI_GCLK_MPEG2 0x148 57 - #define HHI_GCLK_OTHER 0x150 58 - #define HHI_GCLK_AO 0x154 59 - #define HHI_SYS_CPU_CLK_CNTL1 0x15c 60 - #define HHI_SYS_CPU_RESET_CNTL 0x160 61 - #define HHI_VID_CLK_DIV 0x164 62 - #define HHI_SPICC_HCLK_CNTL 0x168 63 - 64 - #define HHI_MPEG_CLK_CNTL 0x174 65 - #define HHI_VID_CLK_CNTL 0x17c 66 - #define HHI_TS_CLK_CNTL 0x190 67 - #define HHI_VID_CLK_CNTL2 0x194 68 - #define HHI_SYS_CPU_CLK_CNTL0 0x19c 69 - #define HHI_VID_PLL_CLK_DIV 0x1a0 70 - #define HHI_VPU_CLK_CNTL 0x1bC 71 - 72 - #define HHI_VAPBCLK_CNTL 0x1F4 73 - 74 - #define HHI_GEN_CLK_CNTL 0x228 75 - 76 - #define HHI_VDIN_MEAS_CLK_CNTL 0x250 77 - #define HHI_NAND_CLK_CNTL 0x25C 78 - #define HHI_SD_EMMC_CLK_CNTL 0x264 79 - 80 - #define HHI_MPLL_CNTL 0x280 81 - #define HHI_MPLL_CNTL2 0x284 82 - #define HHI_MPLL_CNTL3 0x288 83 - #define HHI_MPLL_CNTL4 0x28C 84 - #define HHI_MPLL_CNTL5 0x290 85 - #define HHI_MPLL_CNTL6 0x294 86 - #define HHI_MPLL_CNTL7 0x298 87 - #define HHI_MPLL_CNTL8 0x29C 88 - #define HHI_MPLL_CNTL9 0x2A0 89 - #define HHI_MPLL_CNTL10 0x2A4 90 - 91 - #define HHI_MPLL3_CNTL0 0x2E0 92 - #define HHI_MPLL3_CNTL1 0x2E4 93 - #define HHI_PLL_TOP_MISC 0x2E8 94 - 95 - #define HHI_SYS_PLL_CNTL1 0x2FC 96 - #define HHI_SYS_PLL_CNTL 0x300 97 - #define HHI_SYS_PLL_CNTL2 0x304 98 - #define HHI_SYS_PLL_CNTL3 0x308 99 - #define HHI_SYS_PLL_CNTL4 0x30c 100 - #define HHI_SYS_PLL_CNTL5 0x310 101 - #define HHI_SYS_PLL_STS 0x314 102 - #define HHI_DPLL_TOP_I 0x318 103 - #define HHI_DPLL_TOP2_I 0x31C 104 - 105 - #endif /* __AXG_H */

+110 -1

drivers/clk/meson/g12a.c

··· 24 24 #include "vid-pll-div.h" 25 25 #include "vclk.h" 26 26 #include "meson-eeclk.h" 27 - #include "g12a.h" 28 27 29 28 #include <dt-bindings/clock/g12a-clkc.h> 29 + 30 + #define HHI_MIPI_CNTL0 0x000 31 + #define HHI_MIPI_CNTL1 0x004 32 + #define HHI_MIPI_CNTL2 0x008 33 + #define HHI_MIPI_STS 0x00c 34 + #define HHI_GP0_PLL_CNTL0 0x040 35 + #define HHI_GP0_PLL_CNTL1 0x044 36 + #define HHI_GP0_PLL_CNTL2 0x048 37 + #define HHI_GP0_PLL_CNTL3 0x04c 38 + #define HHI_GP0_PLL_CNTL4 0x050 39 + #define HHI_GP0_PLL_CNTL5 0x054 40 + #define HHI_GP0_PLL_CNTL6 0x058 41 + #define HHI_GP0_PLL_STS 0x05c 42 + #define HHI_GP1_PLL_CNTL0 0x060 43 + #define HHI_GP1_PLL_CNTL1 0x064 44 + #define HHI_GP1_PLL_CNTL2 0x068 45 + #define HHI_GP1_PLL_CNTL3 0x06c 46 + #define HHI_GP1_PLL_CNTL4 0x070 47 + #define HHI_GP1_PLL_CNTL5 0x074 48 + #define HHI_GP1_PLL_CNTL6 0x078 49 + #define HHI_GP1_PLL_STS 0x07c 50 + #define HHI_PCIE_PLL_CNTL0 0x098 51 + #define HHI_PCIE_PLL_CNTL1 0x09c 52 + #define HHI_PCIE_PLL_CNTL2 0x0a0 53 + #define HHI_PCIE_PLL_CNTL3 0x0a4 54 + #define HHI_PCIE_PLL_CNTL4 0x0a8 55 + #define HHI_PCIE_PLL_CNTL5 0x0ac 56 + #define HHI_PCIE_PLL_STS 0x0b8 57 + #define HHI_HIFI_PLL_CNTL0 0x0d8 58 + #define HHI_HIFI_PLL_CNTL1 0x0dc 59 + #define HHI_HIFI_PLL_CNTL2 0x0e0 60 + #define HHI_HIFI_PLL_CNTL3 0x0e4 61 + #define HHI_HIFI_PLL_CNTL4 0x0e8 62 + #define HHI_HIFI_PLL_CNTL5 0x0ec 63 + #define HHI_HIFI_PLL_CNTL6 0x0f0 64 + #define HHI_VIID_CLK_DIV 0x128 65 + #define HHI_VIID_CLK_CNTL 0x12c 66 + #define HHI_GCLK_MPEG0 0x140 67 + #define HHI_GCLK_MPEG1 0x144 68 + #define HHI_GCLK_MPEG2 0x148 69 + #define HHI_GCLK_OTHER 0x150 70 + #define HHI_GCLK_OTHER2 0x154 71 + #define HHI_SYS_CPU_CLK_CNTL1 0x15c 72 + #define HHI_VID_CLK_DIV 0x164 73 + #define HHI_MPEG_CLK_CNTL 0x174 74 + #define HHI_AUD_CLK_CNTL 0x178 75 + #define HHI_VID_CLK_CNTL 0x17c 76 + #define HHI_TS_CLK_CNTL 0x190 77 + #define HHI_VID_CLK_CNTL2 0x194 78 + #define HHI_SYS_CPU_CLK_CNTL0 0x19c 79 + #define HHI_VID_PLL_CLK_DIV 0x1a0 80 + #define HHI_MALI_CLK_CNTL 0x1b0 81 + #define HHI_VPU_CLKC_CNTL 0x1b4 82 + #define HHI_VPU_CLK_CNTL 0x1bc 83 + #define HHI_ISP_CLK_CNTL 0x1c0 84 + #define HHI_NNA_CLK_CNTL 0x1c8 85 + #define HHI_HDMI_CLK_CNTL 0x1cc 86 + #define HHI_VDEC_CLK_CNTL 0x1e0 87 + #define HHI_VDEC2_CLK_CNTL 0x1e4 88 + #define HHI_VDEC3_CLK_CNTL 0x1e8 89 + #define HHI_VDEC4_CLK_CNTL 0x1ec 90 + #define HHI_HDCP22_CLK_CNTL 0x1f0 91 + #define HHI_VAPBCLK_CNTL 0x1f4 92 + #define HHI_SYS_CPUB_CLK_CNTL1 0x200 93 + #define HHI_SYS_CPUB_CLK_CNTL 0x208 94 + #define HHI_VPU_CLKB_CNTL 0x20c 95 + #define HHI_SYS_CPU_CLK_CNTL2 0x210 96 + #define HHI_SYS_CPU_CLK_CNTL3 0x214 97 + #define HHI_SYS_CPU_CLK_CNTL4 0x218 98 + #define HHI_SYS_CPU_CLK_CNTL5 0x21c 99 + #define HHI_SYS_CPU_CLK_CNTL6 0x220 100 + #define HHI_GEN_CLK_CNTL 0x228 101 + #define HHI_VDIN_MEAS_CLK_CNTL 0x250 102 + #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 103 + #define HHI_NAND_CLK_CNTL 0x25c 104 + #define HHI_SD_EMMC_CLK_CNTL 0x264 105 + #define HHI_MPLL_CNTL0 0x278 106 + #define HHI_MPLL_CNTL1 0x27c 107 + #define HHI_MPLL_CNTL2 0x280 108 + #define HHI_MPLL_CNTL3 0x284 109 + #define HHI_MPLL_CNTL4 0x288 110 + #define HHI_MPLL_CNTL5 0x28c 111 + #define HHI_MPLL_CNTL6 0x290 112 + #define HHI_MPLL_CNTL7 0x294 113 + #define HHI_MPLL_CNTL8 0x298 114 + #define HHI_FIX_PLL_CNTL0 0x2a0 115 + #define HHI_FIX_PLL_CNTL1 0x2a4 116 + #define HHI_FIX_PLL_CNTL3 0x2ac 117 + #define HHI_SYS_PLL_CNTL0 0x2f4 118 + #define HHI_SYS_PLL_CNTL1 0x2f8 119 + #define HHI_SYS_PLL_CNTL2 0x2fc 120 + #define HHI_SYS_PLL_CNTL3 0x300 121 + #define HHI_SYS_PLL_CNTL4 0x304 122 + #define HHI_SYS_PLL_CNTL5 0x308 123 + #define HHI_SYS_PLL_CNTL6 0x30c 124 + #define HHI_HDMI_PLL_CNTL0 0x320 125 + #define HHI_HDMI_PLL_CNTL1 0x324 126 + #define HHI_HDMI_PLL_CNTL2 0x328 127 + #define HHI_HDMI_PLL_CNTL3 0x32c 128 + #define HHI_HDMI_PLL_CNTL4 0x330 129 + #define HHI_HDMI_PLL_CNTL5 0x334 130 + #define HHI_HDMI_PLL_CNTL6 0x338 131 + #define HHI_SPICC_CLK_CNTL 0x3dc 132 + #define HHI_SYS1_PLL_CNTL0 0x380 133 + #define HHI_SYS1_PLL_CNTL1 0x384 134 + #define HHI_SYS1_PLL_CNTL2 0x388 135 + #define HHI_SYS1_PLL_CNTL3 0x38c 136 + #define HHI_SYS1_PLL_CNTL4 0x390 137 + #define HHI_SYS1_PLL_CNTL5 0x394 138 + #define HHI_SYS1_PLL_CNTL6 0x398 30 139 31 140 static struct clk_regmap g12a_fixed_pll_dco = { 32 141 .data = &(struct meson_clk_pll_data){

-130

drivers/clk/meson/g12a.h

··· 1 - /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 - /* 3 - * Copyright (c) 2016 Amlogic, Inc. 4 - * Author: Michael Turquette <mturquette@baylibre.com> 5 - * 6 - * Copyright (c) 2018 Amlogic, inc. 7 - * Author: Qiufang Dai <qiufang.dai@amlogic.com> 8 - * Author: Jian Hu <jian.hu@amlogic.com> 9 - * 10 - */ 11 - #ifndef __G12A_H 12 - #define __G12A_H 13 - 14 - /* 15 - * Clock controller register offsets 16 - * 17 - * Register offsets from the data sheet must be multiplied by 4 before 18 - * adding them to the base address to get the right value. 19 - */ 20 - #define HHI_MIPI_CNTL0 0x000 21 - #define HHI_MIPI_CNTL1 0x004 22 - #define HHI_MIPI_CNTL2 0x008 23 - #define HHI_MIPI_STS 0x00C 24 - #define HHI_GP0_PLL_CNTL0 0x040 25 - #define HHI_GP0_PLL_CNTL1 0x044 26 - #define HHI_GP0_PLL_CNTL2 0x048 27 - #define HHI_GP0_PLL_CNTL3 0x04C 28 - #define HHI_GP0_PLL_CNTL4 0x050 29 - #define HHI_GP0_PLL_CNTL5 0x054 30 - #define HHI_GP0_PLL_CNTL6 0x058 31 - #define HHI_GP0_PLL_STS 0x05C 32 - #define HHI_GP1_PLL_CNTL0 0x060 33 - #define HHI_GP1_PLL_CNTL1 0x064 34 - #define HHI_GP1_PLL_CNTL2 0x068 35 - #define HHI_GP1_PLL_CNTL3 0x06C 36 - #define HHI_GP1_PLL_CNTL4 0x070 37 - #define HHI_GP1_PLL_CNTL5 0x074 38 - #define HHI_GP1_PLL_CNTL6 0x078 39 - #define HHI_GP1_PLL_STS 0x07C 40 - #define HHI_PCIE_PLL_CNTL0 0x098 41 - #define HHI_PCIE_PLL_CNTL1 0x09C 42 - #define HHI_PCIE_PLL_CNTL2 0x0A0 43 - #define HHI_PCIE_PLL_CNTL3 0x0A4 44 - #define HHI_PCIE_PLL_CNTL4 0x0A8 45 - #define HHI_PCIE_PLL_CNTL5 0x0AC 46 - #define HHI_PCIE_PLL_STS 0x0B8 47 - #define HHI_HIFI_PLL_CNTL0 0x0D8 48 - #define HHI_HIFI_PLL_CNTL1 0x0DC 49 - #define HHI_HIFI_PLL_CNTL2 0x0E0 50 - #define HHI_HIFI_PLL_CNTL3 0x0E4 51 - #define HHI_HIFI_PLL_CNTL4 0x0E8 52 - #define HHI_HIFI_PLL_CNTL5 0x0EC 53 - #define HHI_HIFI_PLL_CNTL6 0x0F0 54 - #define HHI_VIID_CLK_DIV 0x128 55 - #define HHI_VIID_CLK_CNTL 0x12C 56 - #define HHI_GCLK_MPEG0 0x140 57 - #define HHI_GCLK_MPEG1 0x144 58 - #define HHI_GCLK_MPEG2 0x148 59 - #define HHI_GCLK_OTHER 0x150 60 - #define HHI_GCLK_OTHER2 0x154 61 - #define HHI_SYS_CPU_CLK_CNTL1 0x15c 62 - #define HHI_VID_CLK_DIV 0x164 63 - #define HHI_MPEG_CLK_CNTL 0x174 64 - #define HHI_AUD_CLK_CNTL 0x178 65 - #define HHI_VID_CLK_CNTL 0x17c 66 - #define HHI_TS_CLK_CNTL 0x190 67 - #define HHI_VID_CLK_CNTL2 0x194 68 - #define HHI_SYS_CPU_CLK_CNTL0 0x19c 69 - #define HHI_VID_PLL_CLK_DIV 0x1A0 70 - #define HHI_MALI_CLK_CNTL 0x1b0 71 - #define HHI_VPU_CLKC_CNTL 0x1b4 72 - #define HHI_VPU_CLK_CNTL 0x1bC 73 - #define HHI_ISP_CLK_CNTL 0x1C0 74 - #define HHI_NNA_CLK_CNTL 0x1C8 75 - #define HHI_HDMI_CLK_CNTL 0x1CC 76 - #define HHI_VDEC_CLK_CNTL 0x1E0 77 - #define HHI_VDEC2_CLK_CNTL 0x1E4 78 - #define HHI_VDEC3_CLK_CNTL 0x1E8 79 - #define HHI_VDEC4_CLK_CNTL 0x1EC 80 - #define HHI_HDCP22_CLK_CNTL 0x1F0 81 - #define HHI_VAPBCLK_CNTL 0x1F4 82 - #define HHI_SYS_CPUB_CLK_CNTL1 0x200 83 - #define HHI_SYS_CPUB_CLK_CNTL 0x208 84 - #define HHI_VPU_CLKB_CNTL 0x20C 85 - #define HHI_SYS_CPU_CLK_CNTL2 0x210 86 - #define HHI_SYS_CPU_CLK_CNTL3 0x214 87 - #define HHI_SYS_CPU_CLK_CNTL4 0x218 88 - #define HHI_SYS_CPU_CLK_CNTL5 0x21c 89 - #define HHI_SYS_CPU_CLK_CNTL6 0x220 90 - #define HHI_GEN_CLK_CNTL 0x228 91 - #define HHI_VDIN_MEAS_CLK_CNTL 0x250 92 - #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 93 - #define HHI_NAND_CLK_CNTL 0x25C 94 - #define HHI_SD_EMMC_CLK_CNTL 0x264 95 - #define HHI_MPLL_CNTL0 0x278 96 - #define HHI_MPLL_CNTL1 0x27C 97 - #define HHI_MPLL_CNTL2 0x280 98 - #define HHI_MPLL_CNTL3 0x284 99 - #define HHI_MPLL_CNTL4 0x288 100 - #define HHI_MPLL_CNTL5 0x28c 101 - #define HHI_MPLL_CNTL6 0x290 102 - #define HHI_MPLL_CNTL7 0x294 103 - #define HHI_MPLL_CNTL8 0x298 104 - #define HHI_FIX_PLL_CNTL0 0x2A0 105 - #define HHI_FIX_PLL_CNTL1 0x2A4 106 - #define HHI_FIX_PLL_CNTL3 0x2AC 107 - #define HHI_SYS_PLL_CNTL0 0x2f4 108 - #define HHI_SYS_PLL_CNTL1 0x2f8 109 - #define HHI_SYS_PLL_CNTL2 0x2fc 110 - #define HHI_SYS_PLL_CNTL3 0x300 111 - #define HHI_SYS_PLL_CNTL4 0x304 112 - #define HHI_SYS_PLL_CNTL5 0x308 113 - #define HHI_SYS_PLL_CNTL6 0x30c 114 - #define HHI_HDMI_PLL_CNTL0 0x320 115 - #define HHI_HDMI_PLL_CNTL1 0x324 116 - #define HHI_HDMI_PLL_CNTL2 0x328 117 - #define HHI_HDMI_PLL_CNTL3 0x32c 118 - #define HHI_HDMI_PLL_CNTL4 0x330 119 - #define HHI_HDMI_PLL_CNTL5 0x334 120 - #define HHI_HDMI_PLL_CNTL6 0x338 121 - #define HHI_SPICC_CLK_CNTL 0x3dc 122 - #define HHI_SYS1_PLL_CNTL0 0x380 123 - #define HHI_SYS1_PLL_CNTL1 0x384 124 - #define HHI_SYS1_PLL_CNTL2 0x388 125 - #define HHI_SYS1_PLL_CNTL3 0x38c 126 - #define HHI_SYS1_PLL_CNTL4 0x390 127 - #define HHI_SYS1_PLL_CNTL5 0x394 128 - #define HHI_SYS1_PLL_CNTL6 0x398 129 - 130 - #endif /* __G12A_H */

+98 -1

drivers/clk/meson/gxbb.c

··· 10 10 #include <linux/platform_device.h> 11 11 #include <linux/module.h> 12 12 13 - #include "gxbb.h" 14 13 #include "clk-regmap.h" 15 14 #include "clk-pll.h" 16 15 #include "clk-mpll.h" ··· 17 18 #include "vid-pll-div.h" 18 19 19 20 #include <dt-bindings/clock/gxbb-clkc.h> 21 + 22 + #define SCR 0x2c 23 + #define TIMEOUT_VALUE 0x3c 24 + 25 + #define HHI_GP0_PLL_CNTL 0x40 26 + #define HHI_GP0_PLL_CNTL2 0x44 27 + #define HHI_GP0_PLL_CNTL3 0x48 28 + #define HHI_GP0_PLL_CNTL4 0x4c 29 + #define HHI_GP0_PLL_CNTL5 0x50 30 + #define HHI_GP0_PLL_CNTL1 0x58 31 + 32 + #define HHI_XTAL_DIVN_CNTL 0xbc 33 + #define HHI_TIMER90K 0xec 34 + 35 + #define HHI_MEM_PD_REG0 0x100 36 + #define HHI_MEM_PD_REG1 0x104 37 + #define HHI_VPU_MEM_PD_REG1 0x108 38 + #define HHI_VIID_CLK_DIV 0x128 39 + #define HHI_VIID_CLK_CNTL 0x12c 40 + 41 + #define HHI_GCLK_MPEG0 0x140 42 + #define HHI_GCLK_MPEG1 0x144 43 + #define HHI_GCLK_MPEG2 0x148 44 + #define HHI_GCLK_OTHER 0x150 45 + #define HHI_GCLK_AO 0x154 46 + #define HHI_SYS_OSCIN_CNTL 0x158 47 + #define HHI_SYS_CPU_CLK_CNTL1 0x15c 48 + #define HHI_SYS_CPU_RESET_CNTL 0x160 49 + #define HHI_VID_CLK_DIV 0x164 50 + 51 + #define HHI_MPEG_CLK_CNTL 0x174 52 + #define HHI_AUD_CLK_CNTL 0x178 53 + #define HHI_VID_CLK_CNTL 0x17c 54 + #define HHI_AUD_CLK_CNTL2 0x190 55 + #define HHI_VID_CLK_CNTL2 0x194 56 + #define HHI_SYS_CPU_CLK_CNTL0 0x19c 57 + #define HHI_VID_PLL_CLK_DIV 0x1a0 58 + #define HHI_AUD_CLK_CNTL3 0x1a4 59 + #define HHI_MALI_CLK_CNTL 0x1b0 60 + #define HHI_VPU_CLK_CNTL 0x1bc 61 + 62 + #define HHI_HDMI_CLK_CNTL 0x1cc 63 + #define HHI_VDEC_CLK_CNTL 0x1e0 64 + #define HHI_VDEC2_CLK_CNTL 0x1e4 65 + #define HHI_VDEC3_CLK_CNTL 0x1e8 66 + #define HHI_VDEC4_CLK_CNTL 0x1ec 67 + #define HHI_HDCP22_CLK_CNTL 0x1f0 68 + #define HHI_VAPBCLK_CNTL 0x1f4 69 + 70 + #define HHI_VPU_CLKB_CNTL 0x20c 71 + #define HHI_USB_CLK_CNTL 0x220 72 + #define HHI_32K_CLK_CNTL 0x224 73 + #define HHI_GEN_CLK_CNTL 0x228 74 + 75 + #define HHI_PCM_CLK_CNTL 0x258 76 + #define HHI_NAND_CLK_CNTL 0x25c 77 + #define HHI_SD_EMMC_CLK_CNTL 0x264 78 + 79 + #define HHI_MPLL_CNTL 0x280 80 + #define HHI_MPLL_CNTL2 0x284 81 + #define HHI_MPLL_CNTL3 0x288 82 + #define HHI_MPLL_CNTL4 0x28c 83 + #define HHI_MPLL_CNTL5 0x290 84 + #define HHI_MPLL_CNTL6 0x294 85 + #define HHI_MPLL_CNTL7 0x298 86 + #define HHI_MPLL_CNTL8 0x29c 87 + #define HHI_MPLL_CNTL9 0x2a0 88 + #define HHI_MPLL_CNTL10 0x2a4 89 + 90 + #define HHI_MPLL3_CNTL0 0x2e0 91 + #define HHI_MPLL3_CNTL1 0x2e4 92 + #define HHI_VDAC_CNTL0 0x2f4 93 + #define HHI_VDAC_CNTL1 0x2f8 94 + 95 + #define HHI_SYS_PLL_CNTL 0x300 96 + #define HHI_SYS_PLL_CNTL2 0x304 97 + #define HHI_SYS_PLL_CNTL3 0x308 98 + #define HHI_SYS_PLL_CNTL4 0x30c 99 + #define HHI_SYS_PLL_CNTL5 0x310 100 + #define HHI_DPLL_TOP_I 0x318 101 + #define HHI_DPLL_TOP2_I 0x31c 102 + #define HHI_HDMI_PLL_CNTL 0x320 103 + #define HHI_HDMI_PLL_CNTL2 0x324 104 + #define HHI_HDMI_PLL_CNTL3 0x328 105 + #define HHI_HDMI_PLL_CNTL4 0x32c 106 + #define HHI_HDMI_PLL_CNTL5 0x330 107 + #define HHI_HDMI_PLL_CNTL6 0x334 108 + #define HHI_HDMI_PLL_CNTL_I 0x338 109 + #define HHI_HDMI_PLL_CNTL7 0x33c 110 + 111 + #define HHI_HDMI_PHY_CNTL0 0x3a0 112 + #define HHI_HDMI_PHY_CNTL1 0x3a4 113 + #define HHI_HDMI_PHY_CNTL2 0x3a8 114 + #define HHI_HDMI_PHY_CNTL3 0x3ac 115 + 116 + #define HHI_VID_LOCK_CLK_CNTL 0x3c8 117 + #define HHI_BT656_CLK_CNTL 0x3d4 118 + #define HHI_SAR_CLK_CNTL 0x3d8 20 119 21 120 static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 22 121 PLL_PARAMS(32, 1),

-115

drivers/clk/meson/gxbb.h

··· 1 - /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 - /* 3 - * Copyright (c) 2016 AmLogic, Inc. 4 - * Author: Michael Turquette <mturquette@baylibre.com> 5 - */ 6 - 7 - #ifndef __GXBB_H 8 - #define __GXBB_H 9 - 10 - /* 11 - * Clock controller register offsets 12 - * 13 - * Register offsets from the data sheet are listed in comment blocks below. 14 - * Those offsets must be multiplied by 4 before adding them to the base address 15 - * to get the right value 16 - */ 17 - #define SCR 0x2C /* 0x0b offset in data sheet */ 18 - #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ 19 - 20 - #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ 21 - #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ 22 - #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ 23 - #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ 24 - #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ 25 - #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ 26 - 27 - #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ 28 - #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ 29 - 30 - #define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ 31 - #define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ 32 - #define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ 33 - #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ 34 - #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ 35 - 36 - #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 37 - #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 38 - #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 39 - #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 40 - #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 41 - #define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ 42 - #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 43 - #define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ 44 - #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ 45 - 46 - #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 47 - #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ 48 - #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 49 - #define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ 50 - #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ 51 - #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 52 - #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ 53 - #define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ 54 - #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ 55 - #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ 56 - 57 - #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ 58 - #define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ 59 - #define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ 60 - #define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ 61 - #define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ 62 - #define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ 63 - #define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ 64 - 65 - #define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ 66 - #define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ 67 - #define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ 68 - #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ 69 - 70 - #define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ 71 - #define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ 72 - #define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ 73 - 74 - #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 75 - #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 76 - #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 77 - #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 78 - #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 79 - #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 80 - #define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */ 81 - #define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */ 82 - #define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */ 83 - #define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */ 84 - 85 - #define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ 86 - #define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ 87 - #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ 88 - #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ 89 - 90 - #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 91 - #define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ 92 - #define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ 93 - #define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ 94 - #define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ 95 - #define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ 96 - #define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ 97 - #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 98 - #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ 99 - #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ 100 - #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ 101 - #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ 102 - #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ 103 - #define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ 104 - #define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ 105 - 106 - #define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ 107 - #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ 108 - #define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ 109 - #define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ 110 - 111 - #define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ 112 - #define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ 113 - #define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ 114 - 115 - #endif /* __GXBB_H */

+66 -1

drivers/clk/meson/meson8b.c

··· 16 16 #include <linux/slab.h> 17 17 #include <linux/regmap.h> 18 18 19 - #include "meson8b.h" 20 19 #include "clk-regmap.h" 21 20 #include "meson-clkc-utils.h" 22 21 #include "clk-pll.h" ··· 23 24 24 25 #include <dt-bindings/clock/meson8b-clkc.h> 25 26 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 27 + 28 + /* 29 + * Clock controller register offsets 30 + * 31 + * Register offsets from the HardKernel[0] data sheet must be multiplied 32 + * by 4 before adding them to the base address to get the right value 33 + * 34 + * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 35 + */ 36 + #define HHI_GP_PLL_CNTL 0x40 37 + #define HHI_GP_PLL_CNTL2 0x44 38 + #define HHI_GP_PLL_CNTL3 0x48 39 + #define HHI_GP_PLL_CNTL4 0x4C 40 + #define HHI_GP_PLL_CNTL5 0x50 41 + #define HHI_VIID_CLK_DIV 0x128 42 + #define HHI_VIID_CLK_CNTL 0x12c 43 + #define HHI_GCLK_MPEG0 0x140 44 + #define HHI_GCLK_MPEG1 0x144 45 + #define HHI_GCLK_MPEG2 0x148 46 + #define HHI_GCLK_OTHER 0x150 47 + #define HHI_GCLK_AO 0x154 48 + #define HHI_SYS_CPU_CLK_CNTL1 0x15c 49 + #define HHI_VID_CLK_DIV 0x164 50 + #define HHI_MPEG_CLK_CNTL 0x174 51 + #define HHI_AUD_CLK_CNTL 0x178 52 + #define HHI_VID_CLK_CNTL 0x17c 53 + #define HHI_AUD_CLK_CNTL2 0x190 54 + #define HHI_VID_CLK_CNTL2 0x194 55 + #define HHI_VID_DIVIDER_CNTL 0x198 56 + #define HHI_SYS_CPU_CLK_CNTL0 0x19c 57 + #define HHI_MALI_CLK_CNTL 0x1b0 58 + #define HHI_VPU_CLK_CNTL 0x1bc 59 + #define HHI_HDMI_CLK_CNTL 0x1cc 60 + #define HHI_VDEC_CLK_CNTL 0x1e0 61 + #define HHI_VDEC2_CLK_CNTL 0x1e4 62 + #define HHI_VDEC3_CLK_CNTL 0x1e8 63 + #define HHI_NAND_CLK_CNTL 0x25c 64 + #define HHI_MPLL_CNTL 0x280 65 + #define HHI_SYS_PLL_CNTL 0x300 66 + #define HHI_VID_PLL_CNTL 0x320 67 + #define HHI_VID_PLL_CNTL2 0x324 68 + #define HHI_VID_PLL_CNTL3 0x328 69 + #define HHI_VID_PLL_CNTL4 0x32c 70 + #define HHI_VID_PLL_CNTL5 0x330 71 + #define HHI_VID_PLL_CNTL6 0x334 72 + #define HHI_VID2_PLL_CNTL 0x380 73 + #define HHI_VID2_PLL_CNTL2 0x384 74 + #define HHI_VID2_PLL_CNTL3 0x388 75 + #define HHI_VID2_PLL_CNTL4 0x38c 76 + #define HHI_VID2_PLL_CNTL5 0x390 77 + #define HHI_VID2_PLL_CNTL6 0x394 78 + 79 + /* 80 + * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 81 + * confirm these are the same for the S805. 82 + */ 83 + #define HHI_MPLL_CNTL 0x280 84 + #define HHI_MPLL_CNTL2 0x284 85 + #define HHI_MPLL_CNTL3 0x288 86 + #define HHI_MPLL_CNTL4 0x28c 87 + #define HHI_MPLL_CNTL5 0x290 88 + #define HHI_MPLL_CNTL6 0x294 89 + #define HHI_MPLL_CNTL7 0x298 90 + #define HHI_MPLL_CNTL8 0x29c 91 + #define HHI_MPLL_CNTL9 0x2a0 92 + #define HHI_MPLL_CNTL10 0x2a4 26 93 27 94 struct meson8b_clk_reset { 28 95 struct reset_controller_dev reset;

-80

drivers/clk/meson/meson8b.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Copyright (c) 2015 Endless Mobile, Inc. 4 - * Author: Carlo Caione <carlo@endlessm.com> 5 - * 6 - * Copyright (c) 2016 BayLibre, Inc. 7 - * Michael Turquette <mturquette@baylibre.com> 8 - */ 9 - 10 - #ifndef __MESON8B_H 11 - #define __MESON8B_H 12 - 13 - /* 14 - * Clock controller register offsets 15 - * 16 - * Register offsets from the HardKernel[0] data sheet are listed in comment 17 - * blocks below. Those offsets must be multiplied by 4 before adding them to 18 - * the base address to get the right value 19 - * 20 - * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 21 - */ 22 - #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ 23 - #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ 24 - #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ 25 - #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */ 26 - #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ 27 - #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ 28 - #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ 29 - #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 30 - #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 31 - #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 32 - #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 33 - #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 34 - #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 35 - #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ 36 - #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 37 - #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ 38 - #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 39 - #define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ 40 - #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ 41 - #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 42 - #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 43 - #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ 44 - #define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */ 45 - #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ 46 - #define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */ 47 - #define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */ 48 - #define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */ 49 - #define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ 50 - #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 51 - #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 52 - #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 53 - #define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ 54 - #define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ 55 - #define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */ 56 - #define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ 57 - #define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ 58 - #define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */ 59 - #define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */ 60 - #define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */ 61 - #define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */ 62 - #define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */ 63 - #define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */ 64 - 65 - /* 66 - * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 67 - * confirm these are the same for the S805. 68 - */ 69 - #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 70 - #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 71 - #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 72 - #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 73 - #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 74 - #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 75 - #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 76 - #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 77 - #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 78 - #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 79 - 80 - #endif /* __MESON8B_H */

+46 -1

drivers/clk/meson/s4-peripherals.c

··· 13 13 #include "clk-regmap.h" 14 14 #include "vid-pll-div.h" 15 15 #include "clk-dualdiv.h" 16 - #include "s4-peripherals.h" 17 16 #include "meson-clkc-utils.h" 18 17 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> 18 + 19 + #define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 20 + #define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c 21 + #define CLKCTRL_RTC_CTRL 0x010 22 + #define CLKCTRL_SYS_CLK_CTRL0 0x040 23 + #define CLKCTRL_SYS_CLK_EN0_REG0 0x044 24 + #define CLKCTRL_SYS_CLK_EN0_REG1 0x048 25 + #define CLKCTRL_SYS_CLK_EN0_REG2 0x04c 26 + #define CLKCTRL_SYS_CLK_EN0_REG3 0x050 27 + #define CLKCTRL_CECA_CTRL0 0x088 28 + #define CLKCTRL_CECA_CTRL1 0x08c 29 + #define CLKCTRL_CECB_CTRL0 0x090 30 + #define CLKCTRL_CECB_CTRL1 0x094 31 + #define CLKCTRL_SC_CLK_CTRL 0x098 32 + #define CLKCTRL_CLK12_24_CTRL 0x0a8 33 + #define CLKCTRL_VID_CLK_CTRL 0x0c0 34 + #define CLKCTRL_VID_CLK_CTRL2 0x0c4 35 + #define CLKCTRL_VID_CLK_DIV 0x0c8 36 + #define CLKCTRL_VIID_CLK_DIV 0x0cc 37 + #define CLKCTRL_VIID_CLK_CTRL 0x0d0 38 + #define CLKCTRL_HDMI_CLK_CTRL 0x0e0 39 + #define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 40 + #define CLKCTRL_VPU_CLK_CTRL 0x0e8 41 + #define CLKCTRL_VPU_CLKB_CTRL 0x0ec 42 + #define CLKCTRL_VPU_CLKC_CTRL 0x0f0 43 + #define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 44 + #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 45 + #define CLKCTRL_VAPBCLK_CTRL 0x0fc 46 + #define CLKCTRL_HDCP22_CTRL 0x100 47 + #define CLKCTRL_VDEC_CLK_CTRL 0x140 48 + #define CLKCTRL_VDEC2_CLK_CTRL 0x144 49 + #define CLKCTRL_VDEC3_CLK_CTRL 0x148 50 + #define CLKCTRL_VDEC4_CLK_CTRL 0x14c 51 + #define CLKCTRL_TS_CLK_CTRL 0x158 52 + #define CLKCTRL_MALI_CLK_CTRL 0x15c 53 + #define CLKCTRL_NAND_CLK_CTRL 0x168 54 + #define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c 55 + #define CLKCTRL_SPICC_CLK_CTRL 0x174 56 + #define CLKCTRL_GEN_CLK_CTRL 0x178 57 + #define CLKCTRL_SAR_CLK_CTRL 0x17c 58 + #define CLKCTRL_PWM_CLK_AB_CTRL 0x180 59 + #define CLKCTRL_PWM_CLK_CD_CTRL 0x184 60 + #define CLKCTRL_PWM_CLK_EF_CTRL 0x188 61 + #define CLKCTRL_PWM_CLK_GH_CTRL 0x18c 62 + #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 63 + #define CLKCTRL_DEMOD_CLK_CTRL 0x200 19 64 20 65 static struct clk_regmap s4_rtc_32k_by_oscin_clkin = { 21 66 .data = &(struct clk_regmap_gate_data){

-56

drivers/clk/meson/s4-peripherals.h

··· 1 - /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 - /* 3 - * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved 4 - * Author: Yu Tu <yu.tu@amlogic.com> 5 - */ 6 - 7 - #ifndef __MESON_S4_PERIPHERALS_H__ 8 - #define __MESON_S4_PERIPHERALS_H__ 9 - 10 - #define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 11 - #define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c 12 - #define CLKCTRL_RTC_CTRL 0x010 13 - #define CLKCTRL_SYS_CLK_CTRL0 0x040 14 - #define CLKCTRL_SYS_CLK_EN0_REG0 0x044 15 - #define CLKCTRL_SYS_CLK_EN0_REG1 0x048 16 - #define CLKCTRL_SYS_CLK_EN0_REG2 0x04c 17 - #define CLKCTRL_SYS_CLK_EN0_REG3 0x050 18 - #define CLKCTRL_CECA_CTRL0 0x088 19 - #define CLKCTRL_CECA_CTRL1 0x08c 20 - #define CLKCTRL_CECB_CTRL0 0x090 21 - #define CLKCTRL_CECB_CTRL1 0x094 22 - #define CLKCTRL_SC_CLK_CTRL 0x098 23 - #define CLKCTRL_CLK12_24_CTRL 0x0a8 24 - #define CLKCTRL_VID_CLK_CTRL 0x0c0 25 - #define CLKCTRL_VID_CLK_CTRL2 0x0c4 26 - #define CLKCTRL_VID_CLK_DIV 0x0c8 27 - #define CLKCTRL_VIID_CLK_DIV 0x0cc 28 - #define CLKCTRL_VIID_CLK_CTRL 0x0d0 29 - #define CLKCTRL_HDMI_CLK_CTRL 0x0e0 30 - #define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 31 - #define CLKCTRL_VPU_CLK_CTRL 0x0e8 32 - #define CLKCTRL_VPU_CLKB_CTRL 0x0ec 33 - #define CLKCTRL_VPU_CLKC_CTRL 0x0f0 34 - #define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 35 - #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 36 - #define CLKCTRL_VAPBCLK_CTRL 0x0fc 37 - #define CLKCTRL_HDCP22_CTRL 0x100 38 - #define CLKCTRL_VDEC_CLK_CTRL 0x140 39 - #define CLKCTRL_VDEC2_CLK_CTRL 0x144 40 - #define CLKCTRL_VDEC3_CLK_CTRL 0x148 41 - #define CLKCTRL_VDEC4_CLK_CTRL 0x14c 42 - #define CLKCTRL_TS_CLK_CTRL 0x158 43 - #define CLKCTRL_MALI_CLK_CTRL 0x15c 44 - #define CLKCTRL_NAND_CLK_CTRL 0x168 45 - #define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c 46 - #define CLKCTRL_SPICC_CLK_CTRL 0x174 47 - #define CLKCTRL_GEN_CLK_CTRL 0x178 48 - #define CLKCTRL_SAR_CLK_CTRL 0x17c 49 - #define CLKCTRL_PWM_CLK_AB_CTRL 0x180 50 - #define CLKCTRL_PWM_CLK_CD_CTRL 0x184 51 - #define CLKCTRL_PWM_CLK_EF_CTRL 0x188 52 - #define CLKCTRL_PWM_CLK_GH_CTRL 0x18c 53 - #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 54 - #define CLKCTRL_DEMOD_CLK_CTRL 0x200 55 - 56 - #endif /* __MESON_S4_PERIPHERALS_H__ */

+28 -1

drivers/clk/meson/s4-pll.c

··· 13 13 #include "clk-mpll.h" 14 14 #include "clk-pll.h" 15 15 #include "clk-regmap.h" 16 - #include "s4-pll.h" 17 16 #include "meson-clkc-utils.h" 18 17 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h> 18 + 19 + #define ANACTRL_FIXPLL_CTRL0 0x040 20 + #define ANACTRL_FIXPLL_CTRL1 0x044 21 + #define ANACTRL_FIXPLL_CTRL3 0x04c 22 + #define ANACTRL_GP0PLL_CTRL0 0x080 23 + #define ANACTRL_GP0PLL_CTRL1 0x084 24 + #define ANACTRL_GP0PLL_CTRL2 0x088 25 + #define ANACTRL_GP0PLL_CTRL3 0x08c 26 + #define ANACTRL_GP0PLL_CTRL4 0x090 27 + #define ANACTRL_GP0PLL_CTRL5 0x094 28 + #define ANACTRL_GP0PLL_CTRL6 0x098 29 + #define ANACTRL_HIFIPLL_CTRL0 0x100 30 + #define ANACTRL_HIFIPLL_CTRL1 0x104 31 + #define ANACTRL_HIFIPLL_CTRL2 0x108 32 + #define ANACTRL_HIFIPLL_CTRL3 0x10c 33 + #define ANACTRL_HIFIPLL_CTRL4 0x110 34 + #define ANACTRL_HIFIPLL_CTRL5 0x114 35 + #define ANACTRL_HIFIPLL_CTRL6 0x118 36 + #define ANACTRL_MPLL_CTRL0 0x180 37 + #define ANACTRL_MPLL_CTRL1 0x184 38 + #define ANACTRL_MPLL_CTRL2 0x188 39 + #define ANACTRL_MPLL_CTRL3 0x18c 40 + #define ANACTRL_MPLL_CTRL4 0x190 41 + #define ANACTRL_MPLL_CTRL5 0x194 42 + #define ANACTRL_MPLL_CTRL6 0x198 43 + #define ANACTRL_MPLL_CTRL7 0x19c 44 + #define ANACTRL_MPLL_CTRL8 0x1a0 45 + #define ANACTRL_HDMIPLL_CTRL0 0x1c0 19 46 20 47 /* 21 48 * These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.

-38

drivers/clk/meson/s4-pll.h

··· 1 - /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 - /* 3 - * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved 4 - * Author: Yu Tu <yu.tu@amlogic.com> 5 - */ 6 - 7 - #ifndef __MESON_S4_PLL_H__ 8 - #define __MESON_S4_PLL_H__ 9 - 10 - #define ANACTRL_FIXPLL_CTRL0 0x040 11 - #define ANACTRL_FIXPLL_CTRL1 0x044 12 - #define ANACTRL_FIXPLL_CTRL3 0x04c 13 - #define ANACTRL_GP0PLL_CTRL0 0x080 14 - #define ANACTRL_GP0PLL_CTRL1 0x084 15 - #define ANACTRL_GP0PLL_CTRL2 0x088 16 - #define ANACTRL_GP0PLL_CTRL3 0x08c 17 - #define ANACTRL_GP0PLL_CTRL4 0x090 18 - #define ANACTRL_GP0PLL_CTRL5 0x094 19 - #define ANACTRL_GP0PLL_CTRL6 0x098 20 - #define ANACTRL_HIFIPLL_CTRL0 0x100 21 - #define ANACTRL_HIFIPLL_CTRL1 0x104 22 - #define ANACTRL_HIFIPLL_CTRL2 0x108 23 - #define ANACTRL_HIFIPLL_CTRL3 0x10c 24 - #define ANACTRL_HIFIPLL_CTRL4 0x110 25 - #define ANACTRL_HIFIPLL_CTRL5 0x114 26 - #define ANACTRL_HIFIPLL_CTRL6 0x118 27 - #define ANACTRL_MPLL_CTRL0 0x180 28 - #define ANACTRL_MPLL_CTRL1 0x184 29 - #define ANACTRL_MPLL_CTRL2 0x188 30 - #define ANACTRL_MPLL_CTRL3 0x18c 31 - #define ANACTRL_MPLL_CTRL4 0x190 32 - #define ANACTRL_MPLL_CTRL5 0x194 33 - #define ANACTRL_MPLL_CTRL6 0x198 34 - #define ANACTRL_MPLL_CTRL7 0x19c 35 - #define ANACTRL_MPLL_CTRL8 0x1a0 36 - #define ANACTRL_HDMIPLL_CTRL0 0x1c0 37 - 38 - #endif /* __MESON_S4_PLL_H__ */