Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: Suspend: Fix dependency of ARCH_SUSPEND_POSSIBLE
ARM: SAMSUNG: Fix CPU idmask
ARM: EXYNOS4: Fix addruart macro
ARM: EXYNOS4: Fix smsc9215 irq polarity on SMDKC210
ARM: EXYNOS4: Fix smsc9215 irq polarity on SMDKV310
ARM: EXYNOS4: Fix build warning on regarding SATA_AHCI_PLATFORM
ARM: S5PV210: Remove duplicated inclusion
ARM: S5PV210: Fix security engine interrupt names
ARM: S5P64X0: Fix iodesc array size for S5P6450

+21 -16
+1
arch/arm/Kconfig
··· 2009 source "kernel/power/Kconfig" 2010 2011 config ARCH_SUSPEND_POSSIBLE 2012 def_bool y 2013 2014 endmenu
··· 2009 source "kernel/power/Kconfig" 2010 2011 config ARCH_SUSPEND_POSSIBLE 2012 + depends on !ARCH_S5P64X0 && !ARCH_S5P6442 2013 def_bool y 2014 2015 endmenu
+6 -1
arch/arm/mach-exynos4/Kconfig
··· 20 help 21 Use MCT (Multi Core Timer) as kernel timers 22 23 config EXYNOS4_DEV_PD 24 bool 25 help ··· 139 select S3C_DEV_HSMMC 140 select S3C_DEV_HSMMC2 141 select S3C_DEV_HSMMC3 142 select EXYNOS4_DEV_SYSMMU 143 select EXYNOS4_SETUP_SDHCI 144 - select SATA_AHCI_PLATFORM 145 help 146 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 147
··· 20 help 21 Use MCT (Multi Core Timer) as kernel timers 22 23 + config EXYNOS4_DEV_AHCI 24 + bool 25 + help 26 + Compile in platform device definitions for AHCI 27 + 28 config EXYNOS4_DEV_PD 29 bool 30 help ··· 134 select S3C_DEV_HSMMC 135 select S3C_DEV_HSMMC2 136 select S3C_DEV_HSMMC3 137 + select EXYNOS4_DEV_AHCI 138 select EXYNOS4_DEV_SYSMMU 139 select EXYNOS4_SETUP_SDHCI 140 help 141 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 142
+1 -1
arch/arm/mach-exynos4/Makefile
··· 39 # device support 40 41 obj-y += dev-audio.o 42 obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 43 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 44 ··· 54 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 55 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o 56 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 57 - obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o
··· 39 # device support 40 41 obj-y += dev-audio.o 42 + obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 43 obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 44 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 45 ··· 53 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 54 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o 55 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+2 -2
arch/arm/mach-exynos4/include/mach/debug-macro.S
··· 21 */ 22 23 .macro addruart, rp, rv 24 - ldreq \rp, = S3C_PA_UART 25 - ldrne \rv, = S3C_VA_UART 26 #if CONFIG_DEBUG_S3C_UART != 0 27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) 28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
··· 21 */ 22 23 .macro addruart, rp, rv 24 + ldr \rp, = S3C_PA_UART 25 + ldr \rv, = S3C_VA_UART 26 #if CONFIG_DEBUG_S3C_UART != 0 27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) 28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+1 -1
arch/arm/mach-exynos4/mach-smdkc210.c
··· 125 }; 126 127 static struct smsc911x_platform_config smsc9215_config = { 128 - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, 129 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 130 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, 131 .phy_interface = PHY_INTERFACE_MODE_MII,
··· 125 }; 126 127 static struct smsc911x_platform_config smsc9215_config = { 128 + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 129 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 130 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, 131 .phy_interface = PHY_INTERFACE_MODE_MII,
+1 -1
arch/arm/mach-exynos4/mach-smdkv310.c
··· 127 }; 128 129 static struct smsc911x_platform_config smsc9215_config = { 130 - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, 131 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 132 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, 133 .phy_interface = PHY_INTERFACE_MODE_MII,
··· 127 }; 128 129 static struct smsc911x_platform_config smsc9215_config = { 130 + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 131 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 132 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, 133 .phy_interface = PHY_INTERFACE_MODE_MII,
+1 -1
arch/arm/mach-s5p64x0/cpu.c
··· 119 s3c_adc_setname("s3c64xx-adc"); 120 121 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 122 - iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc)); 123 } 124 125 /*
··· 119 s3c_adc_setname("s3c64xx-adc"); 120 121 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 122 + iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); 123 } 124 125 /*
+3 -3
arch/arm/mach-s5pv210/include/mach/irqs.h
··· 99 #define IRQ_TC IRQ_PENDN 100 #define IRQ_KEYPAD S5P_IRQ_VIC2(25) 101 #define IRQ_CG S5P_IRQ_VIC2(26) 102 - #define IRQ_SEC S5P_IRQ_VIC2(27) 103 - #define IRQ_SECRX S5P_IRQ_VIC2(28) 104 - #define IRQ_SECTX S5P_IRQ_VIC2(29) 105 #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) 106 #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) 107
··· 99 #define IRQ_TC IRQ_PENDN 100 #define IRQ_KEYPAD S5P_IRQ_VIC2(25) 101 #define IRQ_CG S5P_IRQ_VIC2(26) 102 + #define IRQ_SSS_INT S5P_IRQ_VIC2(27) 103 + #define IRQ_SSS_HASH S5P_IRQ_VIC2(28) 104 + #define IRQ_PCM2 S5P_IRQ_VIC2(29) 105 #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) 106 #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) 107
-1
arch/arm/mach-s5pv210/mach-smdkv210.c
··· 44 #include <plat/keypad.h> 45 #include <plat/pm.h> 46 #include <plat/fb.h> 47 - #include <plat/gpio-cfg.h> 48 #include <plat/s5p-time.h> 49 50 /* Following are default values for UCON, ULCON and UFCON UART registers */
··· 44 #include <plat/keypad.h> 45 #include <plat/pm.h> 46 #include <plat/fb.h> 47 #include <plat/s5p-time.h> 48 49 /* Following are default values for UCON, ULCON and UFCON UART registers */
+4 -4
arch/arm/plat-s5p/cpu.c
··· 39 static struct cpu_table cpu_ids[] __initdata = { 40 { 41 .idcode = 0x56440100, 42 - .idmask = 0xffffff00, 43 .map_io = s5p6440_map_io, 44 .init_clocks = s5p6440_init_clocks, 45 .init_uarts = s5p6440_init_uarts, ··· 47 .name = name_s5p6440, 48 }, { 49 .idcode = 0x36442000, 50 - .idmask = 0xffffff00, 51 .map_io = s5p6442_map_io, 52 .init_clocks = s5p6442_init_clocks, 53 .init_uarts = s5p6442_init_uarts, ··· 55 .name = name_s5p6442, 56 }, { 57 .idcode = 0x36450000, 58 - .idmask = 0xffffff00, 59 .map_io = s5p6450_map_io, 60 .init_clocks = s5p6450_init_clocks, 61 .init_uarts = s5p6450_init_uarts, ··· 79 .name = name_s5pv210, 80 }, { 81 .idcode = 0x43210000, 82 - .idmask = 0xfffff000, 83 .map_io = exynos4_map_io, 84 .init_clocks = exynos4_init_clocks, 85 .init_uarts = exynos4_init_uarts,
··· 39 static struct cpu_table cpu_ids[] __initdata = { 40 { 41 .idcode = 0x56440100, 42 + .idmask = 0xfffff000, 43 .map_io = s5p6440_map_io, 44 .init_clocks = s5p6440_init_clocks, 45 .init_uarts = s5p6440_init_uarts, ··· 47 .name = name_s5p6440, 48 }, { 49 .idcode = 0x36442000, 50 + .idmask = 0xfffff000, 51 .map_io = s5p6442_map_io, 52 .init_clocks = s5p6442_init_clocks, 53 .init_uarts = s5p6442_init_uarts, ··· 55 .name = name_s5p6442, 56 }, { 57 .idcode = 0x36450000, 58 + .idmask = 0xfffff000, 59 .map_io = s5p6450_map_io, 60 .init_clocks = s5p6450_init_clocks, 61 .init_uarts = s5p6450_init_uarts, ··· 79 .name = name_s5pv210, 80 }, { 81 .idcode = 0x43210000, 82 + .idmask = 0xfffe0000, 83 .map_io = exynos4_map_io, 84 .init_clocks = exynos4_init_clocks, 85 .init_uarts = exynos4_init_uarts,
+1 -1
arch/arm/plat-samsung/init.c
··· 36 unsigned int count) 37 { 38 for (; count != 0; count--, tab++) { 39 - if ((idcode & tab->idmask) == tab->idcode) 40 return tab; 41 } 42
··· 36 unsigned int count) 37 { 38 for (; count != 0; count--, tab++) { 39 + if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) 40 return tab; 41 } 42