tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amd/display: Updates for OTG and DCCG clocks

Use DTBCLK for valid pixel clock generation

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Samson Tam and committed by
Alex Deucher 327f79d7 0c9ed604

+9 -1
+4 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
··· 514 514 type DIG_UPDATE_POSITION_X;\ 515 515 type DIG_UPDATE_POSITION_Y;\ 516 516 type OTG_H_TIMING_DIV_MODE;\ 517 - type OTG_H_TIMING_DIV_MODE_MANUAL;\ 518 517 type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ 519 518 type OTG_CRC_DSC_MODE;\ 520 519 type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ ··· 521 522 type OTG_CRC_DATA_FORMAT;\ 522 523 type OTG_V_TOTAL_LAST_USED_BY_DRR; 523 524 525 + #define TG_REG_FIELD_LIST_DCN3_2(type) \ 526 + type OTG_H_TIMING_DIV_MODE_MANUAL; 524 527 525 528 struct dcn_optc_shift { 526 529 TG_REG_FIELD_LIST(uint8_t) 530 + TG_REG_FIELD_LIST_DCN3_2(uint8_t) 527 531 }; 528 532 529 533 struct dcn_optc_mask { 530 534 TG_REG_FIELD_LIST(uint32_t) 535 + TG_REG_FIELD_LIST_DCN3_2(uint32_t) 531 536 }; 532 537 533 538 struct optc {
+4
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
··· 45 45 SR(PHYDSYMCLK_CLOCK_CNTL),\ 46 46 SR(PHYESYMCLK_CLOCK_CNTL),\ 47 47 SR(DPSTREAMCLK_CNTL),\ 48 + SR(HDMISTREAMCLK_CNTL),\ 48 49 SR(SYMCLK32_SE_CNTL),\ 49 50 SR(SYMCLK32_LE_CNTL),\ 50 51 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ ··· 99 98 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\ 100 99 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\ 101 100 DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\ 101 + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\ 102 + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\ 102 103 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ 103 104 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ 104 105 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ ··· 146 143 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ 147 144 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ 148 145 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ 146 + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ 149 147 DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh) 150 148 151 149
+1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
··· 245 245 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ 246 246 SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ 247 247 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ 248 + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ 248 249 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 249 250 SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) 250 251