clk: axi-clkgen: replace ARCH dependencies with driver deps

The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).

Signed-off-by: Dragos Bogdan <[e-mail]>
Signed-off-by: Alexandru Ardelean <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Acked-by: Michal Simek <[e-mail]>
Reviewed-by: Moritz Fischer <[e-mail]>
Signed-off-by: Stephen Boyd <[e-mail]>

drivers/clk/Kconfig

···
 
 config COMMON_CLK_AXI_CLKGEN
 	tristate "AXI clkgen driver"
-	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
+	depends on HAS_IOMEM || COMPILE_TEST
+	depends on OF
 	help
 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
 	  FPGAs. It is commonly used in Analog Devices' reference designs.