PCI: pciehp: cleanup register and field definitions

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Clean up register definitions related to PCI Express Hot plug.

- Add register definitions into include/linux/pci_regs.h, and use
them instead of pciehp's locally definied register definitions.
- Remove pciehp's locally defined register definitions
- Remove unused register definitions in pciehp.
- Some minor cleanups.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

authored by

Kenji Kaneshige and committed by

Jesse Barnes 17 years ago 322162a7 67f65338

+156 -236

2 changed files

expand all

drivers

pci

hotplug

pciehp_hpc.c

include

linux

pci_regs.h

+99 -229

drivers/pci/hotplug/pciehp_hpc.c

··· 42 42 43 43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); 44 44 45 - struct ctrl_reg { 46 - u8 cap_id; 47 - u8 nxt_ptr; 48 - u16 cap_reg; 49 - u32 dev_cap; 50 - u16 dev_ctrl; 51 - u16 dev_status; 52 - u32 lnk_cap; 53 - u16 lnk_ctrl; 54 - u16 lnk_status; 55 - u32 slot_cap; 56 - u16 slot_ctrl; 57 - u16 slot_status; 58 - u16 root_ctrl; 59 - u16 rsvp; 60 - u32 root_status; 61 - } __attribute__ ((packed)); 62 - 63 - /* offsets to the controller registers based on the above structure layout */ 64 - enum ctrl_offsets { 65 - PCIECAPID = offsetof(struct ctrl_reg, cap_id), 66 - NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), 67 - CAPREG = offsetof(struct ctrl_reg, cap_reg), 68 - DEVCAP = offsetof(struct ctrl_reg, dev_cap), 69 - DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), 70 - DEVSTATUS = offsetof(struct ctrl_reg, dev_status), 71 - LNKCAP = offsetof(struct ctrl_reg, lnk_cap), 72 - LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), 73 - LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), 74 - SLOTCAP = offsetof(struct ctrl_reg, slot_cap), 75 - SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), 76 - SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), 77 - ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), 78 - ROOTSTATUS = offsetof(struct ctrl_reg, root_status), 79 - }; 80 - 81 45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 82 46 { 83 47 struct pci_dev *dev = ctrl->pci_dev; ··· 66 102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value); 67 103 } 68 104 69 - /* Field definitions in PCI Express Capabilities Register */ 70 - #define CAP_VER 0x000F 71 - #define DEV_PORT_TYPE 0x00F0 72 - #define SLOT_IMPL 0x0100 73 - #define MSG_NUM 0x3E00 74 - 75 - /* Device or Port Type */ 76 - #define NAT_ENDPT 0x00 77 - #define LEG_ENDPT 0x01 78 - #define ROOT_PORT 0x04 79 - #define UP_STREAM 0x05 80 - #define DN_STREAM 0x06 81 - #define PCIE_PCI_BRDG 0x07 82 - #define PCI_PCIE_BRDG 0x10 83 - 84 - /* Field definitions in Device Capabilities Register */ 85 - #define DATTN_BUTTN_PRSN 0x1000 86 - #define DATTN_LED_PRSN 0x2000 87 - #define DPWR_LED_PRSN 0x4000 88 - 89 - /* Field definitions in Link Capabilities Register */ 90 - #define MAX_LNK_SPEED 0x000F 91 - #define MAX_LNK_WIDTH 0x03F0 92 - #define LINK_ACTIVE_REPORTING 0x00100000 93 - 94 - /* Link Width Encoding */ 95 - #define LNK_X1 0x01 96 - #define LNK_X2 0x02 97 - #define LNK_X4 0x04 98 - #define LNK_X8 0x08 99 - #define LNK_X12 0x0C 100 - #define LNK_X16 0x10 101 - #define LNK_X32 0x20 102 - 103 - /*Field definitions of Link Status Register */ 104 - #define LNK_SPEED 0x000F 105 - #define NEG_LINK_WD 0x03F0 106 - #define LNK_TRN_ERR 0x0400 107 - #define LNK_TRN 0x0800 108 - #define SLOT_CLK_CONF 0x1000 109 - #define LINK_ACTIVE 0x2000 110 - 111 - /* Field definitions in Slot Capabilities Register */ 112 - #define ATTN_BUTTN_PRSN 0x00000001 113 - #define PWR_CTRL_PRSN 0x00000002 114 - #define MRL_SENS_PRSN 0x00000004 115 - #define ATTN_LED_PRSN 0x00000008 116 - #define PWR_LED_PRSN 0x00000010 117 - #define HP_SUPR_RM_SUP 0x00000020 118 - #define HP_CAP 0x00000040 119 - #define SLOT_PWR_VALUE 0x000003F8 120 - #define SLOT_PWR_LIMIT 0x00000C00 121 - #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ 122 - 123 - /* Field definitions in Slot Control Register */ 124 - #define ATTN_BUTTN_ENABLE 0x0001 125 - #define PWR_FAULT_DETECT_ENABLE 0x0002 126 - #define MRL_DETECT_ENABLE 0x0004 127 - #define PRSN_DETECT_ENABLE 0x0008 128 - #define CMD_CMPL_INTR_ENABLE 0x0010 129 - #define HP_INTR_ENABLE 0x0020 130 - #define ATTN_LED_CTRL 0x00C0 131 - #define PWR_LED_CTRL 0x0300 132 - #define PWR_CTRL 0x0400 133 - #define EMI_CTRL 0x0800 134 - 135 - /* Attention indicator and Power indicator states */ 136 - #define LED_ON 0x01 137 - #define LED_BLINK 0x10 138 - #define LED_OFF 0x11 139 - 140 105 /* Power Control Command */ 141 106 #define POWER_ON 0 142 - #define POWER_OFF 0x0400 143 - 144 - /* EMI Status defines */ 145 - #define EMI_DISENGAGED 0 146 - #define EMI_ENGAGED 1 147 - 148 - /* Field definitions in Slot Status Register */ 149 - #define ATTN_BUTTN_PRESSED 0x0001 150 - #define PWR_FAULT_DETECTED 0x0002 151 - #define MRL_SENS_CHANGED 0x0004 152 - #define PRSN_DETECT_CHANGED 0x0008 153 - #define CMD_COMPLETED 0x0010 154 - #define MRL_STATE 0x0020 155 - #define PRSN_STATE 0x0040 156 - #define EMI_STATE 0x0080 157 - #define EMI_STATUS_BIT 7 107 + #define POWER_OFF PCI_EXP_SLTCTL_PCC 158 108 159 109 static irqreturn_t pcie_isr(int irq, void *dev_id); 160 110 static void start_int_poll_timer(struct controller *ctrl, int sec); ··· 131 253 static int pcie_poll_cmd(struct controller *ctrl) 132 254 { 133 255 u16 slot_status; 134 - int timeout = 1000; 256 + int err, timeout = 1000; 135 257 136 - if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { 137 - if (slot_status & CMD_COMPLETED) { 138 - pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); 139 - return 1; 140 - } 258 + err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 259 + if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 260 + pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 261 + return 1; 141 262 } 142 263 while (timeout > 0) { 143 264 msleep(10); 144 265 timeout -= 10; 145 - if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { 146 - if (slot_status & CMD_COMPLETED) { 147 - pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); 148 - return 1; 149 - } 266 + err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 267 + if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 268 + pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 269 + return 1; 150 270 } 151 271 } 152 272 return 0; /* timeout */ ··· 178 302 179 303 mutex_lock(&ctrl->ctrl_lock); 180 304 181 - retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 305 + retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 182 306 if (retval) { 183 307 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 184 308 __func__); 185 309 goto out; 186 310 } 187 311 188 - if (slot_status & CMD_COMPLETED) { 312 + if (slot_status & PCI_EXP_SLTSTA_CC) { 189 313 if (!ctrl->no_cmd_complete) { 190 314 /* 191 315 * After 1 sec and CMD_COMPLETED still not set, just ··· 208 332 } 209 333 } 210 334 211 - retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 335 + retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 212 336 if (retval) { 213 337 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 214 338 goto out; ··· 218 342 slot_ctrl |= (cmd & mask); 219 343 ctrl->cmd_busy = 1; 220 344 smp_mb(); 221 - retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); 345 + retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); 222 346 if (retval) 223 347 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); 224 348 ··· 232 356 * completed interrupt is not enabled, we need to poll 233 357 * command completed event. 234 358 */ 235 - if (!(slot_ctrl & HP_INTR_ENABLE) || 236 - !(slot_ctrl & CMD_CMPL_INTR_ENABLE)) 359 + if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || 360 + !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) 237 361 poll = 1; 238 362 pcie_wait_cmd(ctrl, poll); 239 363 } ··· 246 370 { 247 371 u16 link_status; 248 372 249 - if (pciehp_readw(ctrl, LNKSTATUS, &link_status)) 373 + if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) 250 374 return 0; 251 - return !!(link_status & LINK_ACTIVE); 375 + return !!(link_status & PCI_EXP_LNKSTA_DLLLA); 252 376 } 253 377 254 378 static void pcie_wait_link_active(struct controller *ctrl) ··· 288 412 } else 289 413 msleep(1000); 290 414 291 - retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 415 + retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 292 416 if (retval) { 293 417 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 294 418 return retval; 295 419 } 296 420 297 421 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 298 - if ((lnk_status & LNK_TRN) || !(lnk_status & NEG_LINK_WD)) { 422 + if ((lnk_status & PCI_EXP_LNKSTA_LT) || 423 + !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 299 424 ctrl_err(ctrl, "Link Training Error occurs \n"); 300 425 retval = -1; 301 426 return retval; ··· 312 435 u8 atten_led_state; 313 436 int retval = 0; 314 437 315 - retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 438 + retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 316 439 if (retval) { 317 440 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 318 441 return retval; 319 442 } 320 443 321 444 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", 322 - __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 445 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); 323 446 324 - atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; 447 + atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; 325 448 326 449 switch (atten_led_state) { 327 450 case 0: ··· 351 474 u8 pwr_state; 352 475 int retval = 0; 353 476 354 - retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 477 + retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 355 478 if (retval) { 356 479 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 357 480 return retval; 358 481 } 359 482 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", 360 - __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 483 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); 361 484 362 - pwr_state = (slot_ctrl & PWR_CTRL) >> 10; 485 + pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; 363 486 364 487 switch (pwr_state) { 365 488 case 0: ··· 380 503 { 381 504 struct controller *ctrl = slot->ctrl; 382 505 u16 slot_status; 383 - int retval = 0; 506 + int retval; 384 507 385 - retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 508 + retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 386 509 if (retval) { 387 510 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 388 511 __func__); 389 512 return retval; 390 513 } 391 - 392 - *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; 393 - 514 + *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 394 515 return 0; 395 516 } 396 517 ··· 396 521 { 397 522 struct controller *ctrl = slot->ctrl; 398 523 u16 slot_status; 399 - u8 card_state; 400 - int retval = 0; 524 + int retval; 401 525 402 - retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 526 + retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 403 527 if (retval) { 404 528 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 405 529 __func__); 406 530 return retval; 407 531 } 408 - card_state = (u8)((slot_status & PRSN_STATE) >> 6); 409 - *status = (card_state == 1) ? 1 : 0; 410 - 532 + *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 411 533 return 0; 412 534 } 413 535 ··· 412 540 { 413 541 struct controller *ctrl = slot->ctrl; 414 542 u16 slot_status; 415 - u8 pwr_fault; 416 - int retval = 0; 543 + int retval; 417 544 418 - retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 545 + retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 419 546 if (retval) { 420 547 ctrl_err(ctrl, "Cannot check for power fault\n"); 421 548 return retval; 422 549 } 423 - pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); 424 - 425 - return pwr_fault; 550 + return !!(slot_status & PCI_EXP_SLTSTA_PFD); 426 551 } 427 552 428 553 static int hpc_get_emi_status(struct slot *slot, u8 *status) 429 554 { 430 555 struct controller *ctrl = slot->ctrl; 431 556 u16 slot_status; 432 - int retval = 0; 557 + int retval; 433 558 434 - retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 559 + retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 435 560 if (retval) { 436 561 ctrl_err(ctrl, "Cannot check EMI status\n"); 437 562 return retval; 438 563 } 439 - *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; 440 - 564 + *status = !!(slot_status & PCI_EXP_SLTSTA_EIS); 441 565 return retval; 442 566 } 443 567 ··· 443 575 u16 cmd_mask; 444 576 int rc; 445 577 446 - slot_cmd = EMI_CTRL; 447 - cmd_mask = EMI_CTRL; 578 + slot_cmd = PCI_EXP_SLTCTL_EIC; 579 + cmd_mask = PCI_EXP_SLTCTL_EIC; 448 580 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); 449 581 slot->last_emi_toggle = get_seconds(); 450 582 ··· 458 590 u16 cmd_mask; 459 591 int rc; 460 592 461 - cmd_mask = ATTN_LED_CTRL; 593 + cmd_mask = PCI_EXP_SLTCTL_AIC; 462 594 switch (value) { 463 595 case 0 : /* turn off */ 464 596 slot_cmd = 0x00C0; ··· 474 606 } 475 607 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 476 608 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 477 - __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 609 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 478 610 479 611 return rc; 480 612 } ··· 486 618 u16 cmd_mask; 487 619 488 620 slot_cmd = 0x0100; 489 - cmd_mask = PWR_LED_CTRL; 621 + cmd_mask = PCI_EXP_SLTCTL_PIC; 490 622 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 491 623 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 492 - __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 624 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 493 625 } 494 626 495 627 static void hpc_set_green_led_off(struct slot *slot) ··· 499 631 u16 cmd_mask; 500 632 501 633 slot_cmd = 0x0300; 502 - cmd_mask = PWR_LED_CTRL; 634 + cmd_mask = PCI_EXP_SLTCTL_PIC; 503 635 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 504 636 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 505 - __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 637 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 506 638 } 507 639 508 640 static void hpc_set_green_led_blink(struct slot *slot) ··· 512 644 u16 cmd_mask; 513 645 514 646 slot_cmd = 0x0200; 515 - cmd_mask = PWR_LED_CTRL; 647 + cmd_mask = PCI_EXP_SLTCTL_PIC; 516 648 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 517 649 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 518 - __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 650 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 519 651 } 520 652 521 653 static int hpc_power_on_slot(struct slot * slot) ··· 529 661 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); 530 662 531 663 /* Clear sticky power-fault bit from previous power failures */ 532 - retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 664 + retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 533 665 if (retval) { 534 666 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 535 667 __func__); 536 668 return retval; 537 669 } 538 - slot_status &= PWR_FAULT_DETECTED; 670 + slot_status &= PCI_EXP_SLTSTA_PFD; 539 671 if (slot_status) { 540 - retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); 672 + retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); 541 673 if (retval) { 542 674 ctrl_err(ctrl, 543 675 "%s: Cannot write to SLOTSTATUS register\n", ··· 547 679 } 548 680 549 681 slot_cmd = POWER_ON; 550 - cmd_mask = PWR_CTRL; 682 + cmd_mask = PCI_EXP_SLTCTL_PCC; 551 683 /* Enable detection that we turned off at slot power-off time */ 552 684 if (!pciehp_poll_mode) { 553 - slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 554 - PRSN_DETECT_ENABLE); 555 - cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 556 - PRSN_DETECT_ENABLE); 685 + slot_cmd |= (PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE | 686 + PCI_EXP_SLTCTL_PDCE); 687 + cmd_mask |= (PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE | 688 + PCI_EXP_SLTCTL_PDCE); 557 689 } 558 690 559 691 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); ··· 563 695 return -1; 564 696 } 565 697 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 566 - __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 698 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 567 699 568 700 return retval; 569 701 } ··· 620 752 changed = pcie_mask_bad_dllp(ctrl); 621 753 622 754 slot_cmd = POWER_OFF; 623 - cmd_mask = PWR_CTRL; 755 + cmd_mask = PCI_EXP_SLTCTL_PCC; 624 756 /* 625 757 * If we get MRL or presence detect interrupts now, the isr 626 758 * will notice the sticky power-fault bit too and issue power ··· 629 761 * till the slot is powered on again. 630 762 */ 631 763 if (!pciehp_poll_mode) { 632 - slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 633 - PRSN_DETECT_ENABLE); 634 - cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 635 - PRSN_DETECT_ENABLE); 764 + slot_cmd &= ~(PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE | 765 + PCI_EXP_SLTCTL_PDCE); 766 + cmd_mask |= (PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE | 767 + PCI_EXP_SLTCTL_PDCE); 636 768 } 637 769 638 770 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); ··· 642 774 goto out; 643 775 } 644 776 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 645 - __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 777 + __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 646 778 out: 647 779 if (changed) 648 780 pcie_unmask_bad_dllp(ctrl); ··· 663 795 */ 664 796 intr_loc = 0; 665 797 do { 666 - if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { 798 + if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { 667 799 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", 668 800 __func__); 669 801 return IRQ_NONE; 670 802 } 671 803 672 - detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | 673 - MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | 674 - CMD_COMPLETED); 804 + detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 805 + PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 806 + PCI_EXP_SLTSTA_CC); 675 807 intr_loc |= detected; 676 808 if (!intr_loc) 677 809 return IRQ_NONE; 678 - if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { 810 + if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, detected)) { 679 811 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", 680 812 __func__); 681 813 return IRQ_NONE; ··· 685 817 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 686 818 687 819 /* Check Command Complete Interrupt Pending */ 688 - if (intr_loc & CMD_COMPLETED) { 820 + if (intr_loc & PCI_EXP_SLTSTA_CC) { 689 821 ctrl->cmd_busy = 0; 690 822 smp_mb(); 691 823 wake_up(&ctrl->queue); 692 824 } 693 825 694 - if (!(intr_loc & ~CMD_COMPLETED)) 826 + if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 695 827 return IRQ_HANDLED; 696 828 697 829 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); 698 830 699 831 /* Check MRL Sensor Changed */ 700 - if (intr_loc & MRL_SENS_CHANGED) 832 + if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 701 833 pciehp_handle_switch_change(p_slot); 702 834 703 835 /* Check Attention Button Pressed */ 704 - if (intr_loc & ATTN_BUTTN_PRESSED) 836 + if (intr_loc & PCI_EXP_SLTSTA_ABP) 705 837 pciehp_handle_attention_button(p_slot); 706 838 707 839 /* Check Presence Detect Changed */ 708 - if (intr_loc & PRSN_DETECT_CHANGED) 840 + if (intr_loc & PCI_EXP_SLTSTA_PDC) 709 841 pciehp_handle_presence_change(p_slot); 710 842 711 843 /* Check Power Fault Detected */ 712 - if (intr_loc & PWR_FAULT_DETECTED) 844 + if (intr_loc & PCI_EXP_SLTSTA_PFD) 713 845 pciehp_handle_power_fault(p_slot); 714 846 715 847 return IRQ_HANDLED; ··· 722 854 u32 lnk_cap; 723 855 int retval = 0; 724 856 725 - retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); 857 + retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 726 858 if (retval) { 727 859 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 728 860 return retval; ··· 751 883 u32 lnk_cap; 752 884 int retval = 0; 753 885 754 - retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); 886 + retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 755 887 if (retval) { 756 888 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 757 889 return retval; 758 890 } 759 891 760 - switch ((lnk_cap & 0x03F0) >> 4){ 892 + switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ 761 893 case 0: 762 894 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 763 895 break; ··· 800 932 int retval = 0; 801 933 u16 lnk_status; 802 934 803 - retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 935 + retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 804 936 if (retval) { 805 937 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 806 938 __func__); 807 939 return retval; 808 940 } 809 941 810 - switch (lnk_status & 0x0F) { 942 + switch (lnk_status & PCI_EXP_LNKSTA_CLS) { 811 943 case 1: 812 944 lnk_speed = PCIE_2PT5GB; 813 945 break; ··· 830 962 int retval = 0; 831 963 u16 lnk_status; 832 964 833 - retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 965 + retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 834 966 if (retval) { 835 967 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 836 968 __func__); 837 969 return retval; 838 970 } 839 971 840 - switch ((lnk_status & 0x03F0) >> 4){ 972 + switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ 841 973 case 0: 842 974 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 843 975 break; ··· 903 1035 { 904 1036 u16 cmd, mask; 905 1037 906 - cmd = PRSN_DETECT_ENABLE; 1038 + cmd = PCI_EXP_SLTCTL_PDCE; 907 1039 if (ATTN_BUTTN(ctrl)) 908 - cmd |= ATTN_BUTTN_ENABLE; 1040 + cmd |= PCI_EXP_SLTCTL_ABPE; 909 1041 if (POWER_CTRL(ctrl)) 910 - cmd |= PWR_FAULT_DETECT_ENABLE; 1042 + cmd |= PCI_EXP_SLTCTL_PFDE; 911 1043 if (MRL_SENS(ctrl)) 912 - cmd |= MRL_DETECT_ENABLE; 1044 + cmd |= PCI_EXP_SLTCTL_MRLSCE; 913 1045 if (!pciehp_poll_mode) 914 - cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; 1046 + cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 915 1047 916 - mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | 917 - PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; 1048 + mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 1049 + PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 1050 + PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 918 1051 919 1052 if (pcie_write_cmd(ctrl, cmd, mask)) { 920 1053 ctrl_err(ctrl, "Cannot enable software notification\n"); ··· 927 1058 static void pcie_disable_notification(struct controller *ctrl) 928 1059 { 929 1060 u16 mask; 930 - mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | 931 - PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; 1061 + mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 1062 + PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 1063 + PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 932 1064 if (pcie_write_cmd(ctrl, 0, mask)) 933 1065 ctrl_warn(ctrl, "Cannot disable software notification\n"); 934 1066 } ··· 1026 1156 EMI(ctrl) ? "yes" : "no"); 1027 1157 ctrl_info(ctrl, " Command Completed : %3s\n", 1028 1158 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 1029 - pciehp_readw(ctrl, SLOTSTATUS, &reg16); 1159 + pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16); 1030 1160 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 1031 - pciehp_readw(ctrl, SLOTCTRL, &reg16); 1161 + pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16); 1032 1162 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 1033 1163 } 1034 1164 ··· 1052 1182 ctrl_err(ctrl, "Cannot find PCI Express capability\n"); 1053 1183 goto abort_ctrl; 1054 1184 } 1055 - if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { 1185 + if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { 1056 1186 ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); 1057 1187 goto abort_ctrl; 1058 1188 } ··· 1077 1207 ctrl->no_cmd_complete = 1; 1078 1208 1079 1209 /* Check if Data Link Layer Link Active Reporting is implemented */ 1080 - if (pciehp_readl(ctrl, LNKCAP, &link_cap)) { 1210 + if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { 1081 1211 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 1082 1212 goto abort_ctrl; 1083 1213 } 1084 - if (link_cap & LINK_ACTIVE_REPORTING) { 1214 + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 1085 1215 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 1086 1216 ctrl->link_active_reporting = 1; 1087 1217 } 1088 1218 1089 1219 /* Clear all remaining event bits in Slot Status register */ 1090 - if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) 1220 + if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) 1091 1221 goto abort_ctrl; 1092 1222 1093 1223 /* Disable sotfware notification */

+57 -7

include/linux/pci_regs.h

··· 411 411 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 412 412 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 413 413 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 414 - #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ 415 - #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ 416 - #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ 417 - #define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ 414 + #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ 415 + #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 416 + #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 417 + #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ 418 + #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ 419 + #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ 420 + #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */ 421 + #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 422 + #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ 423 + #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 418 424 #define PCI_EXP_LNKCTL 16 /* Link Control */ 419 - #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ 420 - #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ 425 + #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ 426 + #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ 427 + #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ 428 + #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 429 + #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ 430 + #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ 421 431 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ 432 + #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ 433 + #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ 434 + #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ 422 435 #define PCI_EXP_LNKSTA 18 /* Link Status */ 423 - #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ 436 + #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 437 + #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ 438 + #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 424 439 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ 440 + #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 441 + #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 442 + #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 425 443 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 444 + #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ 445 + #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ 446 + #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ 447 + #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ 448 + #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ 449 + #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ 450 + #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ 451 + #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ 452 + #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ 453 + #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ 454 + #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ 455 + #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 426 456 #define PCI_EXP_SLTCTL 24 /* Slot Control */ 457 + #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ 458 + #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ 459 + #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ 460 + #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ 461 + #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ 462 + #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ 463 + #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ 464 + #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ 465 + #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ 466 + #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ 467 + #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ 427 468 #define PCI_EXP_SLTSTA 26 /* Slot Status */ 469 + #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ 470 + #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ 471 + #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ 472 + #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ 473 + #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ 474 + #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ 475 + #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ 476 + #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ 477 + #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ 428 478 #define PCI_EXP_RTCTL 28 /* Root Control */ 429 479 #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ 430 480 #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */