Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

arm64: Disable fine grained traps on boot

The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses
to small sets of registers and instructions from EL1 and EL0. Currently
Linux makes no use of this feature, ensure that it is not active at boot by
disabling the traps during EL2 setup.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210401180942.35815-3-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

authored by

Mark Brown and committed by
Catalin Marinas
31c00d2a 3e237387

+27
+21
arch/arm64/include/asm/el2_setup.h
··· 131 131 .Lskip_sve_\@: 132 132 .endm 133 133 134 + /* Disable any fine grained traps */ 135 + .macro __init_el2_fgt 136 + mrs x1, id_aa64mmfr0_el1 137 + ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4 138 + cbz x1, .Lskip_fgt_\@ 139 + 140 + msr_s SYS_HDFGRTR_EL2, xzr 141 + msr_s SYS_HDFGWTR_EL2, xzr 142 + msr_s SYS_HFGRTR_EL2, xzr 143 + msr_s SYS_HFGWTR_EL2, xzr 144 + msr_s SYS_HFGITR_EL2, xzr 145 + 146 + mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 147 + ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4 148 + cbz x1, .Lskip_fgt_\@ 149 + 150 + msr_s SYS_HAFGRTR_EL2, xzr 151 + .Lskip_fgt_\@: 152 + .endm 153 + 134 154 .macro __init_el2_nvhe_prepare_eret 135 155 mov x0, #INIT_PSTATE_EL1 136 156 msr spsr_el2, x0 ··· 175 155 __init_el2_nvhe_idregs 176 156 __init_el2_nvhe_cptr 177 157 __init_el2_nvhe_sve 158 + __init_el2_fgt 178 159 __init_el2_nvhe_prepare_eret 179 160 .endm 180 161
+6
arch/arm64/include/asm/sysreg.h
··· 475 475 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 476 476 477 477 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 478 + #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) 479 + #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) 480 + #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) 478 481 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 479 482 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 480 483 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 484 + #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) 485 + #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) 486 + #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 481 487 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 482 488 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 483 489 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)