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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
arm: dts: vexpress: Fix motherboard bus 'interrupt-map'
Commit 078fb7aa6a83 ("arm: dts: vexpress: Fix addressing issues with
'motherboard-bus' nodes") broke booting on a couple of 32-bit VExpress
boards. The problem is #address-cells size changed, but interrupt-map
was not updated. This results in the timer interrupt (and all the
other motherboard interrupts) not getting mapped.
As the 'interrupt-map' properties are all just duplicates across boards,
just move them into vexpress-v2m.dtsi and vexpress-v2m-rs1.dtsi.
Strictly speaking, 'interrupt-map' is dependent on the parent
interrupt controller, but it's not likely we'll ever have a different
parent than GICv2 on these old platforms. If there was one,
'interrupt-map' can still be overridden.
Link: https://lore.kernel.org/r/20210924214221.1877686-1-robh@kernel.org
Fixes: 078fb7aa6a83 ("arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodes")
Cc: Guillaume Tucker <guillaume.tucker@collabora.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Reported-by: Reported-by: "kernelci.org bot" <bot@kernelci.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
authored by
Rob Herring
and committed by
Sudeep Holla
319aeaf6
078fb7aa
+94
-231
+47
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+47
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
···
17
17
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18
18
* CHANGES TO vexpress-v2m.dtsi!
19
19
*/
20
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
20
21
21
22
/ {
22
23
v2m_fixed_3v3: fixed-regulator-0 {
···
105
104
compatible = "simple-bus";
106
105
#address-cells = <1>;
107
106
#size-cells = <1>;
107
+
108
+
#interrupt-cells = <1>;
109
+
interrupt-map-mask = <0 63>;
110
+
interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
111
+
<0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
112
+
<0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
113
+
<0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
114
+
<0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
115
+
<0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
116
+
<0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
117
+
<0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
118
+
<0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
119
+
<0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
120
+
<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
121
+
<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
122
+
<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
123
+
<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
124
+
<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
125
+
<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
126
+
<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
127
+
<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
128
+
<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
129
+
<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
130
+
<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
131
+
<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
132
+
<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
133
+
<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
134
+
<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
135
+
<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
136
+
<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
137
+
<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
138
+
<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
139
+
<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
140
+
<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
141
+
<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
142
+
<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
143
+
<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
144
+
<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
145
+
<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
146
+
<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
147
+
<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
148
+
<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
149
+
<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
150
+
<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
151
+
<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
152
+
<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
108
153
109
154
motherboard-bus@8000000 {
110
155
arm,hbi = <0x190>;
+47
arch/arm/boot/dts/vexpress-v2m.dtsi
+47
arch/arm/boot/dts/vexpress-v2m.dtsi
···
17
17
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18
18
* CHANGES TO vexpress-v2m-rs1.dtsi!
19
19
*/
20
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
20
21
21
22
/ {
22
23
bus@40000000 {
···
26
25
#size-cells = <1>;
27
26
ranges = <0x40000000 0x40000000 0x10000000>,
28
27
<0x10000000 0x10000000 0x00020000>;
28
+
29
+
#interrupt-cells = <1>;
30
+
interrupt-map-mask = <0 63>;
31
+
interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
32
+
<0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
33
+
<0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
34
+
<0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
35
+
<0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
36
+
<0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
37
+
<0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
38
+
<0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
39
+
<0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
40
+
<0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
41
+
<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
42
+
<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
43
+
<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
44
+
<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
45
+
<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
46
+
<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
47
+
<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
48
+
<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
49
+
<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
50
+
<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
51
+
<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
52
+
<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
53
+
<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
54
+
<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
55
+
<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
56
+
<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
57
+
<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
58
+
<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
59
+
<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
60
+
<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
61
+
<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
62
+
<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
63
+
<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
64
+
<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
65
+
<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
66
+
<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
67
+
<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
68
+
<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
69
+
<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
70
+
<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
71
+
<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
72
+
<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
73
+
<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
29
74
30
75
motherboard-bus@40000000 {
31
76
arm,hbi = <0x190>;
-46
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
-46
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
···
238
238
239
239
bus@8000000 {
240
240
ranges = <0x8000000 0 0x8000000 0x18000000>;
241
-
242
-
#interrupt-cells = <1>;
243
-
interrupt-map-mask = <0 0 63>;
244
-
interrupt-map = <0 0 0 &gic 0 0 4>,
245
-
<0 0 1 &gic 0 1 4>,
246
-
<0 0 2 &gic 0 2 4>,
247
-
<0 0 3 &gic 0 3 4>,
248
-
<0 0 4 &gic 0 4 4>,
249
-
<0 0 5 &gic 0 5 4>,
250
-
<0 0 6 &gic 0 6 4>,
251
-
<0 0 7 &gic 0 7 4>,
252
-
<0 0 8 &gic 0 8 4>,
253
-
<0 0 9 &gic 0 9 4>,
254
-
<0 0 10 &gic 0 10 4>,
255
-
<0 0 11 &gic 0 11 4>,
256
-
<0 0 12 &gic 0 12 4>,
257
-
<0 0 13 &gic 0 13 4>,
258
-
<0 0 14 &gic 0 14 4>,
259
-
<0 0 15 &gic 0 15 4>,
260
-
<0 0 16 &gic 0 16 4>,
261
-
<0 0 17 &gic 0 17 4>,
262
-
<0 0 18 &gic 0 18 4>,
263
-
<0 0 19 &gic 0 19 4>,
264
-
<0 0 20 &gic 0 20 4>,
265
-
<0 0 21 &gic 0 21 4>,
266
-
<0 0 22 &gic 0 22 4>,
267
-
<0 0 23 &gic 0 23 4>,
268
-
<0 0 24 &gic 0 24 4>,
269
-
<0 0 25 &gic 0 25 4>,
270
-
<0 0 26 &gic 0 26 4>,
271
-
<0 0 27 &gic 0 27 4>,
272
-
<0 0 28 &gic 0 28 4>,
273
-
<0 0 29 &gic 0 29 4>,
274
-
<0 0 30 &gic 0 30 4>,
275
-
<0 0 31 &gic 0 31 4>,
276
-
<0 0 32 &gic 0 32 4>,
277
-
<0 0 33 &gic 0 33 4>,
278
-
<0 0 34 &gic 0 34 4>,
279
-
<0 0 35 &gic 0 35 4>,
280
-
<0 0 36 &gic 0 36 4>,
281
-
<0 0 37 &gic 0 37 4>,
282
-
<0 0 38 &gic 0 38 4>,
283
-
<0 0 39 &gic 0 39 4>,
284
-
<0 0 40 &gic 0 40 4>,
285
-
<0 0 41 &gic 0 41 4>,
286
-
<0 0 42 &gic 0 42 4>;
287
241
};
288
242
289
243
site2: hsb@40000000 {
-46
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
-46
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
···
610
610
611
611
smb: bus@8000000 {
612
612
ranges = <0x8000000 0 0x8000000 0x18000000>;
613
-
614
-
#interrupt-cells = <1>;
615
-
interrupt-map-mask = <0 0 63>;
616
-
interrupt-map = <0 0 0 &gic 0 0 4>,
617
-
<0 0 1 &gic 0 1 4>,
618
-
<0 0 2 &gic 0 2 4>,
619
-
<0 0 3 &gic 0 3 4>,
620
-
<0 0 4 &gic 0 4 4>,
621
-
<0 0 5 &gic 0 5 4>,
622
-
<0 0 6 &gic 0 6 4>,
623
-
<0 0 7 &gic 0 7 4>,
624
-
<0 0 8 &gic 0 8 4>,
625
-
<0 0 9 &gic 0 9 4>,
626
-
<0 0 10 &gic 0 10 4>,
627
-
<0 0 11 &gic 0 11 4>,
628
-
<0 0 12 &gic 0 12 4>,
629
-
<0 0 13 &gic 0 13 4>,
630
-
<0 0 14 &gic 0 14 4>,
631
-
<0 0 15 &gic 0 15 4>,
632
-
<0 0 16 &gic 0 16 4>,
633
-
<0 0 17 &gic 0 17 4>,
634
-
<0 0 18 &gic 0 18 4>,
635
-
<0 0 19 &gic 0 19 4>,
636
-
<0 0 20 &gic 0 20 4>,
637
-
<0 0 21 &gic 0 21 4>,
638
-
<0 0 22 &gic 0 22 4>,
639
-
<0 0 23 &gic 0 23 4>,
640
-
<0 0 24 &gic 0 24 4>,
641
-
<0 0 25 &gic 0 25 4>,
642
-
<0 0 26 &gic 0 26 4>,
643
-
<0 0 27 &gic 0 27 4>,
644
-
<0 0 28 &gic 0 28 4>,
645
-
<0 0 29 &gic 0 29 4>,
646
-
<0 0 30 &gic 0 30 4>,
647
-
<0 0 31 &gic 0 31 4>,
648
-
<0 0 32 &gic 0 32 4>,
649
-
<0 0 33 &gic 0 33 4>,
650
-
<0 0 34 &gic 0 34 4>,
651
-
<0 0 35 &gic 0 35 4>,
652
-
<0 0 36 &gic 0 36 4>,
653
-
<0 0 37 &gic 0 37 4>,
654
-
<0 0 38 &gic 0 38 4>,
655
-
<0 0 39 &gic 0 39 4>,
656
-
<0 0 40 &gic 0 40 4>,
657
-
<0 0 41 &gic 0 41 4>,
658
-
<0 0 42 &gic 0 42 4>;
659
613
};
660
614
661
615
site2: hsb@40000000 {
-46
arch/arm/boot/dts/vexpress-v2p-ca5s.dts
-46
arch/arm/boot/dts/vexpress-v2p-ca5s.dts
···
208
208
209
209
smb: bus@8000000 {
210
210
ranges = <0 0x8000000 0x18000000>;
211
-
212
-
#interrupt-cells = <1>;
213
-
interrupt-map-mask = <0 0 63>;
214
-
interrupt-map = <0 0 0 &gic 0 0 4>,
215
-
<0 0 1 &gic 0 1 4>,
216
-
<0 0 2 &gic 0 2 4>,
217
-
<0 0 3 &gic 0 3 4>,
218
-
<0 0 4 &gic 0 4 4>,
219
-
<0 0 5 &gic 0 5 4>,
220
-
<0 0 6 &gic 0 6 4>,
221
-
<0 0 7 &gic 0 7 4>,
222
-
<0 0 8 &gic 0 8 4>,
223
-
<0 0 9 &gic 0 9 4>,
224
-
<0 0 10 &gic 0 10 4>,
225
-
<0 0 11 &gic 0 11 4>,
226
-
<0 0 12 &gic 0 12 4>,
227
-
<0 0 13 &gic 0 13 4>,
228
-
<0 0 14 &gic 0 14 4>,
229
-
<0 0 15 &gic 0 15 4>,
230
-
<0 0 16 &gic 0 16 4>,
231
-
<0 0 17 &gic 0 17 4>,
232
-
<0 0 18 &gic 0 18 4>,
233
-
<0 0 19 &gic 0 19 4>,
234
-
<0 0 20 &gic 0 20 4>,
235
-
<0 0 21 &gic 0 21 4>,
236
-
<0 0 22 &gic 0 22 4>,
237
-
<0 0 23 &gic 0 23 4>,
238
-
<0 0 24 &gic 0 24 4>,
239
-
<0 0 25 &gic 0 25 4>,
240
-
<0 0 26 &gic 0 26 4>,
241
-
<0 0 27 &gic 0 27 4>,
242
-
<0 0 28 &gic 0 28 4>,
243
-
<0 0 29 &gic 0 29 4>,
244
-
<0 0 30 &gic 0 30 4>,
245
-
<0 0 31 &gic 0 31 4>,
246
-
<0 0 32 &gic 0 32 4>,
247
-
<0 0 33 &gic 0 33 4>,
248
-
<0 0 34 &gic 0 34 4>,
249
-
<0 0 35 &gic 0 35 4>,
250
-
<0 0 36 &gic 0 36 4>,
251
-
<0 0 37 &gic 0 37 4>,
252
-
<0 0 38 &gic 0 38 4>,
253
-
<0 0 39 &gic 0 39 4>,
254
-
<0 0 40 &gic 0 40 4>,
255
-
<0 0 41 &gic 0 41 4>,
256
-
<0 0 42 &gic 0 42 4>;
257
211
};
258
212
259
213
site2: hsb@40000000 {
-48
arch/arm/boot/dts/vexpress-v2p-ca9.dts
-48
arch/arm/boot/dts/vexpress-v2p-ca9.dts
···
295
295
};
296
296
};
297
297
298
-
smb: bus@40000000 {
299
-
#interrupt-cells = <1>;
300
-
interrupt-map-mask = <0 0 63>;
301
-
interrupt-map = <0 0 0 &gic 0 0 4>,
302
-
<0 0 1 &gic 0 1 4>,
303
-
<0 0 2 &gic 0 2 4>,
304
-
<0 0 3 &gic 0 3 4>,
305
-
<0 0 4 &gic 0 4 4>,
306
-
<0 0 5 &gic 0 5 4>,
307
-
<0 0 6 &gic 0 6 4>,
308
-
<0 0 7 &gic 0 7 4>,
309
-
<0 0 8 &gic 0 8 4>,
310
-
<0 0 9 &gic 0 9 4>,
311
-
<0 0 10 &gic 0 10 4>,
312
-
<0 0 11 &gic 0 11 4>,
313
-
<0 0 12 &gic 0 12 4>,
314
-
<0 0 13 &gic 0 13 4>,
315
-
<0 0 14 &gic 0 14 4>,
316
-
<0 0 15 &gic 0 15 4>,
317
-
<0 0 16 &gic 0 16 4>,
318
-
<0 0 17 &gic 0 17 4>,
319
-
<0 0 18 &gic 0 18 4>,
320
-
<0 0 19 &gic 0 19 4>,
321
-
<0 0 20 &gic 0 20 4>,
322
-
<0 0 21 &gic 0 21 4>,
323
-
<0 0 22 &gic 0 22 4>,
324
-
<0 0 23 &gic 0 23 4>,
325
-
<0 0 24 &gic 0 24 4>,
326
-
<0 0 25 &gic 0 25 4>,
327
-
<0 0 26 &gic 0 26 4>,
328
-
<0 0 27 &gic 0 27 4>,
329
-
<0 0 28 &gic 0 28 4>,
330
-
<0 0 29 &gic 0 29 4>,
331
-
<0 0 30 &gic 0 30 4>,
332
-
<0 0 31 &gic 0 31 4>,
333
-
<0 0 32 &gic 0 32 4>,
334
-
<0 0 33 &gic 0 33 4>,
335
-
<0 0 34 &gic 0 34 4>,
336
-
<0 0 35 &gic 0 35 4>,
337
-
<0 0 36 &gic 0 36 4>,
338
-
<0 0 37 &gic 0 37 4>,
339
-
<0 0 38 &gic 0 38 4>,
340
-
<0 0 39 &gic 0 39 4>,
341
-
<0 0 40 &gic 0 40 4>,
342
-
<0 0 41 &gic 0 41 4>,
343
-
<0 0 42 &gic 0 42 4>;
344
-
};
345
-
346
298
site2: hsb@e0000000 {
347
299
compatible = "simple-bus";
348
300
#address-cells = <1>;
-45
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
-45
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
···
146
146
147
147
smb: bus@8000000 {
148
148
ranges = <0x8000000 0 0x8000000 0x18000000>;
149
-
#interrupt-cells = <1>;
150
-
interrupt-map-mask = <0 0 63>;
151
-
interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
152
-
<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
153
-
<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
154
-
<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
155
-
<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
156
-
<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
157
-
<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
158
-
<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
159
-
<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
160
-
<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
161
-
<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
162
-
<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
163
-
<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
164
-
<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
165
-
<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
166
-
<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
167
-
<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
168
-
<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
169
-
<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
170
-
<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
171
-
<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
172
-
<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
173
-
<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
174
-
<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
175
-
<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
176
-
<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
177
-
<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
178
-
<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
179
-
<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
180
-
<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
181
-
<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
182
-
<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
183
-
<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
184
-
<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
185
-
<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
186
-
<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
187
-
<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
188
-
<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
189
-
<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
190
-
<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
191
-
<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
192
-
<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
193
-
<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
194
149
};
195
150
};