Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

scsi: gdth: remove ISA and EISA support

The non-PCI code has bitrotted for quite a while and will just oops
on load because it passes a NULL pointer to the PCI DMA routines.

Lets kill it for good - if someone really wants to use one of these
cards I'll help mentoring them to write a proper driver glue.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

authored by

Christoph Hellwig and committed by
Martin K. Petersen
31481455 463563fa

+24 -717
+1 -1
drivers/scsi/Kconfig
··· 665 665 666 666 config SCSI_GDTH 667 667 tristate "Intel/ICP (former GDT SCSI Disk Array) RAID Controller support" 668 - depends on (ISA || EISA || PCI) && SCSI && ISA_DMA_API 668 + depends on PCI && SCSI 669 669 ---help--- 670 670 Formerly called GDT SCSI Disk Array Controller Support. 671 671
+23 -686
drivers/scsi/gdth.c
··· 1 1 /************************************************************************ 2 2 * Linux driver for * 3 - * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers * 3 + * ICP vortex GmbH: GDT PCI Disk Array Controllers * 4 4 * Intel Corporation: Storage RAID Controllers * 5 5 * * 6 6 * gdth.c * ··· 32 32 ************************************************************************/ 33 33 34 34 /* All GDT Disk Array Controllers are fully supported by this driver. 35 - * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the 35 + * This includes the PCI SCSI Disk Array Controllers and the 36 36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete 37 37 * list of all controller types. 38 - * 39 - * If you have one or more GDT3000/3020 EISA controllers with 40 - * controller BIOS disabled, you have to set the IRQ values with the 41 - * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are 42 - * the IRQ values for the EISA controllers. 43 38 * 44 39 * After the optional list of IRQ values, other possible 45 40 * command line options are: ··· 56 61 * access a shared resource from several nodes, 57 62 * appropriate controller firmware required 58 63 * shared_access:N enable driver reserve/release protocol 59 - * probe_eisa_isa:Y scan for EISA/ISA controllers 60 - * probe_eisa_isa:N do not scan for EISA/ISA controllers 61 64 * force_dma32:Y use only 32 bit DMA mode 62 65 * force_dma32:N use 64 bit DMA mode, if supported 63 66 * 64 67 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N, 65 68 * max_ids:127,rescan:N,hdr_channel:0, 66 - * shared_access:Y,probe_eisa_isa:N,force_dma32:N". 69 + * shared_access:Y,force_dma32:N". 67 70 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y". 68 71 * 69 72 * When loading the gdth driver as a module, the same options are available. ··· 72 79 * 73 80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0 74 81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0 75 - * probe_eisa_isa=0 force_dma32=0" 82 + * force_dma32=0" 76 83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1". 77 84 */ 78 85 ··· 279 286 280 287 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b)) 281 288 282 - #ifdef CONFIG_ISA 283 - static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */ 284 - #endif 285 - #if defined(CONFIG_EISA) || defined(CONFIG_ISA) 286 - static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */ 287 - #endif 288 289 static u8 gdth_polling; /* polling if TRUE */ 289 290 static int gdth_ctr_count = 0; /* controller count */ 290 291 static LIST_HEAD(gdth_instances); /* controller list */ ··· 312 325 }; 313 326 314 327 /* LILO and modprobe/insmod parameters */ 315 - /* IRQ list for GDT3000/3020 EISA controllers */ 316 - static int irq[MAXHA] __initdata = 317 - {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 318 - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}; 319 328 /* disable driver flag */ 320 329 static int disable __initdata = 0; 321 330 /* reserve flag */ ··· 331 348 static int rescan = 0; 332 349 /* shared access */ 333 350 static int shared_access = 1; 334 - /* enable support for EISA and ISA controllers */ 335 - static int probe_eisa_isa = 0; 336 351 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */ 337 352 static int force_dma32 = 0; 338 353 339 354 /* parameters for modprobe/insmod */ 340 - module_param_hw_array(irq, int, irq, NULL, 0); 341 355 module_param(disable, int, 0); 342 356 module_param(reserve_mode, int, 0); 343 357 module_param_array(reserve_list, int, NULL, 0); ··· 343 363 module_param(max_ids, int, 0); 344 364 module_param(rescan, int, 0); 345 365 module_param(shared_access, int, 0); 346 - module_param(probe_eisa_isa, int, 0); 347 366 module_param(force_dma32, int, 0); 348 367 MODULE_AUTHOR("Achim Leubner"); 349 368 MODULE_LICENSE("GPL"); ··· 494 515 } 495 516 } 496 517 497 - /* controller search and initialization functions */ 498 - #ifdef CONFIG_EISA 499 - static int __init gdth_search_eisa(u16 eisa_adr) 500 - { 501 - u32 id; 502 - 503 - TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr)); 504 - id = inl(eisa_adr+ID0REG); 505 - if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */ 506 - if ((inb(eisa_adr+EISAREG) & 8) == 0) 507 - return 0; /* not EISA configured */ 508 - return 1; 509 - } 510 - if (id == GDT3_ID) /* GDT3000 */ 511 - return 1; 512 - 513 - return 0; 514 - } 515 - #endif /* CONFIG_EISA */ 516 - 517 - #ifdef CONFIG_ISA 518 - static int __init gdth_search_isa(u32 bios_adr) 519 - { 520 - void __iomem *addr; 521 - u32 id; 522 - 523 - TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr)); 524 - if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) { 525 - id = readl(addr); 526 - iounmap(addr); 527 - if (id == GDT2_ID) /* GDT2000 */ 528 - return 1; 529 - } 530 - return 0; 531 - } 532 - #endif /* CONFIG_ISA */ 533 - 534 - #ifdef CONFIG_PCI 535 - 536 518 static bool gdth_search_vortex(u16 device) 537 519 { 538 520 if (device <= PCI_DEVICE_ID_VORTEX_GDT6555) ··· 596 656 597 657 return 0; 598 658 } 599 - #endif /* CONFIG_PCI */ 600 659 601 - #ifdef CONFIG_EISA 602 - static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha) 603 - { 604 - u32 retries,id; 605 - u8 prot_ver,eisacf,i,irq_found; 606 - 607 - TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr)); 608 - 609 - /* disable board interrupts, deinitialize services */ 610 - outb(0xff,eisa_adr+EDOORREG); 611 - outb(0x00,eisa_adr+EDENABREG); 612 - outb(0x00,eisa_adr+EINTENABREG); 613 - 614 - outb(0xff,eisa_adr+LDOORREG); 615 - retries = INIT_RETRIES; 616 - gdth_delay(20); 617 - while (inb(eisa_adr+EDOORREG) != 0xff) { 618 - if (--retries == 0) { 619 - printk("GDT-EISA: Initialization error (DEINIT failed)\n"); 620 - return 0; 621 - } 622 - gdth_delay(1); 623 - TRACE2(("wait for DEINIT: retries=%d\n",retries)); 624 - } 625 - prot_ver = inb(eisa_adr+MAILBOXREG); 626 - outb(0xff,eisa_adr+EDOORREG); 627 - if (prot_ver != PROTOCOL_VERSION) { 628 - printk("GDT-EISA: Illegal protocol version\n"); 629 - return 0; 630 - } 631 - ha->bmic = eisa_adr; 632 - ha->brd_phys = (u32)eisa_adr >> 12; 633 - 634 - outl(0,eisa_adr+MAILBOXREG); 635 - outl(0,eisa_adr+MAILBOXREG+4); 636 - outl(0,eisa_adr+MAILBOXREG+8); 637 - outl(0,eisa_adr+MAILBOXREG+12); 638 - 639 - /* detect IRQ */ 640 - if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) { 641 - ha->oem_id = OEM_ID_ICP; 642 - ha->type = GDT_EISA; 643 - ha->stype = id; 644 - outl(1,eisa_adr+MAILBOXREG+8); 645 - outb(0xfe,eisa_adr+LDOORREG); 646 - retries = INIT_RETRIES; 647 - gdth_delay(20); 648 - while (inb(eisa_adr+EDOORREG) != 0xfe) { 649 - if (--retries == 0) { 650 - printk("GDT-EISA: Initialization error (get IRQ failed)\n"); 651 - return 0; 652 - } 653 - gdth_delay(1); 654 - } 655 - ha->irq = inb(eisa_adr+MAILBOXREG); 656 - outb(0xff,eisa_adr+EDOORREG); 657 - TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq)); 658 - /* check the result */ 659 - if (ha->irq == 0) { 660 - TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n")); 661 - for (i = 0, irq_found = FALSE; 662 - i < MAXHA && irq[i] != 0xff; ++i) { 663 - if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) { 664 - irq_found = TRUE; 665 - break; 666 - } 667 - } 668 - if (irq_found) { 669 - ha->irq = irq[i]; 670 - irq[i] = 0; 671 - printk("GDT-EISA: Can not detect controller IRQ,\n"); 672 - printk("Use IRQ setting from command line (IRQ = %d)\n", 673 - ha->irq); 674 - } else { 675 - printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n"); 676 - printk("the controller BIOS or use command line parameters\n"); 677 - return 0; 678 - } 679 - } 680 - } else { 681 - eisacf = inb(eisa_adr+EISAREG) & 7; 682 - if (eisacf > 4) /* level triggered */ 683 - eisacf -= 4; 684 - ha->irq = gdth_irq_tab[eisacf]; 685 - ha->oem_id = OEM_ID_ICP; 686 - ha->type = GDT_EISA; 687 - ha->stype = id; 688 - } 689 - 690 - ha->dma64_support = 0; 691 - return 1; 692 - } 693 - #endif /* CONFIG_EISA */ 694 - 695 - #ifdef CONFIG_ISA 696 - static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha) 697 - { 698 - register gdt2_dpram_str __iomem *dp2_ptr; 699 - int i; 700 - u8 irq_drq,prot_ver; 701 - u32 retries; 702 - 703 - TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr)); 704 - 705 - ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str)); 706 - if (ha->brd == NULL) { 707 - printk("GDT-ISA: Initialization error (DPMEM remap error)\n"); 708 - return 0; 709 - } 710 - dp2_ptr = ha->brd; 711 - writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */ 712 - /* reset interface area */ 713 - memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u)); 714 - if (readl(&dp2_ptr->u) != 0) { 715 - printk("GDT-ISA: Initialization error (DPMEM write error)\n"); 716 - iounmap(ha->brd); 717 - return 0; 718 - } 719 - 720 - /* disable board interrupts, read DRQ and IRQ */ 721 - writeb(0xff, &dp2_ptr->io.irqdel); 722 - writeb(0x00, &dp2_ptr->io.irqen); 723 - writeb(0x00, &dp2_ptr->u.ic.S_Status); 724 - writeb(0x00, &dp2_ptr->u.ic.Cmd_Index); 725 - 726 - irq_drq = readb(&dp2_ptr->io.rq); 727 - for (i=0; i<3; ++i) { 728 - if ((irq_drq & 1)==0) 729 - break; 730 - irq_drq >>= 1; 731 - } 732 - ha->drq = gdth_drq_tab[i]; 733 - 734 - irq_drq = readb(&dp2_ptr->io.rq) >> 3; 735 - for (i=1; i<5; ++i) { 736 - if ((irq_drq & 1)==0) 737 - break; 738 - irq_drq >>= 1; 739 - } 740 - ha->irq = gdth_irq_tab[i]; 741 - 742 - /* deinitialize services */ 743 - writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]); 744 - writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx); 745 - writeb(0, &dp2_ptr->io.event); 746 - retries = INIT_RETRIES; 747 - gdth_delay(20); 748 - while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) { 749 - if (--retries == 0) { 750 - printk("GDT-ISA: Initialization error (DEINIT failed)\n"); 751 - iounmap(ha->brd); 752 - return 0; 753 - } 754 - gdth_delay(1); 755 - } 756 - prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]); 757 - writeb(0, &dp2_ptr->u.ic.Status); 758 - writeb(0xff, &dp2_ptr->io.irqdel); 759 - if (prot_ver != PROTOCOL_VERSION) { 760 - printk("GDT-ISA: Illegal protocol version\n"); 761 - iounmap(ha->brd); 762 - return 0; 763 - } 764 - 765 - ha->oem_id = OEM_ID_ICP; 766 - ha->type = GDT_ISA; 767 - ha->ic_all_size = sizeof(dp2_ptr->u); 768 - ha->stype= GDT2_ID; 769 - ha->brd_phys = bios_adr >> 4; 770 - 771 - /* special request to controller BIOS */ 772 - writel(0x00, &dp2_ptr->u.ic.S_Info[0]); 773 - writel(0x00, &dp2_ptr->u.ic.S_Info[1]); 774 - writel(0x01, &dp2_ptr->u.ic.S_Info[2]); 775 - writel(0x00, &dp2_ptr->u.ic.S_Info[3]); 776 - writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx); 777 - writeb(0, &dp2_ptr->io.event); 778 - retries = INIT_RETRIES; 779 - gdth_delay(20); 780 - while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) { 781 - if (--retries == 0) { 782 - printk("GDT-ISA: Initialization error\n"); 783 - iounmap(ha->brd); 784 - return 0; 785 - } 786 - gdth_delay(1); 787 - } 788 - writeb(0, &dp2_ptr->u.ic.Status); 789 - writeb(0xff, &dp2_ptr->io.irqdel); 790 - 791 - ha->dma64_support = 0; 792 - return 1; 793 - } 794 - #endif /* CONFIG_ISA */ 795 - 796 - #ifdef CONFIG_PCI 797 660 static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr, 798 661 gdth_ha_str *ha) 799 662 { ··· 971 1228 972 1229 return 1; 973 1230 } 974 - #endif /* CONFIG_PCI */ 975 1231 976 1232 /* controller protocol functions */ 977 1233 978 1234 static void gdth_enable_int(gdth_ha_str *ha) 979 1235 { 980 1236 unsigned long flags; 981 - gdt2_dpram_str __iomem *dp2_ptr; 982 1237 gdt6_dpram_str __iomem *dp6_ptr; 983 1238 gdt6m_dpram_str __iomem *dp6m_ptr; 984 1239 985 1240 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum)); 986 1241 spin_lock_irqsave(&ha->smp_lock, flags); 987 1242 988 - if (ha->type == GDT_EISA) { 989 - outb(0xff, ha->bmic + EDOORREG); 990 - outb(0xff, ha->bmic + EDENABREG); 991 - outb(0x01, ha->bmic + EINTENABREG); 992 - } else if (ha->type == GDT_ISA) { 993 - dp2_ptr = ha->brd; 994 - writeb(1, &dp2_ptr->io.irqdel); 995 - writeb(0, &dp2_ptr->u.ic.Cmd_Index); 996 - writeb(1, &dp2_ptr->io.irqen); 997 - } else if (ha->type == GDT_PCI) { 1243 + if (ha->type == GDT_PCI) { 998 1244 dp6_ptr = ha->brd; 999 1245 writeb(1, &dp6_ptr->io.irqdel); 1000 1246 writeb(0, &dp6_ptr->u.ic.Cmd_Index); ··· 1007 1275 1008 1276 TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count)); 1009 1277 1010 - if (ha->type == GDT_EISA) 1011 - IStatus = inb((u16)ha->bmic + EDOORREG); 1012 - else if (ha->type == GDT_ISA) 1013 - IStatus = 1014 - readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); 1015 - else if (ha->type == GDT_PCI) 1278 + if (ha->type == GDT_PCI) 1016 1279 IStatus = 1017 1280 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); 1018 1281 else if (ha->type == GDT_PCINEW) ··· 1025 1298 1026 1299 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum)); 1027 1300 1028 - if (ha->type == GDT_EISA) 1029 - gdtsema0 = (int)inb(ha->bmic + SEMA0REG); 1030 - else if (ha->type == GDT_ISA) 1031 - gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0); 1032 - else if (ha->type == GDT_PCI) 1301 + if (ha->type == GDT_PCI) 1033 1302 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); 1034 1303 else if (ha->type == GDT_PCINEW) 1035 1304 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg)); ··· 1059 1336 { 1060 1337 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum)); 1061 1338 1062 - if (ha->type == GDT_EISA) { 1063 - outb(1, ha->bmic + SEMA0REG); 1064 - } else if (ha->type == GDT_ISA) { 1065 - writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0); 1066 - } else if (ha->type == GDT_PCI) { 1339 + if (ha->type == GDT_PCI) { 1067 1340 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); 1068 1341 } else if (ha->type == GDT_PCINEW) { 1069 1342 outb(1, PTR2USHORT(&ha->plx->sema0_reg)); ··· 1075 1356 register gdt6m_dpram_str __iomem *dp6m_ptr; 1076 1357 register gdt6c_dpram_str __iomem *dp6c_ptr; 1077 1358 gdt6_dpram_str __iomem *dp6_ptr; 1078 - gdt2_dpram_str __iomem *dp2_ptr; 1079 1359 u16 cp_count,dp_offset,cmd_no; 1080 1360 1081 1361 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum)); ··· 1085 1367 cmd_ptr = ha->pccb; 1086 1368 1087 1369 ++ha->cmd_cnt; 1088 - if (ha->type == GDT_EISA) 1089 - return; /* no DPMEM, no copy */ 1090 1370 1091 1371 /* set cpcount dword aligned */ 1092 1372 if (cp_count & 3) ··· 1093 1377 ha->cmd_offs_dpmem += cp_count; 1094 1378 1095 1379 /* set offset and service, copy command to DPMEM */ 1096 - if (ha->type == GDT_ISA) { 1097 - dp2_ptr = ha->brd; 1098 - writew(dp_offset + DPMEM_COMMAND_OFFSET, 1099 - &dp2_ptr->u.ic.comm_queue[cmd_no].offset); 1100 - writew((u16)cmd_ptr->Service, 1101 - &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id); 1102 - memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); 1103 - } else if (ha->type == GDT_PCI) { 1380 + if (ha->type == GDT_PCI) { 1104 1381 dp6_ptr = ha->brd; 1105 1382 writew(dp_offset + DPMEM_COMMAND_OFFSET, 1106 1383 &dp6_ptr->u.ic.comm_queue[cmd_no].offset); ··· 1139 1430 if (ha->pccb->OpCode == GDT_INIT) 1140 1431 ha->pccb->Service |= 0x80; 1141 1432 1142 - if (ha->type == GDT_EISA) { 1143 - if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */ 1144 - outl(ha->ccb_phys, ha->bmic + MAILBOXREG); 1145 - outb(ha->pccb->Service, ha->bmic + LDOORREG); 1146 - } else if (ha->type == GDT_ISA) { 1147 - writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event); 1148 - } else if (ha->type == GDT_PCI) { 1433 + if (ha->type == GDT_PCI) { 1149 1434 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event); 1150 1435 } else if (ha->type == GDT_PCINEW) { 1151 1436 outb(1, PTR2USHORT(&ha->plx->ldoor_reg)); ··· 2136 2433 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n", 2137 2434 scp->cmnd[0],scp->cmd_len,hdrive)); 2138 2435 2139 - if (ha->type==GDT_EISA && ha->cmd_cnt>0) 2140 - return 0; 2141 - 2142 2436 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE; 2143 2437 /* test for READ_16, WRITE_16 if !mode64 ? --- 2144 2438 not required, should not occur due to error return on ··· 2313 2613 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n", 2314 2614 scp->cmnd[0],b,t,l)); 2315 2615 2316 - if (ha->type==GDT_EISA && ha->cmd_cnt>0) 2317 - return 0; 2318 - 2319 2616 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE; 2320 2617 2321 2618 cmdp->Service = SCSIRAWSERVICE; ··· 2474 2777 2475 2778 cmdp= ha->pccb; 2476 2779 TRACE2(("gdth_special_cmd(): ")); 2477 - 2478 - if (ha->type==GDT_EISA && ha->cmd_cnt>0) 2479 - return 0; 2480 2780 2481 2781 *cmdp = *cmndinfo->internal_cmd_str; 2482 2782 cmdp->RequestBuffer = scp; ··· 2653 2959 { 2654 2960 gdt6m_dpram_str __iomem *dp6m_ptr = NULL; 2655 2961 gdt6_dpram_str __iomem *dp6_ptr; 2656 - gdt2_dpram_str __iomem *dp2_ptr; 2657 2962 struct scsi_cmnd *scp; 2658 2963 int rval, i; 2659 2964 u8 IStatus; ··· 2708 3015 } 2709 3016 #endif 2710 3017 2711 - if (ha->type == GDT_EISA) { 2712 - if (IStatus & 0x80) { /* error flag */ 2713 - IStatus &= ~0x80; 2714 - ha->status = inw(ha->bmic + MAILBOXREG+8); 2715 - TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); 2716 - } else /* no error */ 2717 - ha->status = S_OK; 2718 - ha->info = inl(ha->bmic + MAILBOXREG+12); 2719 - ha->service = inw(ha->bmic + MAILBOXREG+10); 2720 - ha->info2 = inl(ha->bmic + MAILBOXREG+4); 2721 - 2722 - outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */ 2723 - outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */ 2724 - } else if (ha->type == GDT_ISA) { 2725 - dp2_ptr = ha->brd; 2726 - if (IStatus & 0x80) { /* error flag */ 2727 - IStatus &= ~0x80; 2728 - ha->status = readw(&dp2_ptr->u.ic.Status); 2729 - TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status)); 2730 - } else /* no error */ 2731 - ha->status = S_OK; 2732 - ha->info = readl(&dp2_ptr->u.ic.Info[0]); 2733 - ha->service = readw(&dp2_ptr->u.ic.Service); 2734 - ha->info2 = readl(&dp2_ptr->u.ic.Info[1]); 2735 - 2736 - writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */ 2737 - writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */ 2738 - writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */ 2739 - } else if (ha->type == GDT_PCI) { 3018 + if (ha->type == GDT_PCI) { 2740 3019 dp6_ptr = ha->brd; 2741 3020 if (IStatus & 0x80) { /* error flag */ 2742 3021 IStatus &= ~0x80; ··· 3275 3610 + sizeof(u64); 3276 3611 ha->cmd_cnt = 0; 3277 3612 gdth_copy_command(ha); 3278 - if (ha->type == GDT_EISA) 3279 - printk("[EISA slot %d] ",(u16)ha->brd_phys); 3280 - else if (ha->type == GDT_ISA) 3281 - printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys); 3282 - else 3283 - printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8), 3613 + printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8), 3284 3614 (u16)((ha->brd_phys>>3)&0x1f)); 3285 3615 gdth_release_event(ha); 3286 3616 } ··· 3416 3756 3417 3757 static void __init internal_setup(char *str,int *ints) 3418 3758 { 3419 - int i, argc; 3759 + int i; 3420 3760 char *cur_str, *argv; 3421 3761 3422 3762 TRACE2(("internal_setup() str %s ints[0] %d\n", 3423 3763 str ? str:"NULL", ints ? ints[0]:0)); 3424 - 3425 - /* read irq[] from ints[] */ 3426 - if (ints) { 3427 - argc = ints[0]; 3428 - if (argc > 0) { 3429 - if (argc > MAXHA) 3430 - argc = MAXHA; 3431 - for (i = 0; i < argc; ++i) 3432 - irq[i] = ints[i+1]; 3433 - } 3434 - } 3435 3764 3436 3765 /* analyse string */ 3437 3766 argv = str; ··· 3448 3799 rescan = val; 3449 3800 else if (!strncmp(argv, "shared_access:", 14)) 3450 3801 shared_access = val; 3451 - else if (!strncmp(argv, "probe_eisa_isa:", 15)) 3452 - probe_eisa_isa = val; 3453 3802 else if (!strncmp(argv, "reserve_list:", 13)) { 3454 3803 reserve_list[0] = val; 3455 3804 for (i = 1; i < MAX_RES_ARGS; i++) { ··· 3494 3847 { 3495 3848 TRACE2(("gdth_ctr_name()\n")); 3496 3849 3497 - if (ha->type == GDT_EISA) { 3498 - switch (ha->stype) { 3499 - case GDT3_ID: 3500 - return("GDT3000/3020"); 3501 - case GDT3A_ID: 3502 - return("GDT3000A/3020A/3050A"); 3503 - case GDT3B_ID: 3504 - return("GDT3000B/3010A"); 3505 - } 3506 - } else if (ha->type == GDT_ISA) { 3507 - return("GDT2000/2020"); 3508 - } else if (ha->type == GDT_PCI) { 3850 + if (ha->type == GDT_PCI) { 3509 3851 switch (ha->pdev->device) { 3510 3852 case PCI_DEVICE_ID_VORTEX_GDT60x0: 3511 3853 return("GDT6000/6020/6050"); ··· 4164 4528 (NULL == (ha = gdth_find_ha(ctrt.ionode)))) 4165 4529 return -EFAULT; 4166 4530 4167 - if (ha->type == GDT_ISA || ha->type == GDT_EISA) { 4168 - ctrt.type = (u8)((ha->stype>>20) - 0x10); 4531 + if (ha->type != GDT_PCIMPR) { 4532 + ctrt.type = (u8)((ha->stype<<4) + 6); 4169 4533 } else { 4170 - if (ha->type != GDT_PCIMPR) { 4171 - ctrt.type = (u8)((ha->stype<<4) + 6); 4172 - } else { 4173 - ctrt.type = 4174 - (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe); 4175 - if (ha->stype >= 0x300) 4176 - ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device; 4177 - else 4178 - ctrt.ext_type = 0x6000 | ha->stype; 4179 - } 4180 - ctrt.device_id = ha->pdev->device; 4181 - ctrt.sub_device_id = ha->pdev->subsystem_device; 4534 + ctrt.type = (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe); 4535 + if (ha->stype >= 0x300) 4536 + ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device; 4537 + else 4538 + ctrt.ext_type = 0x6000 | ha->stype; 4182 4539 } 4540 + ctrt.device_id = ha->pdev->device; 4541 + ctrt.sub_device_id = ha->pdev->subsystem_device; 4183 4542 ctrt.info = ha->brd_phys; 4184 4543 ctrt.oem_id = ha->oem_id; 4185 4544 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype))) ··· 4328 4697 .no_write_same = 1, 4329 4698 }; 4330 4699 4331 - #ifdef CONFIG_ISA 4332 - static int __init gdth_isa_probe_one(u32 isa_bios) 4333 - { 4334 - struct Scsi_Host *shp; 4335 - gdth_ha_str *ha; 4336 - dma_addr_t scratch_dma_handle = 0; 4337 - int error, i; 4338 - 4339 - if (!gdth_search_isa(isa_bios)) 4340 - return -ENXIO; 4341 - 4342 - shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str)); 4343 - if (!shp) 4344 - return -ENOMEM; 4345 - ha = shost_priv(shp); 4346 - 4347 - error = -ENODEV; 4348 - if (!gdth_init_isa(isa_bios,ha)) 4349 - goto out_host_put; 4350 - 4351 - /* controller found and initialized */ 4352 - printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n", 4353 - isa_bios, ha->irq, ha->drq); 4354 - 4355 - error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha); 4356 - if (error) { 4357 - printk("GDT-ISA: Unable to allocate IRQ\n"); 4358 - goto out_host_put; 4359 - } 4360 - 4361 - error = request_dma(ha->drq, "gdth"); 4362 - if (error) { 4363 - printk("GDT-ISA: Unable to allocate DMA channel\n"); 4364 - goto out_free_irq; 4365 - } 4366 - 4367 - set_dma_mode(ha->drq,DMA_MODE_CASCADE); 4368 - enable_dma(ha->drq); 4369 - shp->unchecked_isa_dma = 1; 4370 - shp->irq = ha->irq; 4371 - shp->dma_channel = ha->drq; 4372 - 4373 - ha->hanum = gdth_ctr_count++; 4374 - ha->shost = shp; 4375 - 4376 - ha->pccb = &ha->cmdext; 4377 - ha->ccb_phys = 0L; 4378 - ha->pdev = NULL; 4379 - 4380 - error = -ENOMEM; 4381 - 4382 - ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH, 4383 - &scratch_dma_handle); 4384 - if (!ha->pscratch) 4385 - goto out_dec_counters; 4386 - ha->scratch_phys = scratch_dma_handle; 4387 - 4388 - ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str), 4389 - &scratch_dma_handle); 4390 - if (!ha->pmsg) 4391 - goto out_free_pscratch; 4392 - ha->msg_phys = scratch_dma_handle; 4393 - 4394 - #ifdef INT_COAL 4395 - ha->coal_stat = pci_alloc_consistent(ha->pdev, 4396 - sizeof(gdth_coal_status) * MAXOFFSETS, 4397 - &scratch_dma_handle); 4398 - if (!ha->coal_stat) 4399 - goto out_free_pmsg; 4400 - ha->coal_stat_phys = scratch_dma_handle; 4401 - #endif 4402 - 4403 - ha->scratch_busy = FALSE; 4404 - ha->req_first = NULL; 4405 - ha->tid_cnt = MAX_HDRIVES; 4406 - if (max_ids > 0 && max_ids < ha->tid_cnt) 4407 - ha->tid_cnt = max_ids; 4408 - for (i = 0; i < GDTH_MAXCMDS; ++i) 4409 - ha->cmd_tab[i].cmnd = UNUSED_CMND; 4410 - ha->scan_mode = rescan ? 0x10 : 0; 4411 - 4412 - error = -ENODEV; 4413 - if (!gdth_search_drives(ha)) { 4414 - printk("GDT-ISA: Error during device scan\n"); 4415 - goto out_free_coal_stat; 4416 - } 4417 - 4418 - if (hdr_channel < 0 || hdr_channel > ha->bus_cnt) 4419 - hdr_channel = ha->bus_cnt; 4420 - ha->virt_bus = hdr_channel; 4421 - 4422 - if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) 4423 - shp->max_cmd_len = 16; 4424 - 4425 - shp->max_id = ha->tid_cnt; 4426 - shp->max_lun = MAXLUN; 4427 - shp->max_channel = ha->bus_cnt; 4428 - 4429 - spin_lock_init(&ha->smp_lock); 4430 - gdth_enable_int(ha); 4431 - 4432 - error = scsi_add_host(shp, NULL); 4433 - if (error) 4434 - goto out_free_coal_stat; 4435 - list_add_tail(&ha->list, &gdth_instances); 4436 - gdth_timer_init(); 4437 - 4438 - scsi_scan_host(shp); 4439 - 4440 - return 0; 4441 - 4442 - out_free_coal_stat: 4443 - #ifdef INT_COAL 4444 - pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS, 4445 - ha->coal_stat, ha->coal_stat_phys); 4446 - out_free_pmsg: 4447 - #endif 4448 - pci_free_consistent(ha->pdev, sizeof(gdth_msg_str), 4449 - ha->pmsg, ha->msg_phys); 4450 - out_free_pscratch: 4451 - pci_free_consistent(ha->pdev, GDTH_SCRATCH, 4452 - ha->pscratch, ha->scratch_phys); 4453 - out_dec_counters: 4454 - gdth_ctr_count--; 4455 - out_free_irq: 4456 - free_irq(ha->irq, ha); 4457 - out_host_put: 4458 - scsi_host_put(shp); 4459 - return error; 4460 - } 4461 - #endif /* CONFIG_ISA */ 4462 - 4463 - #ifdef CONFIG_EISA 4464 - static int __init gdth_eisa_probe_one(u16 eisa_slot) 4465 - { 4466 - struct Scsi_Host *shp; 4467 - gdth_ha_str *ha; 4468 - dma_addr_t scratch_dma_handle = 0; 4469 - int error, i; 4470 - 4471 - if (!gdth_search_eisa(eisa_slot)) 4472 - return -ENXIO; 4473 - 4474 - shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str)); 4475 - if (!shp) 4476 - return -ENOMEM; 4477 - ha = shost_priv(shp); 4478 - 4479 - error = -ENODEV; 4480 - if (!gdth_init_eisa(eisa_slot,ha)) 4481 - goto out_host_put; 4482 - 4483 - /* controller found and initialized */ 4484 - printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n", 4485 - eisa_slot >> 12, ha->irq); 4486 - 4487 - error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha); 4488 - if (error) { 4489 - printk("GDT-EISA: Unable to allocate IRQ\n"); 4490 - goto out_host_put; 4491 - } 4492 - 4493 - shp->unchecked_isa_dma = 0; 4494 - shp->irq = ha->irq; 4495 - shp->dma_channel = 0xff; 4496 - 4497 - ha->hanum = gdth_ctr_count++; 4498 - ha->shost = shp; 4499 - 4500 - TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum)); 4501 - 4502 - ha->pccb = &ha->cmdext; 4503 - ha->ccb_phys = 0L; 4504 - 4505 - error = -ENOMEM; 4506 - 4507 - ha->pdev = NULL; 4508 - ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH, 4509 - &scratch_dma_handle); 4510 - if (!ha->pscratch) 4511 - goto out_free_irq; 4512 - ha->scratch_phys = scratch_dma_handle; 4513 - 4514 - ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str), 4515 - &scratch_dma_handle); 4516 - if (!ha->pmsg) 4517 - goto out_free_pscratch; 4518 - ha->msg_phys = scratch_dma_handle; 4519 - 4520 - #ifdef INT_COAL 4521 - ha->coal_stat = pci_alloc_consistent(ha->pdev, 4522 - sizeof(gdth_coal_status) * MAXOFFSETS, 4523 - &scratch_dma_handle); 4524 - if (!ha->coal_stat) 4525 - goto out_free_pmsg; 4526 - ha->coal_stat_phys = scratch_dma_handle; 4527 - #endif 4528 - 4529 - ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb, 4530 - sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL); 4531 - if (!ha->ccb_phys) 4532 - goto out_free_coal_stat; 4533 - 4534 - ha->scratch_busy = FALSE; 4535 - ha->req_first = NULL; 4536 - ha->tid_cnt = MAX_HDRIVES; 4537 - if (max_ids > 0 && max_ids < ha->tid_cnt) 4538 - ha->tid_cnt = max_ids; 4539 - for (i = 0; i < GDTH_MAXCMDS; ++i) 4540 - ha->cmd_tab[i].cmnd = UNUSED_CMND; 4541 - ha->scan_mode = rescan ? 0x10 : 0; 4542 - 4543 - if (!gdth_search_drives(ha)) { 4544 - printk("GDT-EISA: Error during device scan\n"); 4545 - error = -ENODEV; 4546 - goto out_free_ccb_phys; 4547 - } 4548 - 4549 - if (hdr_channel < 0 || hdr_channel > ha->bus_cnt) 4550 - hdr_channel = ha->bus_cnt; 4551 - ha->virt_bus = hdr_channel; 4552 - 4553 - if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) 4554 - shp->max_cmd_len = 16; 4555 - 4556 - shp->max_id = ha->tid_cnt; 4557 - shp->max_lun = MAXLUN; 4558 - shp->max_channel = ha->bus_cnt; 4559 - 4560 - spin_lock_init(&ha->smp_lock); 4561 - gdth_enable_int(ha); 4562 - 4563 - error = scsi_add_host(shp, NULL); 4564 - if (error) 4565 - goto out_free_ccb_phys; 4566 - list_add_tail(&ha->list, &gdth_instances); 4567 - gdth_timer_init(); 4568 - 4569 - scsi_scan_host(shp); 4570 - 4571 - return 0; 4572 - 4573 - out_free_ccb_phys: 4574 - pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str), 4575 - PCI_DMA_BIDIRECTIONAL); 4576 - out_free_coal_stat: 4577 - #ifdef INT_COAL 4578 - pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS, 4579 - ha->coal_stat, ha->coal_stat_phys); 4580 - out_free_pmsg: 4581 - #endif 4582 - pci_free_consistent(ha->pdev, sizeof(gdth_msg_str), 4583 - ha->pmsg, ha->msg_phys); 4584 - out_free_pscratch: 4585 - pci_free_consistent(ha->pdev, GDTH_SCRATCH, 4586 - ha->pscratch, ha->scratch_phys); 4587 - out_free_irq: 4588 - free_irq(ha->irq, ha); 4589 - gdth_ctr_count--; 4590 - out_host_put: 4591 - scsi_host_put(shp); 4592 - return error; 4593 - } 4594 - #endif /* CONFIG_EISA */ 4595 - 4596 - #ifdef CONFIG_PCI 4597 4700 static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out) 4598 4701 { 4599 4702 struct Scsi_Host *shp; ··· 4470 5105 scsi_host_put(shp); 4471 5106 return error; 4472 5107 } 4473 - #endif /* CONFIG_PCI */ 4474 5108 4475 5109 static void gdth_remove_one(gdth_ha_str *ha) 4476 5110 { ··· 4489 5125 if (shp->irq) 4490 5126 free_irq(shp->irq,ha); 4491 5127 4492 - #ifdef CONFIG_ISA 4493 - if (shp->dma_channel != 0xff) 4494 - free_dma(shp->dma_channel); 4495 - #endif 4496 5128 #ifdef INT_COAL 4497 5129 if (ha->coal_stat) 4498 5130 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * ··· 4541 5181 gdth_clear_events(); 4542 5182 timer_setup(&gdth_timer, gdth_timeout, 0); 4543 5183 4544 - /* As default we do not probe for EISA or ISA controllers */ 4545 - if (probe_eisa_isa) { 4546 - /* scanning for controllers, at first: ISA controller */ 4547 - #ifdef CONFIG_ISA 4548 - u32 isa_bios; 4549 - for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL; 4550 - isa_bios += 0x8000UL) 4551 - gdth_isa_probe_one(isa_bios); 4552 - #endif 4553 - #ifdef CONFIG_EISA 4554 - { 4555 - u16 eisa_slot; 4556 - for (eisa_slot = 0x1000; eisa_slot <= 0x8000; 4557 - eisa_slot += 0x1000) 4558 - gdth_eisa_probe_one(eisa_slot); 4559 - } 4560 - #endif 4561 - } 4562 - 4563 - #ifdef CONFIG_PCI 4564 5184 /* scanning for PCI controllers */ 4565 5185 if (pci_register_driver(&gdth_pci_driver)) { 4566 5186 gdth_ha_str *ha; ··· 4549 5209 gdth_remove_one(ha); 4550 5210 return -ENODEV; 4551 5211 } 4552 - #endif /* CONFIG_PCI */ 4553 5212 4554 5213 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count)); 4555 5214 ··· 4569 5230 del_timer_sync(&gdth_timer); 4570 5231 #endif 4571 5232 4572 - #ifdef CONFIG_PCI 4573 5233 pci_unregister_driver(&gdth_pci_driver); 4574 - #endif 4575 5234 4576 5235 list_for_each_entry(ha, &gdth_instances, list) 4577 5236 gdth_remove_one(ha);
-30
drivers/scsi/gdth.h
··· 38 38 #define OEM_ID_INTEL 0x8000 39 39 40 40 /* controller classes */ 41 - #define GDT_ISA 0x01 /* ISA controller */ 42 - #define GDT_EISA 0x02 /* EISA controller */ 43 41 #define GDT_PCI 0x03 /* PCI controller */ 44 42 #define GDT_PCINEW 0x04 /* new PCI controller */ 45 43 #define GDT_PCIMPR 0x05 /* PCI MPR controller */ 46 - /* GDT_EISA, controller subtypes EISA */ 47 - #define GDT3_ID 0x0130941c /* GDT3000/3020 */ 48 - #define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */ 49 - #define GDT3B_ID 0x0330941c /* GDT3000B/3010A */ 50 - /* GDT_ISA */ 51 - #define GDT2_ID 0x0120941c /* GDT2000/2020 */ 52 44 53 45 #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0 54 46 /* GDT_PCI */ ··· 272 280 /* data directions */ 273 281 #define GDTH_DATA_IN 0x01000000L /* data from target */ 274 282 #define GDTH_DATA_OUT 0x00000000L /* data to target */ 275 - 276 - /* BMIC registers (EISA controllers) */ 277 - #define ID0REG 0x0c80 /* board ID */ 278 - #define EINTENABREG 0x0c89 /* interrupt enable */ 279 - #define SEMA0REG 0x0c8a /* command semaphore */ 280 - #define SEMA1REG 0x0c8b /* status semaphore */ 281 - #define LDOORREG 0x0c8d /* local doorbell */ 282 - #define EDENABREG 0x0c8e /* EISA system doorbell enab. */ 283 - #define EDOORREG 0x0c8f /* EISA system doorbell */ 284 - #define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */ 285 - #define EISAREG 0x0cc0 /* EISA configuration */ 286 283 287 284 /* other defines */ 288 285 #define LINUX_OS 8 /* used for cache optim. */ ··· 687 706 u8 fw_magic; /* contr. ID from firmware */ 688 707 } __attribute__((packed)) gdt_pci_sram; 689 708 690 - /* SRAM structure EISA controllers (but NOT GDT3000/3020) */ 691 - typedef struct { 692 - u8 os_used[16]; /* OS code per service */ 693 - u16 need_deinit; /* switch betw. BIOS/driver */ 694 - u8 switch_support; /* see need_deinit */ 695 - u8 padding; 696 - } __attribute__((packed)) gdt_eisa_sram; 697 - 698 - 699 709 /* DPRAM ISA controllers */ 700 710 typedef struct { 701 711 union { 702 712 struct { 703 713 u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */ 704 - u32 magic; /* controller (EISA) ID */ 705 714 u16 need_deinit; /* switch betw. BIOS/driver */ 706 715 u8 switch_support; /* see need_deinit */ 707 716 u8 padding[9]; ··· 814 843 u16 cache_feat; /* feat. cache serv. (s/g,..)*/ 815 844 u16 raw_feat; /* feat. raw service (s/g,..)*/ 816 845 u16 screen_feat; /* feat. raw service (s/g,..)*/ 817 - u16 bmic; /* BMIC address (EISA) */ 818 846 void __iomem *brd; /* DPRAM address */ 819 847 u32 brd_phys; /* slot number/BIOS address */ 820 848 gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */