[IA64] Two trivial spelling fixes

s/addres/address/
s/performanc/performance/

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

authored by Joe Perches and committed by Tony Luck 313d8e57 aec103bf

+2 -2
+1 -1
arch/ia64/sn/pci/tioce_provider.c
··· 41 41 * } else 42 42 * do desired mmr access 43 43 * 44 - * According to hw, we can use reads instead of writes to the above addres 44 + * According to hw, we can use reads instead of writes to the above address 45 45 * 46 46 * Note this WAR can only to be used for accessing internal MMR's in the 47 47 * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
+1 -1
include/asm-ia64/hw_irq.h
··· 63 63 #define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) 64 64 65 65 #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ 66 - #define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */ 66 + #define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */ 67 67 #define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ 68 68 #define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ 69 69 #define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */