clocksource: mips-gic-timer: Enable counter when CPUs start

In multi-cluster MIPS I6500 systems there is a GIC in each cluster,
each with its own counter. When a cluster powers up the counter will
be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register.

In single cluster systems, it has been fine to clear COUNTSTOP once
in gic_clocksource_of_init() to start the counter. In multi-cluster
systems, this will only have started the counter in the boot cluster,
and any CPUs in other clusters will find their counter stopped which
will break the GIC clock_event_device.

Resolve this by having CPUs clear the COUNTSTOP bit when they come
online, using the existing gic_starting_cpu() CPU hotplug callback. This
will allow CPUs in secondary clusters to ensure that the cluster's GIC
counter is running as expected.

Signed-off-by: Paul Burton <[e-mail]>
Signed-off-by: Chao-ying Fu <[e-mail]>
Signed-off-by: Dragan Mladjenovic <[e-mail]>
Signed-off-by: Aleksandar Rikalo <[e-mail]>
Reviewed-by: Philippe Mathieu-Daudé <[e-mail]>
Tested-by: Serge Semin <[e-mail]>
Tested-by: Gregory CLEMENT <[e-mail]>
Acked-by: Daniel Lezcano <[e-mail]>
Signed-off-by: Thomas Bogendoerfer <[e-mail]>

drivers/clocksource/mips-gic-timer.c

···
 
 static int gic_starting_cpu(unsigned int cpu)
 {
+	/* Ensure the GIC counter is running */
+	clear_gic_config(GIC_CONFIG_COUNTSTOP);
+
 	gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
 	return 0;
 }
···
 		if (clk_notifier_register(clk, &gic_clk_nb) < 0)
 			pr_warn("Unable to register clock notifier\n");
 	}
-
-	/* And finally start the counter */
-	clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
 	/*
 	 * It's safe to use the MIPS GIC timer as a sched clock source only if