tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
This patch adds documentation for the uncore PMUs on HiSilicon SoC.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
authored by
Shaokun Zhang
and committed by
Will Deacon
3125b5b2
d5d9696b
+53
+53
Documentation/perf/hisi-pmu.txt
+53
Documentation/perf/hisi-pmu.txt
···
1
+
HiSilicon SoC uncore Performance Monitoring Unit (PMU)
2
+
======================================================
3
+
The HiSilicon SoC chip includes various independent system device PMUs
4
+
such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
5
+
independent and have hardware logic to gather statistics and performance
6
+
information.
7
+
8
+
The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
9
+
(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
10
+
called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
11
+
two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
12
+
13
+
HiSilicon SoC uncore PMU driver
14
+
---------------------------------------
15
+
Each device PMU has separate registers for event counting, control and
16
+
interrupt, and the PMU driver shall register perf PMU drivers like L3C,
17
+
HHA and DDRC etc. The available events and configuration options shall
18
+
be described in the sysfs, see :
19
+
/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
20
+
/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
21
+
The "perf list" command shall list the available events from sysfs.
22
+
23
+
Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
24
+
name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
25
+
where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
26
+
module.
27
+
e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
28
+
SCCL ID #3.
29
+
e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
30
+
SCCL ID #1.
31
+
32
+
The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
33
+
ID used to count the uncore PMU event.
34
+
35
+
Example usage of perf:
36
+
$# perf list
37
+
hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
38
+
------------------------------------------
39
+
hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
40
+
------------------------------------------
41
+
hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
42
+
------------------------------------------
43
+
hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
44
+
------------------------------------------
45
+
46
+
$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
47
+
$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
48
+
49
+
The current driver does not support sampling. So "perf record" is unsupported.
50
+
Also attach to a task is unsupported as the events are all uncore.
51
+
52
+
Note: Please contact the maintainer for a complete list of events supported for
53
+
the PMU devices in the SoC and its information if needed.