clk: meson: axg: Remove MIPI enable clock gate

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

authored by

Remi Pommarel and committed by

Jerome Brunet 5 years ago 31035839 dcd48b25

-4

2 changed files

expand all

drivers

clk

meson

axg.c

axg.h

-3

drivers/clk/meson/axg.c

··· 1879 1879 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 1880 1880 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1881 1881 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 1882 - static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29); 1883 1882 1884 1883 /* Always On (AO) domain gates */ 1885 1884 ··· 1973 1974 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1974 1975 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1975 1976 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1976 - [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw, 1977 1977 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1978 1978 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1979 1979 [CLKID_GEN_CLK] = &axg_gen_clk.hw, ··· 2113 2115 &axg_pcie_ref, 2114 2116 &axg_pcie_cml_en0, 2115 2117 &axg_pcie_cml_en1, 2116 - &axg_mipi_enable, 2117 2118 &axg_gen_clk_sel, 2118 2119 &axg_gen_clk_div, 2119 2120 &axg_gen_clk,

-1

drivers/clk/meson/axg.h

··· 16 16 * Register offsets from the data sheet must be multiplied by 4 before 17 17 * adding them to the base address to get the right value. 18 18 */ 19 - #define HHI_MIPI_CNTL0 0x00 20 19 #define HHI_GP0_PLL_CNTL 0x40 21 20 #define HHI_GP0_PLL_CNTL2 0x44 22 21 #define HHI_GP0_PLL_CNTL3 0x48