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linux
ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml
1. Change node name to match '^serial(@[0-9a-f,]+)*$'
2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same
clock.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+16
-16
+12
-12
arch/arm/boot/dts/hip01.dtsi
+12
-12
arch/arm/boot/dts/hip01.dtsi
···
41
41
compatible = "simple-bus";
42
42
ranges;
43
43
44
-
uart0: uart@10001000 {
44
+
uart0: serial@10001000 {
45
45
compatible = "snps,dw-apb-uart";
46
46
reg = <0x10001000 0x1000>;
47
-
clocks = <&hisi_refclk144mhz>;
48
-
clock-names = "apb_pclk";
47
+
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
48
+
clock-names = "baudclk", "apb_pclk";
49
49
reg-shift = <2>;
50
50
interrupts = <0 32 4>;
51
51
status = "disabled";
52
52
};
53
53
54
-
uart1: uart@10002000 {
54
+
uart1: serial@10002000 {
55
55
compatible = "snps,dw-apb-uart";
56
56
reg = <0x10002000 0x1000>;
57
-
clocks = <&hisi_refclk144mhz>;
58
-
clock-names = "apb_pclk";
57
+
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
58
+
clock-names = "baudclk", "apb_pclk";
59
59
reg-shift = <2>;
60
60
interrupts = <0 33 4>;
61
61
status = "disabled";
62
62
};
63
63
64
-
uart2: uart@10003000 {
64
+
uart2: serial@10003000 {
65
65
compatible = "snps,dw-apb-uart";
66
66
reg = <0x10003000 0x1000>;
67
-
clocks = <&hisi_refclk144mhz>;
68
-
clock-names = "apb_pclk";
67
+
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
68
+
clock-names = "baudclk", "apb_pclk";
69
69
reg-shift = <2>;
70
70
interrupts = <0 34 4>;
71
71
status = "disabled";
72
72
};
73
73
74
-
uart3: uart@10006000 {
74
+
uart3: serial@10006000 {
75
75
compatible = "snps,dw-apb-uart";
76
76
reg = <0x10006000 0x1000>;
77
-
clocks = <&hisi_refclk144mhz>;
78
-
clock-names = "apb_pclk";
77
+
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
78
+
clock-names = "baudclk", "apb_pclk";
79
79
reg-shift = <2>;
80
80
interrupts = <0 4 4>;
81
81
status = "disabled";
+1
-1
arch/arm/boot/dts/hip04-d01.dts
+1
-1
arch/arm/boot/dts/hip04-d01.dts
+3
-3
arch/arm/boot/dts/hip04.dtsi
+3
-3
arch/arm/boot/dts/hip04.dtsi
···
250
250
<0 79 4>;
251
251
};
252
252
253
-
uart0: uart@4007000 {
253
+
uart0: serial@4007000 {
254
254
compatible = "snps,dw-apb-uart";
255
255
reg = <0x4007000 0x1000>;
256
256
interrupts = <0 381 4>;
257
-
clocks = <&clk_168m>;
258
-
clock-names = "uartclk";
257
+
clocks = <&clk_168m>, <&clk_168m>;
258
+
clock-names = "baudclk", "apb_pclk";
259
259
reg-shift = <2>;
260
260
status = "disabled";
261
261
};