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Merge tag 'tegra-for-4.16-dt-bindings' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Pull "dt-bindings: Updates for v4.16-rc1" from Thierry Reding:
This contains a set of patches that extend existing bindings with support
for Tegra186.
* tag 'tegra-for-4.16-dt-bindings' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: memory: Add Tegra186 support
dt-bindings: misc: Add Tegra186 MISC registers bindings
+125
+2
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
+2
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
···
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- clock-names: Must include the following entries:
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- mc: the module's clock input
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- interrupts: The interrupt outputs from the controller.
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Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
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- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
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the SWGROUP of the master.
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+12
Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
+12
Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
···
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NVIDIA Tegra186 MISC register block
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The MISC register block found on Tegra186 SoCs contains registers that can be
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used to identify a given chip and various strapping options.
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Required properties:
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- compatible: Must be:
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- Tegra186: "nvidia,tegra186-misc"
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- reg: Should contain 2 entries: The first entry gives the physical address
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and length of the register region which contains revision and debug
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features. The second entry specifies the physical address and length
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of the register region indicating the strapping options.
+111
include/dt-bindings/memory/tegra186-mc.h
+111
include/dt-bindings/memory/tegra186-mc.h
···
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#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA186_MC_H
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/* special clients */
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#define TEGRA186_SID_INVALID 0x00
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#define TEGRA186_SID_PASSTHROUGH 0x7f
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/* host1x clients */
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#define TEGRA186_SID_HOST1X 0x01
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#define TEGRA186_SID_CSI 0x02
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#define TEGRA186_SID_VIC 0x03
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#define TEGRA186_SID_VI 0x04
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#define TEGRA186_SID_ISP 0x05
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#define TEGRA186_SID_NVDEC 0x06
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#define TEGRA186_SID_NVENC 0x07
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#define TEGRA186_SID_NVJPG 0x08
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#define TEGRA186_SID_NVDISPLAY 0x09
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#define TEGRA186_SID_TSEC 0x0a
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#define TEGRA186_SID_TSECB 0x0b
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#define TEGRA186_SID_SE 0x0c
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#define TEGRA186_SID_SE1 0x0d
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#define TEGRA186_SID_SE2 0x0e
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#define TEGRA186_SID_SE3 0x0f
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/* GPU clients */
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#define TEGRA186_SID_GPU 0x10
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/* other SoC clients */
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#define TEGRA186_SID_AFI 0x11
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#define TEGRA186_SID_HDA 0x12
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#define TEGRA186_SID_ETR 0x13
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#define TEGRA186_SID_EQOS 0x14
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#define TEGRA186_SID_UFSHC 0x15
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#define TEGRA186_SID_AON 0x16
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#define TEGRA186_SID_SDMMC4 0x17
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#define TEGRA186_SID_SDMMC3 0x18
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#define TEGRA186_SID_SDMMC2 0x19
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#define TEGRA186_SID_SDMMC1 0x1a
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#define TEGRA186_SID_XUSB_HOST 0x1b
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#define TEGRA186_SID_XUSB_DEV 0x1c
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#define TEGRA186_SID_SATA 0x1d
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#define TEGRA186_SID_APE 0x1e
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#define TEGRA186_SID_SCE 0x1f
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/* GPC DMA clients */
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#define TEGRA186_SID_GPCDMA_0 0x20
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#define TEGRA186_SID_GPCDMA_1 0x21
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#define TEGRA186_SID_GPCDMA_2 0x22
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#define TEGRA186_SID_GPCDMA_3 0x23
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#define TEGRA186_SID_GPCDMA_4 0x24
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#define TEGRA186_SID_GPCDMA_5 0x25
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#define TEGRA186_SID_GPCDMA_6 0x26
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#define TEGRA186_SID_GPCDMA_7 0x27
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/* APE DMA clients */
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#define TEGRA186_SID_APE_1 0x28
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#define TEGRA186_SID_APE_2 0x29
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/* camera RTCPU */
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#define TEGRA186_SID_RCE 0x2a
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/* camera RTCPU on host1x address space */
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#define TEGRA186_SID_RCE_1X 0x2b
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/* APE DMA clients */
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#define TEGRA186_SID_APE_3 0x2c
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/* camera RTCPU running on APE */
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#define TEGRA186_SID_APE_CAM 0x2d
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#define TEGRA186_SID_APE_CAM_1X 0x2e
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/*
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* The BPMP has its SID value hardcoded in the firmware. Changing it requires
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* considerable effort.
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*/
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#define TEGRA186_SID_BPMP 0x32
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/* for SMMU tests */
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#define TEGRA186_SID_SMMU_TEST 0x33
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/* host1x virtualization channels */
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#define TEGRA186_SID_HOST1X_CTX0 0x38
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#define TEGRA186_SID_HOST1X_CTX1 0x39
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#define TEGRA186_SID_HOST1X_CTX2 0x3a
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#define TEGRA186_SID_HOST1X_CTX3 0x3b
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#define TEGRA186_SID_HOST1X_CTX4 0x3c
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#define TEGRA186_SID_HOST1X_CTX5 0x3d
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#define TEGRA186_SID_HOST1X_CTX6 0x3e
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#define TEGRA186_SID_HOST1X_CTX7 0x3f
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/* host1x command buffers */
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#define TEGRA186_SID_HOST1X_VM0 0x40
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#define TEGRA186_SID_HOST1X_VM1 0x41
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#define TEGRA186_SID_HOST1X_VM2 0x42
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#define TEGRA186_SID_HOST1X_VM3 0x43
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#define TEGRA186_SID_HOST1X_VM4 0x44
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#define TEGRA186_SID_HOST1X_VM5 0x45
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#define TEGRA186_SID_HOST1X_VM6 0x46
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#define TEGRA186_SID_HOST1X_VM7 0x47
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/* SE data buffers */
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#define TEGRA186_SID_SE_VM0 0x48
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#define TEGRA186_SID_SE_VM1 0x49
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#define TEGRA186_SID_SE_VM2 0x4a
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#define TEGRA186_SID_SE_VM3 0x4b
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#define TEGRA186_SID_SE_VM4 0x4c
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#define TEGRA186_SID_SE_VM5 0x4d
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#define TEGRA186_SID_SE_VM6 0x4e
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#define TEGRA186_SID_SE_VM7 0x4f
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111
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#endif