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Documentation: clk: Fix a trivial typo in audss
Fixes a trivial typo.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
authored by
Sachin Kamat
and committed by
Jiri Kosina
30abda17
9ca18397
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Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
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Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
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The Samsung Audio Subsystem clock controller generates and supplies clocks
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to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
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binding described here is applicable to all SoC's in Exynos family.
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binding described here is applicable to all SoCs in Exynos family.
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Required Properties:
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