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Documentation: clk: Fix a trivial typo in audss

Fixes a trivial typo.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

authored by

Sachin Kamat and committed by
Jiri Kosina
30abda17 9ca18397

+1 -1
+1 -1
Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
··· 2 2 3 3 The Samsung Audio Subsystem clock controller generates and supplies clocks 4 4 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock 5 - binding described here is applicable to all SoC's in Exynos family. 5 + binding described here is applicable to all SoCs in Exynos family. 6 6 7 7 Required Properties: 8 8