tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/powerplay: add header file for tonga smu and dpm
These headers provide the SMU interface used by the driver.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
authored by
yanyang1
and committed by
Alex Deucher
306d8db3
7ff1d70a
+1844
-198
-198
drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
-198
drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
···
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef TONGA_PP_SMC_H
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#define TONGA_PP_SMC_H
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#pragma pack(push, 1)
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#define PPSMC_SWSTATE_FLAG_DC 0x01
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#define PPSMC_SWSTATE_FLAG_UVD 0x02
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#define PPSMC_SWSTATE_FLAG_VCE 0x04
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#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
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#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
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#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
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#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
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#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
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#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
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#define PPSMC_SYSTEMFLAG_GDDR5 0x04
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#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
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#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
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#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
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#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40
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#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
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#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
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#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
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#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
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#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10
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#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20
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#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40
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#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
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#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
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#define PPSMC_DPM2FLAGS_OCP 0x04
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#define PPSMC_DISPLAY_WATERMARK_LOW 0
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#define PPSMC_DISPLAY_WATERMARK_HIGH 1
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#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
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#define PPSMC_STATEFLAG_POWERBOOST 0x02
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#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
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#define PPSMC_STATEFLAG_POWERSHIFT 0x08
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#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
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#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
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#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
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#define FDO_MODE_HARDWARE 0
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#define FDO_MODE_PIECE_WISE_LINEAR 1
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enum FAN_CONTROL {
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FAN_CONTROL_FUZZY,
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FAN_CONTROL_TABLE
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};
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#define PPSMC_Result_OK ((uint16_t)0x01)
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#define PPSMC_Result_NoMore ((uint16_t)0x02)
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#define PPSMC_Result_NotNow ((uint16_t)0x03)
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#define PPSMC_Result_Failed ((uint16_t)0xFF)
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#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
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#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
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typedef uint16_t PPSMC_Result;
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#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
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#define PPSMC_MSG_Halt ((uint16_t)0x10)
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#define PPSMC_MSG_Resume ((uint16_t)0x11)
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#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
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#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
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#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
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#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
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#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
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#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
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#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
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#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
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#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
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#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
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#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
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#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
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#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
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#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
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#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
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#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
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#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
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#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
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#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
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#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
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#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
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#define PPSMC_CACHistoryStart ((uint16_t)0x57)
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#define PPSMC_CACHistoryStop ((uint16_t)0x58)
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#define PPSMC_TDPClampingActive ((uint16_t)0x59)
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#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
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#define PPSMC_StartFanControl ((uint16_t)0x5B)
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#define PPSMC_StopFanControl ((uint16_t)0x5C)
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#define PPSMC_NoDisplay ((uint16_t)0x5D)
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#define PPSMC_HasDisplay ((uint16_t)0x5E)
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#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
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#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
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#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
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#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
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#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
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#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
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#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
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#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
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#define PPSMC_OCPActive ((uint16_t)0x6C)
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#define PPSMC_OCPInactive ((uint16_t)0x6D)
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#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
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#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
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#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
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#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
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#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
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#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
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#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
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#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
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#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
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#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
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#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
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#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
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#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
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#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
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#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
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#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
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#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
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#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
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#define PPSMC_FlushDataCache ((uint16_t)0x80)
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#define PPSMC_FlushInstrCache ((uint16_t)0x81)
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#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
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#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
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#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
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#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
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#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
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#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
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#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
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#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
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#define PPSMC_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A)
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#define PPSMC_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B)
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#define PPSMC_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C)
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#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90)
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#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91)
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#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92)
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#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93)
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#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94)
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#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95)
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#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96)
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#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97)
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#define PPSMC_MSG_GPIO17 ((uint16_t)0x98)
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#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99)
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#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A)
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#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B)
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#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C)
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#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D)
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#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E)
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#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
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#define PPSMC_MSG_Test ((uint16_t)0x100)
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#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t)0x250)
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#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t)0x251)
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#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t)0x252)
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#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t)0x253)
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#define PPSMC_MSG_LoadUcodes ((uint16_t)0x254)
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typedef uint16_t PPSMC_Msg;
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#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
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#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
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#define PPSMC_EVENT_STATUS_DC 0x00000004
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#define PPSMC_EVENT_STATUS_GPIO17 0x00000008
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#pragma pack(pop)
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#endif
+664
drivers/gpu/drm/amd/powerplay/inc/smu72.h
+664
drivers/gpu/drm/amd/powerplay/inc/smu72.h
···
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#ifndef SMU72_H
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#define SMU72_H
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#if !defined(SMC_MICROCODE)
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#pragma pack(push, 1)
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#endif
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 4
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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enum SID_OPTION {
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SID_OPTION_HI,
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SID_OPTION_LO,
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SID_OPTION_COUNT
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};
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enum Poly3rdOrderCoeff {
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LEAKAGE_TEMPERATURE_SCALAR,
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LEAKAGE_VOLTAGE_SCALAR,
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DYNAMIC_VOLTAGE_SCALAR,
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POLY_3RD_ORDER_COUNT
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};
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struct SMU7_Poly3rdOrder_Data {
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int32_t a;
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int32_t b;
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int32_t c;
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int32_t d;
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uint8_t a_shift;
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uint8_t b_shift;
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uint8_t c_shift;
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uint8_t x_shift;
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};
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typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
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struct Power_Calculator_Data {
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uint16_t NoLoadVoltage;
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uint16_t LoadVoltage;
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uint16_t Resistance;
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uint16_t Temperature;
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uint16_t BaseLeakage;
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uint16_t LkgTempScalar;
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uint16_t LkgVoltScalar;
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uint16_t LkgAreaScalar;
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uint16_t LkgPower;
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uint16_t DynVoltScalar;
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uint32_t Cac;
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uint32_t DynPower;
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uint32_t TotalCurrent;
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uint32_t TotalPower;
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};
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typedef struct Power_Calculator_Data PowerCalculatorData_t;
57
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struct Gc_Cac_Weight_Data {
59
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uint8_t index;
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uint32_t value;
61
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};
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typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
64
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typedef struct {
67
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uint32_t high;
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uint32_t low;
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} data_64_t;
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typedef struct {
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data_64_t high;
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data_64_t low;
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} data_128_t;
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76
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#define SMU7_CONTEXT_ID_SMC 1
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#define SMU7_CONTEXT_ID_VBIOS 2
78
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#define SMU72_MAX_LEVELS_VDDC 16
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#define SMU72_MAX_LEVELS_VDDGFX 16
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#define SMU72_MAX_LEVELS_VDDCI 8
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#define SMU72_MAX_LEVELS_MVDD 4
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#define SMU_MAX_SMIO_LEVELS 4
85
+
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#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
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#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
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#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
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#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */
90
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#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */
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#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */
92
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#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */
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#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */
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#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */
95
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#define DPM_NO_LIMIT 0
97
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#define DPM_NO_UP 1
98
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#define DPM_GO_DOWN 2
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#define DPM_GO_UP 3
100
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101
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#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
102
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#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
103
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104
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#define GPIO_CLAMP_MODE_VRHOT 1
105
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#define GPIO_CLAMP_MODE_THERM 2
106
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#define GPIO_CLAMP_MODE_DC 4
107
+
108
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#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
109
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#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
110
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#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
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#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
112
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#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
113
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#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
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#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
115
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#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
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#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
117
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#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
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#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
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#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
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#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
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#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
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#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
125
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#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
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#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
127
+
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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+
129
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/* Virtualization Defines */
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+
#define CG_XDMA_MASK 0x1
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#define CG_XDMA_SHIFT 0
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#define CG_UVD_MASK 0x2
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#define CG_UVD_SHIFT 1
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#define CG_VCE_MASK 0x4
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#define CG_VCE_SHIFT 2
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#define CG_SAMU_MASK 0x8
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#define CG_SAMU_SHIFT 3
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#define CG_GFX_MASK 0x10
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#define CG_GFX_SHIFT 4
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#define CG_SDMA_MASK 0x20
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#define CG_SDMA_SHIFT 5
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#define CG_HDP_MASK 0x40
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#define CG_HDP_SHIFT 6
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#define CG_MC_MASK 0x80
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#define CG_MC_SHIFT 7
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#define CG_DRM_MASK 0x100
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#define CG_DRM_SHIFT 8
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#define CG_ROM_MASK 0x200
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#define CG_ROM_SHIFT 9
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#define CG_BIF_MASK 0x400
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#define CG_BIF_SHIFT 10
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+
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#define SMU72_DTE_ITERATIONS 5
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#define SMU72_DTE_SOURCES 3
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#define SMU72_DTE_SINKS 1
156
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#define SMU72_NUM_CPU_TES 0
157
+
#define SMU72_NUM_GPU_TES 1
158
+
#define SMU72_NUM_NON_TES 2
159
+
#define SMU72_DTE_FAN_SCALAR_MIN 0x100
160
+
#define SMU72_DTE_FAN_SCALAR_MAX 0x166
161
+
#define SMU72_DTE_FAN_TEMP_MAX 93
162
+
#define SMU72_DTE_FAN_TEMP_MIN 83
163
+
164
+
#if defined SMU__FUSION_ONLY
165
+
#define SMU7_DTE_ITERATIONS 5
166
+
#define SMU7_DTE_SOURCES 5
167
+
#define SMU7_DTE_SINKS 3
168
+
#define SMU7_NUM_CPU_TES 2
169
+
#define SMU7_NUM_GPU_TES 1
170
+
#define SMU7_NUM_NON_TES 2
171
+
#endif
172
+
173
+
struct SMU7_HystController_Data {
174
+
uint8_t waterfall_up;
175
+
uint8_t waterfall_down;
176
+
uint8_t waterfall_limit;
177
+
uint8_t spare;
178
+
uint16_t release_cnt;
179
+
uint16_t release_limit;
180
+
};
181
+
182
+
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
183
+
184
+
struct SMU72_PIDController {
185
+
uint32_t Ki;
186
+
int32_t LFWindupUpperLim;
187
+
int32_t LFWindupLowerLim;
188
+
uint32_t StatePrecision;
189
+
uint32_t LfPrecision;
190
+
uint32_t LfOffset;
191
+
uint32_t MaxState;
192
+
uint32_t MaxLfFraction;
193
+
uint32_t StateShift;
194
+
};
195
+
196
+
typedef struct SMU72_PIDController SMU72_PIDController;
197
+
198
+
struct SMU7_LocalDpmScoreboard {
199
+
uint32_t PercentageBusy;
200
+
201
+
int32_t PIDError;
202
+
int32_t PIDIntegral;
203
+
int32_t PIDOutput;
204
+
205
+
uint32_t SigmaDeltaAccum;
206
+
uint32_t SigmaDeltaOutput;
207
+
uint32_t SigmaDeltaLevel;
208
+
209
+
uint32_t UtilizationSetpoint;
210
+
211
+
uint8_t TdpClampMode;
212
+
uint8_t TdcClampMode;
213
+
uint8_t ThermClampMode;
214
+
uint8_t VoltageBusy;
215
+
216
+
int8_t CurrLevel;
217
+
int8_t TargLevel;
218
+
uint8_t LevelChangeInProgress;
219
+
uint8_t UpHyst;
220
+
221
+
uint8_t DownHyst;
222
+
uint8_t VoltageDownHyst;
223
+
uint8_t DpmEnable;
224
+
uint8_t DpmRunning;
225
+
226
+
uint8_t DpmForce;
227
+
uint8_t DpmForceLevel;
228
+
uint8_t DisplayWatermark;
229
+
uint8_t McArbIndex;
230
+
231
+
uint32_t MinimumPerfSclk;
232
+
233
+
uint8_t AcpiReq;
234
+
uint8_t AcpiAck;
235
+
uint8_t GfxClkSlow;
236
+
uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
237
+
238
+
uint8_t FpsFilterWeight;
239
+
uint8_t EnabledLevelsChange;
240
+
uint8_t DteClampMode;
241
+
uint8_t FpsClampMode;
242
+
243
+
uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
244
+
uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
245
+
246
+
void (*TargetStateCalculator)(uint8_t);
247
+
void (*SavedTargetStateCalculator)(uint8_t);
248
+
249
+
uint16_t AutoDpmInterval;
250
+
uint16_t AutoDpmRange;
251
+
252
+
uint8_t FpsEnabled;
253
+
uint8_t MaxPerfLevel;
254
+
uint8_t AllowLowClkInterruptToHost;
255
+
uint8_t FpsRunning;
256
+
257
+
uint32_t MaxAllowedFrequency;
258
+
259
+
uint32_t FilteredSclkFrequency;
260
+
uint32_t LastSclkFrequency;
261
+
uint32_t FilteredSclkFrequencyCnt;
262
+
};
263
+
264
+
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
265
+
266
+
#define SMU7_MAX_VOLTAGE_CLIENTS 12
267
+
268
+
typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
269
+
270
+
struct SMU_VoltageLevel {
271
+
uint8_t Vddc;
272
+
uint8_t Vddci;
273
+
uint8_t VddGfx;
274
+
uint8_t Phases;
275
+
};
276
+
277
+
typedef struct SMU_VoltageLevel SMU_VoltageLevel;
278
+
279
+
struct SMU7_VoltageScoreboard {
280
+
SMU_VoltageLevel CurrentVoltage;
281
+
SMU_VoltageLevel TargetVoltage;
282
+
uint16_t MaxVid;
283
+
uint8_t HighestVidOffset;
284
+
uint8_t CurrentVidOffset;
285
+
286
+
uint8_t ControllerBusy;
287
+
uint8_t CurrentVid;
288
+
uint8_t CurrentVddciVid;
289
+
uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
290
+
291
+
SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
292
+
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
293
+
294
+
uint8_t TargetIndex;
295
+
uint8_t Delay;
296
+
uint8_t ControllerEnable;
297
+
uint8_t ControllerRunning;
298
+
uint16_t CurrentStdVoltageHiSidd;
299
+
uint16_t CurrentStdVoltageLoSidd;
300
+
uint8_t OverrideVoltage;
301
+
uint8_t VddcUseUlvOffset;
302
+
uint8_t VddGfxUseUlvOffset;
303
+
uint8_t padding;
304
+
305
+
VoltageChangeHandler_t ChangeVddc;
306
+
VoltageChangeHandler_t ChangeVddGfx;
307
+
VoltageChangeHandler_t ChangeVddci;
308
+
VoltageChangeHandler_t ChangePhase;
309
+
VoltageChangeHandler_t ChangeMvdd;
310
+
311
+
VoltageChangeHandler_t functionLinks[6];
312
+
313
+
uint8_t *VddcFollower1;
314
+
uint8_t *VddcFollower2;
315
+
int16_t Driver_OD_RequestedVidOffset1;
316
+
int16_t Driver_OD_RequestedVidOffset2;
317
+
318
+
};
319
+
320
+
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
321
+
322
+
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
323
+
324
+
struct SMU7_PCIeLinkSpeedScoreboard {
325
+
uint8_t DpmEnable;
326
+
uint8_t DpmRunning;
327
+
uint8_t DpmForce;
328
+
uint8_t DpmForceLevel;
329
+
330
+
uint8_t CurrentLinkSpeed;
331
+
uint8_t EnabledLevelsChange;
332
+
uint16_t AutoDpmInterval;
333
+
334
+
uint16_t AutoDpmRange;
335
+
uint16_t AutoDpmCount;
336
+
337
+
uint8_t DpmMode;
338
+
uint8_t AcpiReq;
339
+
uint8_t AcpiAck;
340
+
uint8_t CurrentLinkLevel;
341
+
342
+
};
343
+
344
+
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
345
+
346
+
/* -------------------------------------------------------- CAC table ------------------------------------------------------ */
347
+
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
348
+
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
349
+
#define SMU7_SCALE_I 7
350
+
#define SMU7_SCALE_R 12
351
+
352
+
struct SMU7_PowerScoreboard {
353
+
PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
354
+
PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
355
+
356
+
uint32_t TotalGpuPower;
357
+
uint32_t TdcCurrent;
358
+
359
+
uint16_t VddciTotalPower;
360
+
uint16_t sparesasfsdfd;
361
+
uint16_t Vddr1Power;
362
+
uint16_t RocPower;
363
+
364
+
uint16_t CalcMeasPowerBlend;
365
+
uint8_t SidOptionPower;
366
+
uint8_t SidOptionCurrent;
367
+
368
+
uint32_t WinTime;
369
+
370
+
uint16_t Telemetry_1_slope;
371
+
uint16_t Telemetry_2_slope;
372
+
int32_t Telemetry_1_offset;
373
+
int32_t Telemetry_2_offset;
374
+
375
+
uint32_t VddcCurrentTelemetry;
376
+
uint32_t VddGfxCurrentTelemetry;
377
+
uint32_t VddcPowerTelemetry;
378
+
uint32_t VddGfxPowerTelemetry;
379
+
uint32_t VddciPowerTelemetry;
380
+
381
+
uint32_t VddcPower;
382
+
uint32_t VddGfxPower;
383
+
uint32_t VddciPower;
384
+
385
+
uint32_t TelemetryCurrent[2];
386
+
uint32_t TelemetryVoltage[2];
387
+
uint32_t TelemetryPower[2];
388
+
};
389
+
390
+
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
391
+
392
+
struct SMU7_ThermalScoreboard {
393
+
int16_t GpuLimit;
394
+
int16_t GpuHyst;
395
+
uint16_t CurrGnbTemp;
396
+
uint16_t FilteredGnbTemp;
397
+
398
+
uint8_t ControllerEnable;
399
+
uint8_t ControllerRunning;
400
+
uint8_t AutoTmonCalInterval;
401
+
uint8_t AutoTmonCalEnable;
402
+
403
+
uint8_t ThermalDpmEnabled;
404
+
uint8_t SclkEnabledMask;
405
+
uint8_t spare[2];
406
+
int32_t temperature_gradient;
407
+
408
+
SMU7_HystController_Data HystControllerData;
409
+
int32_t WeightedSensorTemperature;
410
+
uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
411
+
uint32_t Alpha;
412
+
};
413
+
414
+
typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
415
+
416
+
/* For FeatureEnables: */
417
+
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
418
+
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
419
+
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
420
+
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
421
+
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
422
+
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
423
+
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
424
+
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
425
+
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
426
+
427
+
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
428
+
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
429
+
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
430
+
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
431
+
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
432
+
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
433
+
434
+
/* All 'soft registers' should be uint32_t. */
435
+
struct SMU72_SoftRegisters {
436
+
uint32_t RefClockFrequency;
437
+
uint32_t PmTimerPeriod;
438
+
uint32_t FeatureEnables;
439
+
440
+
uint32_t PreVBlankGap;
441
+
uint32_t VBlankTimeout;
442
+
uint32_t TrainTimeGap;
443
+
444
+
uint32_t MvddSwitchTime;
445
+
uint32_t LongestAcpiTrainTime;
446
+
uint32_t AcpiDelay;
447
+
uint32_t G5TrainTime;
448
+
uint32_t DelayMpllPwron;
449
+
uint32_t VoltageChangeTimeout;
450
+
451
+
uint32_t HandshakeDisables;
452
+
453
+
uint8_t DisplayPhy1Config;
454
+
uint8_t DisplayPhy2Config;
455
+
uint8_t DisplayPhy3Config;
456
+
uint8_t DisplayPhy4Config;
457
+
458
+
uint8_t DisplayPhy5Config;
459
+
uint8_t DisplayPhy6Config;
460
+
uint8_t DisplayPhy7Config;
461
+
uint8_t DisplayPhy8Config;
462
+
463
+
uint32_t AverageGraphicsActivity;
464
+
uint32_t AverageMemoryActivity;
465
+
uint32_t AverageGioActivity;
466
+
467
+
uint8_t SClkDpmEnabledLevels;
468
+
uint8_t MClkDpmEnabledLevels;
469
+
uint8_t LClkDpmEnabledLevels;
470
+
uint8_t PCIeDpmEnabledLevels;
471
+
472
+
uint8_t UVDDpmEnabledLevels;
473
+
uint8_t SAMUDpmEnabledLevels;
474
+
uint8_t ACPDpmEnabledLevels;
475
+
uint8_t VCEDpmEnabledLevels;
476
+
477
+
uint32_t DRAM_LOG_ADDR_H;
478
+
uint32_t DRAM_LOG_ADDR_L;
479
+
uint32_t DRAM_LOG_PHY_ADDR_H;
480
+
uint32_t DRAM_LOG_PHY_ADDR_L;
481
+
uint32_t DRAM_LOG_BUFF_SIZE;
482
+
uint32_t UlvEnterCount;
483
+
uint32_t UlvTime;
484
+
uint32_t UcodeLoadStatus;
485
+
uint32_t Reserved[2];
486
+
487
+
};
488
+
489
+
typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
490
+
491
+
struct SMU72_Firmware_Header {
492
+
uint32_t Digest[5];
493
+
uint32_t Version;
494
+
uint32_t HeaderSize;
495
+
uint32_t Flags;
496
+
uint32_t EntryPoint;
497
+
uint32_t CodeSize;
498
+
uint32_t ImageSize;
499
+
500
+
uint32_t Rtos;
501
+
uint32_t SoftRegisters;
502
+
uint32_t DpmTable;
503
+
uint32_t FanTable;
504
+
uint32_t CacConfigTable;
505
+
uint32_t CacStatusTable;
506
+
uint32_t mcRegisterTable;
507
+
uint32_t mcArbDramTimingTable;
508
+
uint32_t PmFuseTable;
509
+
uint32_t Globals;
510
+
uint32_t ClockStretcherTable;
511
+
uint32_t Reserved[41];
512
+
uint32_t Signature;
513
+
};
514
+
515
+
typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
516
+
517
+
#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
518
+
519
+
enum DisplayConfig {
520
+
PowerDown = 1,
521
+
DP54x4,
522
+
DP54x2,
523
+
DP54x1,
524
+
DP27x4,
525
+
DP27x2,
526
+
DP27x1,
527
+
HDMI297,
528
+
HDMI162,
529
+
LVDS,
530
+
DP324x4,
531
+
DP324x2,
532
+
DP324x1
533
+
};
534
+
535
+
#define MC_BLOCK_COUNT 1
536
+
#define CPL_BLOCK_COUNT 5
537
+
#define SE_BLOCK_COUNT 15
538
+
#define GC_BLOCK_COUNT 24
539
+
540
+
struct SMU7_Local_Cac {
541
+
uint8_t BlockId;
542
+
uint8_t SignalId;
543
+
uint8_t Threshold;
544
+
uint8_t Padding;
545
+
};
546
+
547
+
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
548
+
549
+
struct SMU7_Local_Cac_Table {
550
+
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
551
+
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
552
+
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
553
+
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
554
+
};
555
+
556
+
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
557
+
558
+
#if !defined(SMC_MICROCODE)
559
+
#pragma pack(pop)
560
+
#endif
561
+
562
+
/* Description of Clock Gating bitmask for Tonga: */
563
+
/* System Clock Gating */
564
+
#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */
565
+
#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */
566
+
#define CG_SYS_BIF_MGLS_SHIFT 0
567
+
#define CG_SYS_ROM_SHIFT 1
568
+
#define CG_SYS_MC_MGCG_SHIFT 2
569
+
#define CG_SYS_MC_MGLS_SHIFT 3
570
+
#define CG_SYS_SDMA_MGCG_SHIFT 4
571
+
#define CG_SYS_SDMA_MGLS_SHIFT 5
572
+
#define CG_SYS_DRM_MGCG_SHIFT 6
573
+
#define CG_SYS_HDP_MGCG_SHIFT 7
574
+
#define CG_SYS_HDP_MGLS_SHIFT 8
575
+
#define CG_SYS_DRM_MGLS_SHIFT 9
576
+
577
+
#define CG_SYS_BIF_MGLS_MASK 0x1
578
+
#define CG_SYS_ROM_MASK 0x2
579
+
#define CG_SYS_MC_MGCG_MASK 0x4
580
+
#define CG_SYS_MC_MGLS_MASK 0x8
581
+
#define CG_SYS_SDMA_MGCG_MASK 0x10
582
+
#define CG_SYS_SDMA_MGLS_MASK 0x20
583
+
#define CG_SYS_DRM_MGCG_MASK 0x40
584
+
#define CG_SYS_HDP_MGCG_MASK 0x80
585
+
#define CG_SYS_HDP_MGLS_MASK 0x100
586
+
#define CG_SYS_DRM_MGLS_MASK 0x200
587
+
588
+
/* Graphics Clock Gating */
589
+
#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */
590
+
#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */
591
+
#define CG_GFX_CGCG_SHIFT 16
592
+
#define CG_GFX_CGLS_SHIFT 17
593
+
#define CG_CPF_MGCG_SHIFT 18
594
+
#define CG_RLC_MGCG_SHIFT 19
595
+
#define CG_GFX_OTHERS_MGCG_SHIFT 20
596
+
597
+
#define CG_GFX_CGCG_MASK 0x00010000
598
+
#define CG_GFX_CGLS_MASK 0x00020000
599
+
#define CG_CPF_MGCG_MASK 0x00040000
600
+
#define CG_RLC_MGCG_MASK 0x00080000
601
+
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
602
+
603
+
/* Voltage Regulator Configuration */
604
+
/* VR Config info is contained in dpmTable.VRConfig */
605
+
606
+
#define VRCONF_VDDC_MASK 0x000000FF
607
+
#define VRCONF_VDDC_SHIFT 0
608
+
#define VRCONF_VDDGFX_MASK 0x0000FF00
609
+
#define VRCONF_VDDGFX_SHIFT 8
610
+
#define VRCONF_VDDCI_MASK 0x00FF0000
611
+
#define VRCONF_VDDCI_SHIFT 16
612
+
#define VRCONF_MVDD_MASK 0xFF000000
613
+
#define VRCONF_MVDD_SHIFT 24
614
+
615
+
#define VR_MERGED_WITH_VDDC 0
616
+
#define VR_SVI2_PLANE_1 1
617
+
#define VR_SVI2_PLANE_2 2
618
+
#define VR_SMIO_PATTERN_1 3
619
+
#define VR_SMIO_PATTERN_2 4
620
+
#define VR_STATIC_VOLTAGE 5
621
+
622
+
/* Clock Stretcher Configuration */
623
+
624
+
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
625
+
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
626
+
627
+
/* The 'settings' field is subdivided in the following way: */
628
+
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
629
+
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
630
+
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
631
+
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
632
+
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
633
+
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
634
+
635
+
struct SMU_ClockStretcherDataTableEntry {
636
+
uint8_t minVID;
637
+
uint8_t maxVID;
638
+
639
+
uint16_t setting;
640
+
};
641
+
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
642
+
643
+
struct SMU_ClockStretcherDataTable {
644
+
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
645
+
};
646
+
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
647
+
648
+
struct SMU_CKS_LOOKUPTableEntry {
649
+
uint16_t minFreq;
650
+
uint16_t maxFreq;
651
+
652
+
uint8_t setting;
653
+
uint8_t padding[3];
654
+
};
655
+
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
656
+
657
+
struct SMU_CKS_LOOKUPTable {
658
+
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
659
+
};
660
+
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
661
+
662
+
#endif
663
+
664
+
+760
drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h
+760
drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h
···
1
+
#ifndef SMU72_DISCRETE_H
2
+
#define SMU72_DISCRETE_H
3
+
4
+
#include "smu72.h"
5
+
6
+
#if !defined(SMC_MICROCODE)
7
+
#pragma pack(push, 1)
8
+
#endif
9
+
10
+
struct SMIO_Pattern {
11
+
uint16_t Voltage;
12
+
uint8_t Smio;
13
+
uint8_t padding;
14
+
};
15
+
16
+
typedef struct SMIO_Pattern SMIO_Pattern;
17
+
18
+
struct SMIO_Table {
19
+
SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
20
+
};
21
+
22
+
typedef struct SMIO_Table SMIO_Table;
23
+
24
+
struct SMU72_Discrete_GraphicsLevel {
25
+
SMU_VoltageLevel MinVoltage;
26
+
27
+
uint32_t SclkFrequency;
28
+
29
+
uint8_t pcieDpmLevel;
30
+
uint8_t DeepSleepDivId;
31
+
uint16_t ActivityLevel;
32
+
33
+
uint32_t CgSpllFuncCntl3;
34
+
uint32_t CgSpllFuncCntl4;
35
+
uint32_t SpllSpreadSpectrum;
36
+
uint32_t SpllSpreadSpectrum2;
37
+
uint32_t CcPwrDynRm;
38
+
uint32_t CcPwrDynRm1;
39
+
uint8_t SclkDid;
40
+
uint8_t DisplayWatermark;
41
+
uint8_t EnabledForActivity;
42
+
uint8_t EnabledForThrottle;
43
+
uint8_t UpHyst;
44
+
uint8_t DownHyst;
45
+
uint8_t VoltageDownHyst;
46
+
uint8_t PowerThrottle;
47
+
};
48
+
49
+
typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
50
+
51
+
struct SMU72_Discrete_ACPILevel {
52
+
uint32_t Flags;
53
+
SMU_VoltageLevel MinVoltage;
54
+
uint32_t SclkFrequency;
55
+
uint8_t SclkDid;
56
+
uint8_t DisplayWatermark;
57
+
uint8_t DeepSleepDivId;
58
+
uint8_t padding;
59
+
uint32_t CgSpllFuncCntl;
60
+
uint32_t CgSpllFuncCntl2;
61
+
uint32_t CgSpllFuncCntl3;
62
+
uint32_t CgSpllFuncCntl4;
63
+
uint32_t SpllSpreadSpectrum;
64
+
uint32_t SpllSpreadSpectrum2;
65
+
uint32_t CcPwrDynRm;
66
+
uint32_t CcPwrDynRm1;
67
+
};
68
+
69
+
typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
70
+
71
+
struct SMU72_Discrete_Ulv {
72
+
uint32_t CcPwrDynRm;
73
+
uint32_t CcPwrDynRm1;
74
+
uint16_t VddcOffset;
75
+
uint8_t VddcOffsetVid;
76
+
uint8_t VddcPhase;
77
+
uint32_t Reserved;
78
+
};
79
+
80
+
typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
81
+
82
+
struct SMU72_Discrete_MemoryLevel {
83
+
SMU_VoltageLevel MinVoltage;
84
+
uint32_t MinMvdd;
85
+
86
+
uint32_t MclkFrequency;
87
+
88
+
uint8_t EdcReadEnable;
89
+
uint8_t EdcWriteEnable;
90
+
uint8_t RttEnable;
91
+
uint8_t StutterEnable;
92
+
93
+
uint8_t StrobeEnable;
94
+
uint8_t StrobeRatio;
95
+
uint8_t EnabledForThrottle;
96
+
uint8_t EnabledForActivity;
97
+
98
+
uint8_t UpHyst;
99
+
uint8_t DownHyst;
100
+
uint8_t VoltageDownHyst;
101
+
uint8_t padding;
102
+
103
+
uint16_t ActivityLevel;
104
+
uint8_t DisplayWatermark;
105
+
uint8_t padding1;
106
+
107
+
uint32_t MpllFuncCntl;
108
+
uint32_t MpllFuncCntl_1;
109
+
uint32_t MpllFuncCntl_2;
110
+
uint32_t MpllAdFuncCntl;
111
+
uint32_t MpllDqFuncCntl;
112
+
uint32_t MclkPwrmgtCntl;
113
+
uint32_t DllCntl;
114
+
uint32_t MpllSs1;
115
+
uint32_t MpllSs2;
116
+
};
117
+
118
+
typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
119
+
120
+
struct SMU72_Discrete_LinkLevel {
121
+
uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
122
+
uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
123
+
uint8_t EnabledForActivity;
124
+
uint8_t SPC;
125
+
uint32_t DownThreshold;
126
+
uint32_t UpThreshold;
127
+
uint32_t Reserved;
128
+
};
129
+
130
+
typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
131
+
132
+
/* MC ARB DRAM Timing registers. */
133
+
struct SMU72_Discrete_MCArbDramTimingTableEntry {
134
+
uint32_t McArbDramTiming;
135
+
uint32_t McArbDramTiming2;
136
+
uint8_t McArbBurstTime;
137
+
uint8_t padding[3];
138
+
};
139
+
140
+
typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
141
+
142
+
struct SMU72_Discrete_MCArbDramTimingTable {
143
+
SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
144
+
};
145
+
146
+
typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
147
+
148
+
/* UVD VCLK/DCLK state (level) definition. */
149
+
struct SMU72_Discrete_UvdLevel {
150
+
uint32_t VclkFrequency;
151
+
uint32_t DclkFrequency;
152
+
SMU_VoltageLevel MinVoltage;
153
+
uint8_t VclkDivider;
154
+
uint8_t DclkDivider;
155
+
uint8_t padding[2];
156
+
};
157
+
158
+
typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
159
+
160
+
/* Clocks for other external blocks (VCE, ACP, SAMU). */
161
+
struct SMU72_Discrete_ExtClkLevel {
162
+
uint32_t Frequency;
163
+
SMU_VoltageLevel MinVoltage;
164
+
uint8_t Divider;
165
+
uint8_t padding[3];
166
+
};
167
+
168
+
typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
169
+
170
+
struct SMU72_Discrete_StateInfo {
171
+
uint32_t SclkFrequency;
172
+
uint32_t MclkFrequency;
173
+
uint32_t VclkFrequency;
174
+
uint32_t DclkFrequency;
175
+
uint32_t SamclkFrequency;
176
+
uint32_t AclkFrequency;
177
+
uint32_t EclkFrequency;
178
+
uint16_t MvddVoltage;
179
+
uint16_t padding16;
180
+
uint8_t DisplayWatermark;
181
+
uint8_t McArbIndex;
182
+
uint8_t McRegIndex;
183
+
uint8_t SeqIndex;
184
+
uint8_t SclkDid;
185
+
int8_t SclkIndex;
186
+
int8_t MclkIndex;
187
+
uint8_t PCIeGen;
188
+
189
+
};
190
+
191
+
typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
192
+
193
+
struct SMU72_Discrete_DpmTable {
194
+
/* Multi-DPM controller settings */
195
+
SMU72_PIDController GraphicsPIDController;
196
+
SMU72_PIDController MemoryPIDController;
197
+
SMU72_PIDController LinkPIDController;
198
+
199
+
uint32_t SystemFlags;
200
+
201
+
/* SMIO masks for voltage and phase controls */
202
+
uint32_t VRConfig;
203
+
uint32_t SmioMask1;
204
+
uint32_t SmioMask2;
205
+
SMIO_Table SmioTable1;
206
+
SMIO_Table SmioTable2;
207
+
208
+
uint32_t VddcLevelCount;
209
+
uint32_t VddciLevelCount;
210
+
uint32_t VddGfxLevelCount;
211
+
uint32_t MvddLevelCount;
212
+
213
+
uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC];
214
+
uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
215
+
uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI];
216
+
217
+
uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
218
+
uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
219
+
uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
220
+
221
+
uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
222
+
uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
223
+
uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
224
+
225
+
uint8_t GraphicsDpmLevelCount;
226
+
uint8_t MemoryDpmLevelCount;
227
+
uint8_t LinkLevelCount;
228
+
uint8_t MasterDeepSleepControl;
229
+
230
+
uint8_t UvdLevelCount;
231
+
uint8_t VceLevelCount;
232
+
uint8_t AcpLevelCount;
233
+
uint8_t SamuLevelCount;
234
+
235
+
uint8_t ThermOutGpio;
236
+
uint8_t ThermOutPolarity;
237
+
uint8_t ThermOutMode;
238
+
uint8_t DPMFreezeAndForced;
239
+
uint32_t Reserved[4];
240
+
241
+
/* State table entries for each DPM state */
242
+
SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
243
+
SMU72_Discrete_MemoryLevel MemoryACPILevel;
244
+
SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
245
+
SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK];
246
+
SMU72_Discrete_ACPILevel ACPILevel;
247
+
SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD];
248
+
SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE];
249
+
SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP];
250
+
SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU];
251
+
SMU72_Discrete_Ulv Ulv;
252
+
253
+
uint32_t SclkStepSize;
254
+
uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];
255
+
256
+
uint8_t UvdBootLevel;
257
+
uint8_t VceBootLevel;
258
+
uint8_t AcpBootLevel;
259
+
uint8_t SamuBootLevel;
260
+
261
+
uint8_t GraphicsBootLevel;
262
+
uint8_t GraphicsVoltageChangeEnable;
263
+
uint8_t GraphicsThermThrottleEnable;
264
+
uint8_t GraphicsInterval;
265
+
266
+
uint8_t VoltageInterval;
267
+
uint8_t ThermalInterval;
268
+
uint16_t TemperatureLimitHigh;
269
+
270
+
uint16_t TemperatureLimitLow;
271
+
uint8_t MemoryBootLevel;
272
+
uint8_t MemoryVoltageChangeEnable;
273
+
274
+
uint16_t BootMVdd;
275
+
uint8_t MemoryInterval;
276
+
uint8_t MemoryThermThrottleEnable;
277
+
278
+
uint16_t VoltageResponseTime;
279
+
uint16_t PhaseResponseTime;
280
+
281
+
uint8_t PCIeBootLinkLevel;
282
+
uint8_t PCIeGenInterval;
283
+
uint8_t DTEInterval;
284
+
uint8_t DTEMode;
285
+
286
+
uint8_t SVI2Enable;
287
+
uint8_t VRHotGpio;
288
+
uint8_t AcDcGpio;
289
+
uint8_t ThermGpio;
290
+
291
+
uint16_t PPM_PkgPwrLimit;
292
+
uint16_t PPM_TemperatureLimit;
293
+
294
+
uint16_t DefaultTdp;
295
+
uint16_t TargetTdp;
296
+
297
+
uint16_t FpsHighThreshold;
298
+
uint16_t FpsLowThreshold;
299
+
300
+
uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
301
+
uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
302
+
303
+
uint8_t DTEAmbientTempBase;
304
+
uint8_t DTETjOffset;
305
+
uint8_t GpuTjMax;
306
+
uint8_t GpuTjHyst;
307
+
308
+
SMU_VoltageLevel BootVoltage;
309
+
310
+
uint32_t BAPM_TEMP_GRADIENT;
311
+
312
+
uint32_t LowSclkInterruptThreshold;
313
+
uint32_t VddGfxReChkWait;
314
+
315
+
uint8_t ClockStretcherAmount;
316
+
317
+
uint8_t Sclk_CKS_masterEn0_7;
318
+
uint8_t Sclk_CKS_masterEn8_15;
319
+
uint8_t padding[1];
320
+
321
+
uint8_t Sclk_voltageOffset[8];
322
+
323
+
SMU_ClockStretcherDataTable ClockStretcherDataTable;
324
+
SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
325
+
};
326
+
327
+
typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
328
+
329
+
/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
330
+
#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
331
+
#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
332
+
333
+
struct SMU72_Discrete_MCRegisterAddress {
334
+
uint16_t s0;
335
+
uint16_t s1;
336
+
};
337
+
338
+
typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
339
+
340
+
struct SMU72_Discrete_MCRegisterSet {
341
+
uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
342
+
};
343
+
344
+
typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
345
+
346
+
struct SMU72_Discrete_MCRegisters {
347
+
uint8_t last;
348
+
uint8_t reserved[3];
349
+
SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
350
+
SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
351
+
};
352
+
353
+
typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
354
+
355
+
356
+
/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
357
+
358
+
struct SMU72_Discrete_FanTable {
359
+
uint16_t FdoMode;
360
+
int16_t TempMin;
361
+
int16_t TempMed;
362
+
int16_t TempMax;
363
+
int16_t Slope1;
364
+
int16_t Slope2;
365
+
int16_t FdoMin;
366
+
int16_t HystUp;
367
+
int16_t HystDown;
368
+
int16_t HystSlope;
369
+
int16_t TempRespLim;
370
+
int16_t TempCurr;
371
+
int16_t SlopeCurr;
372
+
int16_t PwmCurr;
373
+
uint32_t RefreshPeriod;
374
+
int16_t FdoMax;
375
+
uint8_t TempSrc;
376
+
int8_t FanControl_GL_Flag;
377
+
};
378
+
379
+
typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
380
+
381
+
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
382
+
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
383
+
384
+
struct SMU7_MclkDpmScoreboard {
385
+
386
+
uint32_t PercentageBusy;
387
+
388
+
int32_t PIDError;
389
+
int32_t PIDIntegral;
390
+
int32_t PIDOutput;
391
+
392
+
uint32_t SigmaDeltaAccum;
393
+
uint32_t SigmaDeltaOutput;
394
+
uint32_t SigmaDeltaLevel;
395
+
396
+
uint32_t UtilizationSetpoint;
397
+
398
+
uint8_t TdpClampMode;
399
+
uint8_t TdcClampMode;
400
+
uint8_t ThermClampMode;
401
+
uint8_t VoltageBusy;
402
+
403
+
int8_t CurrLevel;
404
+
int8_t TargLevel;
405
+
uint8_t LevelChangeInProgress;
406
+
uint8_t UpHyst;
407
+
408
+
uint8_t DownHyst;
409
+
uint8_t VoltageDownHyst;
410
+
uint8_t DpmEnable;
411
+
uint8_t DpmRunning;
412
+
413
+
uint8_t DpmForce;
414
+
uint8_t DpmForceLevel;
415
+
uint8_t DisplayWatermark;
416
+
uint8_t McArbIndex;
417
+
418
+
uint32_t MinimumPerfMclk;
419
+
420
+
uint8_t AcpiReq;
421
+
uint8_t AcpiAck;
422
+
uint8_t MclkSwitchInProgress;
423
+
uint8_t MclkSwitchCritical;
424
+
425
+
uint8_t IgnoreVBlank;
426
+
uint8_t TargetMclkIndex;
427
+
uint8_t TargetMvddIndex;
428
+
uint8_t MclkSwitchResult;
429
+
430
+
uint16_t VbiFailureCount;
431
+
uint8_t VbiWaitCounter;
432
+
uint8_t EnabledLevelsChange;
433
+
434
+
uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
435
+
uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
436
+
437
+
void (*TargetStateCalculator)(uint8_t);
438
+
void (*SavedTargetStateCalculator)(uint8_t);
439
+
440
+
uint16_t AutoDpmInterval;
441
+
uint16_t AutoDpmRange;
442
+
443
+
uint16_t VbiTimeoutCount;
444
+
uint16_t MclkSwitchingTime;
445
+
446
+
uint8_t fastSwitch;
447
+
uint8_t Save_PIC_VDDGFX_EXIT;
448
+
uint8_t Save_PIC_VDDGFX_ENTER;
449
+
uint8_t padding;
450
+
451
+
};
452
+
453
+
typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
454
+
455
+
struct SMU7_UlvScoreboard {
456
+
uint8_t EnterUlv;
457
+
uint8_t ExitUlv;
458
+
uint8_t UlvActive;
459
+
uint8_t WaitingForUlv;
460
+
uint8_t UlvEnable;
461
+
uint8_t UlvRunning;
462
+
uint8_t UlvMasterEnable;
463
+
uint8_t padding;
464
+
uint32_t UlvAbortedCount;
465
+
uint32_t UlvTimeStamp;
466
+
};
467
+
468
+
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
469
+
470
+
struct VddgfxSavedRegisters {
471
+
uint32_t GPU_DBG[3];
472
+
uint32_t MEC_BaseAddress_Hi;
473
+
uint32_t MEC_BaseAddress_Lo;
474
+
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
475
+
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
476
+
uint32_t CP_INT_CNTL;
477
+
};
478
+
479
+
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
480
+
481
+
struct SMU7_VddGfxScoreboard {
482
+
uint8_t VddGfxEnable;
483
+
uint8_t VddGfxActive;
484
+
uint8_t VPUResetOccured;
485
+
uint8_t padding;
486
+
487
+
uint32_t VddGfxEnteredCount;
488
+
uint32_t VddGfxAbortedCount;
489
+
490
+
uint32_t VddGfxVid;
491
+
492
+
VddgfxSavedRegisters SavedRegisters;
493
+
};
494
+
495
+
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
496
+
497
+
struct SMU7_TdcLimitScoreboard {
498
+
uint8_t Enable;
499
+
uint8_t Running;
500
+
uint16_t Alpha;
501
+
uint32_t FilteredIddc;
502
+
uint32_t IddcLimit;
503
+
uint32_t IddcHyst;
504
+
SMU7_HystController_Data HystControllerData;
505
+
};
506
+
507
+
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
508
+
509
+
struct SMU7_PkgPwrLimitScoreboard {
510
+
uint8_t Enable;
511
+
uint8_t Running;
512
+
uint16_t Alpha;
513
+
uint32_t FilteredPkgPwr;
514
+
uint32_t Limit;
515
+
uint32_t Hyst;
516
+
uint32_t LimitFromDriver;
517
+
SMU7_HystController_Data HystControllerData;
518
+
};
519
+
520
+
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
521
+
522
+
struct SMU7_BapmScoreboard {
523
+
uint32_t source_powers[SMU72_DTE_SOURCES];
524
+
uint32_t source_powers_last[SMU72_DTE_SOURCES];
525
+
int32_t entity_temperatures[SMU72_NUM_GPU_TES];
526
+
int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
527
+
int32_t Limit;
528
+
int32_t Hyst;
529
+
int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
530
+
int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
531
+
uint16_t ConfigTDPPowerScalar;
532
+
uint16_t FanSpeedPowerScalar;
533
+
uint16_t OverDrivePowerScalar;
534
+
uint16_t OverDriveLimitScalar;
535
+
uint16_t FinalPowerScalar;
536
+
uint8_t VariantID;
537
+
uint8_t spare997;
538
+
539
+
SMU7_HystController_Data HystControllerData;
540
+
541
+
int32_t temperature_gradient_slope;
542
+
int32_t temperature_gradient;
543
+
uint32_t measured_temperature;
544
+
};
545
+
546
+
547
+
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
548
+
549
+
struct SMU7_AcpiScoreboard {
550
+
uint32_t SavedInterruptMask[2];
551
+
uint8_t LastACPIRequest;
552
+
uint8_t CgBifResp;
553
+
uint8_t RequestType;
554
+
uint8_t Padding;
555
+
SMU72_Discrete_ACPILevel D0Level;
556
+
};
557
+
558
+
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
559
+
560
+
struct SMU72_Discrete_PmFuses {
561
+
/* dw1 */
562
+
uint8_t SviLoadLineEn;
563
+
uint8_t SviLoadLineVddC;
564
+
uint8_t SviLoadLineTrimVddC;
565
+
uint8_t SviLoadLineOffsetVddC;
566
+
567
+
/* dw2 */
568
+
uint16_t TDC_VDDC_PkgLimit;
569
+
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
570
+
uint8_t TDC_MAWt;
571
+
572
+
/* dw3 */
573
+
uint8_t TdcWaterfallCtl;
574
+
uint8_t LPMLTemperatureMin;
575
+
uint8_t LPMLTemperatureMax;
576
+
uint8_t Reserved;
577
+
578
+
/* dw4-dw7 */
579
+
uint8_t LPMLTemperatureScaler[16];
580
+
581
+
/* dw8-dw9 */
582
+
int16_t FuzzyFan_ErrorSetDelta;
583
+
int16_t FuzzyFan_ErrorRateSetDelta;
584
+
int16_t FuzzyFan_PwmSetDelta;
585
+
uint16_t Reserved6;
586
+
587
+
/* dw10-dw14 */
588
+
uint8_t GnbLPML[16];
589
+
590
+
/* dw15 */
591
+
uint8_t GnbLPMLMaxVid;
592
+
uint8_t GnbLPMLMinVid;
593
+
uint8_t Reserved1[2];
594
+
595
+
/* dw16 */
596
+
uint16_t BapmVddCBaseLeakageHiSidd;
597
+
uint16_t BapmVddCBaseLeakageLoSidd;
598
+
};
599
+
600
+
typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
601
+
602
+
struct SMU7_Discrete_Log_Header_Table {
603
+
uint32_t version;
604
+
uint32_t asic_id;
605
+
uint16_t flags;
606
+
uint16_t entry_size;
607
+
uint32_t total_size;
608
+
uint32_t num_of_entries;
609
+
uint8_t type;
610
+
uint8_t mode;
611
+
uint8_t filler_0[2];
612
+
uint32_t filler_1[2];
613
+
};
614
+
615
+
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
616
+
617
+
struct SMU7_Discrete_Log_Cntl {
618
+
uint8_t Enabled;
619
+
uint8_t Type;
620
+
uint8_t padding[2];
621
+
uint32_t BufferSize;
622
+
uint32_t SamplesLogged;
623
+
uint32_t SampleSize;
624
+
uint32_t AddrL;
625
+
uint32_t AddrH;
626
+
};
627
+
628
+
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
629
+
630
+
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
631
+
632
+
struct SMU7_Discrete_Cac_Collection_Table {
633
+
uint32_t temperature;
634
+
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
635
+
};
636
+
637
+
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
638
+
639
+
struct SMU7_Discrete_Cac_Verification_Table {
640
+
uint32_t VddcTotalPower;
641
+
uint32_t VddcLeakagePower;
642
+
uint32_t VddcConstantPower;
643
+
uint32_t VddcGfxDynamicPower;
644
+
uint32_t VddcUvdDynamicPower;
645
+
uint32_t VddcVceDynamicPower;
646
+
uint32_t VddcAcpDynamicPower;
647
+
uint32_t VddcPcieDynamicPower;
648
+
uint32_t VddcDceDynamicPower;
649
+
uint32_t VddcCurrent;
650
+
uint32_t VddcVoltage;
651
+
uint32_t VddciTotalPower;
652
+
uint32_t VddciLeakagePower;
653
+
uint32_t VddciConstantPower;
654
+
uint32_t VddciDynamicPower;
655
+
uint32_t Vddr1TotalPower;
656
+
uint32_t Vddr1LeakagePower;
657
+
uint32_t Vddr1ConstantPower;
658
+
uint32_t Vddr1DynamicPower;
659
+
uint32_t spare[4];
660
+
uint32_t temperature;
661
+
};
662
+
663
+
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
664
+
665
+
struct SMU7_Discrete_Pm_Status_Table {
666
+
/* Thermal entities */
667
+
int32_t T_meas_max;
668
+
int32_t T_meas_acc;
669
+
int32_t T_calc_max;
670
+
int32_t T_calc_acc;
671
+
uint32_t P_scalar_acc;
672
+
uint32_t P_calc_max;
673
+
uint32_t P_calc_acc;
674
+
675
+
/*Voltage domains */
676
+
uint32_t I_calc_max;
677
+
uint32_t I_calc_acc;
678
+
uint32_t I_calc_acc_vddci;
679
+
uint32_t V_calc_noload_acc;
680
+
uint32_t V_calc_load_acc;
681
+
uint32_t V_calc_noload_acc_vddci;
682
+
uint32_t P_meas_acc;
683
+
uint32_t V_meas_noload_acc;
684
+
uint32_t V_meas_load_acc;
685
+
uint32_t I_meas_acc;
686
+
uint32_t P_meas_acc_vddci;
687
+
uint32_t V_meas_noload_acc_vddci;
688
+
uint32_t V_meas_load_acc_vddci;
689
+
uint32_t I_meas_acc_vddci;
690
+
691
+
/*Frequency */
692
+
uint16_t Sclk_dpm_residency[8];
693
+
uint16_t Uvd_dpm_residency[8];
694
+
uint16_t Vce_dpm_residency[8];
695
+
uint16_t Mclk_dpm_residency[4];
696
+
697
+
/*Chip */
698
+
uint32_t P_vddci_acc;
699
+
uint32_t P_vddr1_acc;
700
+
uint32_t P_nte1_acc;
701
+
uint32_t PkgPwr_max;
702
+
uint32_t PkgPwr_acc;
703
+
uint32_t MclkSwitchingTime_max;
704
+
uint32_t MclkSwitchingTime_acc;
705
+
uint32_t FanPwm_acc;
706
+
uint32_t FanRpm_acc;
707
+
708
+
uint32_t AccCnt;
709
+
};
710
+
711
+
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
712
+
713
+
/*FIXME THESE NEED TO BE UPDATED */
714
+
#define SMU7_SCLK_CAC 0x561
715
+
#define SMU7_MCLK_CAC 0xF9
716
+
#define SMU7_VCLK_CAC 0x2DE
717
+
#define SMU7_DCLK_CAC 0x2DE
718
+
#define SMU7_ECLK_CAC 0x25E
719
+
#define SMU7_ACLK_CAC 0x25E
720
+
#define SMU7_SAMCLK_CAC 0x25E
721
+
#define SMU7_DISPCLK_CAC 0x100
722
+
#define SMU7_CAC_CONSTANT 0x2EE3430
723
+
#define SMU7_CAC_CONSTANT_SHIFT 18
724
+
725
+
#define SMU7_VDDCI_MCLK_CONST 1765
726
+
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
727
+
#define SMU7_VDDCI_VDDCI_CONST 50958
728
+
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
729
+
#define SMU7_VDDCI_CONST 11781
730
+
731
+
#define SMU7_12C_VDDCI_MCLK_CONST 1623
732
+
#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15
733
+
#define SMU7_12C_VDDCI_VDDCI_CONST 40088
734
+
#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
735
+
#define SMU7_12C_VDDCI_CONST 20856
736
+
737
+
#define SMU7_VDDCI_STROBE_PWR 1331
738
+
739
+
#define SMU7_VDDR1_CONST 693
740
+
#define SMU7_VDDR1_CAC_WEIGHT 20
741
+
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
742
+
#define SMU7_VDDR1_STROBE_PWR 512
743
+
744
+
#define SMU7_AREA_COEFF_UVD 0xA78
745
+
#define SMU7_AREA_COEFF_VCE 0x190A
746
+
#define SMU7_AREA_COEFF_ACP 0x22D1
747
+
#define SMU7_AREA_COEFF_SAMU 0x534
748
+
749
+
/*ThermOutMode values */
750
+
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
751
+
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
752
+
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
753
+
754
+
#if !defined(SMC_MICROCODE)
755
+
#pragma pack(pop)
756
+
#endif
757
+
758
+
759
+
#endif
760
+
+420
drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h
+420
drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h
···
1
+
/*
2
+
* Copyright 2015 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef TONGA_PP_SMC_H
25
+
#define TONGA_PP_SMC_H
26
+
27
+
#pragma pack(push, 1)
28
+
29
+
#define PPSMC_SWSTATE_FLAG_DC 0x01
30
+
#define PPSMC_SWSTATE_FLAG_UVD 0x02
31
+
#define PPSMC_SWSTATE_FLAG_VCE 0x04
32
+
#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33
+
34
+
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35
+
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36
+
#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37
+
38
+
#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39
+
#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40
+
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
41
+
42
+
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
43
+
44
+
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
45
+
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
46
+
#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40
47
+
48
+
49
+
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
50
+
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
51
+
52
+
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
53
+
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
54
+
55
+
#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10
56
+
#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20
57
+
#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40
58
+
59
+
/* Defines for DPM 2.0 */
60
+
#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
61
+
#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
62
+
#define PPSMC_DPM2FLAGS_OCP 0x04
63
+
64
+
/* Defines for display watermark level */
65
+
66
+
#define PPSMC_DISPLAY_WATERMARK_LOW 0
67
+
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
68
+
69
+
/* In the HW performance level's state flags:*/
70
+
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
71
+
#define PPSMC_STATEFLAG_POWERBOOST 0x02
72
+
#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
73
+
#define PPSMC_STATEFLAG_POWERSHIFT 0x08
74
+
#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
75
+
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
76
+
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
77
+
78
+
/* Fan control algorithm:*/
79
+
#define FDO_MODE_HARDWARE 0
80
+
#define FDO_MODE_PIECE_WISE_LINEAR 1
81
+
82
+
enum FAN_CONTROL {
83
+
FAN_CONTROL_FUZZY,
84
+
FAN_CONTROL_TABLE
85
+
};
86
+
87
+
/* Return codes for driver to SMC communication.*/
88
+
89
+
#define PPSMC_Result_OK ((uint16_t)0x01)
90
+
#define PPSMC_Result_NoMore ((uint16_t)0x02)
91
+
#define PPSMC_Result_NotNow ((uint16_t)0x03)
92
+
93
+
#define PPSMC_Result_Failed ((uint16_t)0xFF)
94
+
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
95
+
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
96
+
97
+
typedef uint16_t PPSMC_Result;
98
+
99
+
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
100
+
101
+
102
+
#define PPSMC_MSG_Halt ((uint16_t)0x10)
103
+
#define PPSMC_MSG_Resume ((uint16_t)0x11)
104
+
#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
105
+
#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
106
+
#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
107
+
#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
108
+
#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
109
+
#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
110
+
#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
111
+
#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
112
+
#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
113
+
#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
114
+
115
+
#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
116
+
#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
117
+
#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
118
+
#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
119
+
#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
120
+
121
+
#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
122
+
#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
123
+
#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
124
+
#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
125
+
#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
126
+
#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
127
+
#define PPSMC_CACHistoryStart ((uint16_t)0x57)
128
+
#define PPSMC_CACHistoryStop ((uint16_t)0x58)
129
+
#define PPSMC_TDPClampingActive ((uint16_t)0x59)
130
+
#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
131
+
#define PPSMC_StartFanControl ((uint16_t)0x5B)
132
+
#define PPSMC_StopFanControl ((uint16_t)0x5C)
133
+
#define PPSMC_NoDisplay ((uint16_t)0x5D)
134
+
#define PPSMC_HasDisplay ((uint16_t)0x5E)
135
+
#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
136
+
#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
137
+
#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
138
+
#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
139
+
#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
140
+
#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
141
+
#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
142
+
#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
143
+
#define PPSMC_OCPActive ((uint16_t)0x6C)
144
+
#define PPSMC_OCPInactive ((uint16_t)0x6D)
145
+
#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
146
+
#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
147
+
#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
148
+
#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
149
+
#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
150
+
#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
151
+
#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
152
+
#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
153
+
#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
154
+
#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
155
+
#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
156
+
#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
157
+
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
158
+
#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
159
+
#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
160
+
#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
161
+
162
+
#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
163
+
#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
164
+
#define PPSMC_FlushDataCache ((uint16_t)0x80)
165
+
#define PPSMC_FlushInstrCache ((uint16_t)0x81)
166
+
167
+
#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
168
+
#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
169
+
170
+
#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
171
+
172
+
#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
173
+
#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
174
+
#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
175
+
#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
176
+
177
+
#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
178
+
#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90)
179
+
#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91)
180
+
181
+
#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92)
182
+
#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93)
183
+
184
+
#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94)
185
+
#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95)
186
+
#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96)
187
+
#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97)
188
+
#define PPSMC_MSG_GPIO17 ((uint16_t)0x98)
189
+
190
+
#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99)
191
+
#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A)
192
+
#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B)
193
+
#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C)
194
+
#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D)
195
+
#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E)
196
+
197
+
#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
198
+
199
+
/* Trinity Specific Messages*/
200
+
#define PPSMC_MSG_Test ((uint16_t) 0x100)
201
+
#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
202
+
#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
203
+
#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
204
+
#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
205
+
#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
206
+
#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
207
+
#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
208
+
#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
209
+
#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
210
+
#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
211
+
#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
212
+
#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
213
+
#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
214
+
#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
215
+
#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
216
+
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
217
+
#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
218
+
#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
219
+
#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
220
+
#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
221
+
#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
222
+
#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
223
+
#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
224
+
#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
225
+
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
226
+
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
227
+
#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
228
+
#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
229
+
#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
230
+
#define PPSMC_MSG_PCIE_PHYPowerDown ((uint16_t) 0x122)
231
+
#define PPSMC_MSG_PCIE_PHYPowerUp ((uint16_t) 0x123)
232
+
#define PPSMC_MSG_UVD_DPM_Config ((uint16_t) 0x124)
233
+
#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
234
+
#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
235
+
#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
236
+
#define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125)
237
+
#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint16_t) 0x126)
238
+
#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint16_t) 0x127)
239
+
#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
240
+
241
+
#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
242
+
#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
243
+
#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
244
+
#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
245
+
#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
246
+
#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
247
+
#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
248
+
#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
249
+
#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
250
+
#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
251
+
#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
252
+
#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
253
+
#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
254
+
#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
255
+
#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
256
+
#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
257
+
#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
258
+
#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
259
+
#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
260
+
#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
261
+
#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
262
+
#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
263
+
#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
264
+
#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
265
+
#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
266
+
#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
267
+
#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
268
+
#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
269
+
#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
270
+
#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
271
+
#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
272
+
#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
273
+
#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
274
+
#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
275
+
#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
276
+
277
+
#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
278
+
#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
279
+
280
+
#define PPSMC_MSG_DPM_Enable ((uint16_t)0x14e)
281
+
#define PPSMC_MSG_DPM_Disable ((uint16_t)0x14f)
282
+
#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t)0x150)
283
+
#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t)0x151)
284
+
#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t)0x152)
285
+
#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t)0x153)
286
+
#define PPSMC_MSG_UVDDPM_Enable ((uint16_t)0x154)
287
+
#define PPSMC_MSG_UVDDPM_Disable ((uint16_t)0x155)
288
+
#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t)0x156)
289
+
#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t)0x157)
290
+
#define PPSMC_MSG_ACPDPM_Enable ((uint16_t)0x158)
291
+
#define PPSMC_MSG_ACPDPM_Disable ((uint16_t)0x159)
292
+
#define PPSMC_MSG_VCEDPM_Enable ((uint16_t)0x15a)
293
+
#define PPSMC_MSG_VCEDPM_Disable ((uint16_t)0x15b)
294
+
#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t)0x15c)
295
+
296
+
#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
297
+
#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
298
+
#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
299
+
#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
300
+
#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
301
+
#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
302
+
#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
303
+
#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
304
+
#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
305
+
#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
306
+
#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
307
+
#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
308
+
#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
309
+
#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
310
+
#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
311
+
#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t)0x16c)
312
+
#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t)0x16d)
313
+
#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t)0x16e)
314
+
#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t)0x16f)
315
+
#define PPSMC_MSG_PmStatusLogStart ((uint16_t)0x170)
316
+
#define PPSMC_MSG_PmStatusLogSample ((uint16_t)0x171)
317
+
#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
318
+
#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
319
+
#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
320
+
#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
321
+
#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
322
+
#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
323
+
#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
324
+
#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
325
+
#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
326
+
#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
327
+
#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
328
+
#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
329
+
#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
330
+
#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
331
+
#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
332
+
#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
333
+
#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
334
+
#define PPSMC_MSG_UVD_HANDSHAKE_OFF ((uint16_t) 0x183)
335
+
#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
336
+
#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
337
+
#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
338
+
#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
339
+
#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
340
+
#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
341
+
#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
342
+
#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
343
+
#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
344
+
#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
345
+
#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
346
+
#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
347
+
#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
348
+
#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
349
+
#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
350
+
#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
351
+
#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
352
+
#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
353
+
#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
354
+
#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
355
+
#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
356
+
#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
357
+
#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
358
+
#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
359
+
#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
360
+
361
+
#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
362
+
#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
363
+
#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
364
+
#define PPSMC_MSG_Enable_PCC ((uint16_t) 0x19E)
365
+
#define PPSMC_MSG_Disable_PCC ((uint16_t) 0x19F)
366
+
367
+
#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
368
+
#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
369
+
#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
370
+
#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
371
+
#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
372
+
#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
373
+
#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
374
+
#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
375
+
#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
376
+
377
+
#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
378
+
#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
379
+
#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
380
+
#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
381
+
#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
382
+
#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
383
+
#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
384
+
385
+
#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
386
+
#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
387
+
#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
388
+
#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
389
+
#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
390
+
#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
391
+
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
392
+
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
393
+
#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
394
+
#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
395
+
#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
396
+
#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
397
+
#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
398
+
#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
399
+
#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
400
+
#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
401
+
#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
402
+
#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
403
+
#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
404
+
#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
405
+
#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
406
+
#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
407
+
#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
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+
#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
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+
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+
typedef uint16_t PPSMC_Msg;
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+
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+
/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
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+
#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
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+
#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
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+
#define PPSMC_EVENT_STATUS_DC 0x00000004
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+
#define PPSMC_EVENT_STATUS_GPIO17 0x00000008
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+
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+
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+
#pragma pack(pop)
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+
#endif