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KVM: PPC: booke(hv): Fix save/restore of guest accessible SPRGs.

For Guest accessible SPRGs 4-7, save/restore must be handled differently for 64bit and
non-64 bit case. Use the PPC_STD/PPC_LD macros for saving/restoring to/from these registers.

Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

authored by

Varun Sethi and committed by
Alexander Graf 30124906 3d4c6826

+12 -12
+4 -4
arch/powerpc/kvm/booke_interrupts.S
··· 419 419 * written directly to the shared area, so we 420 420 * need to reload them here with the guest's values. 421 421 */ 422 - lwz r3, VCPU_SHARED_SPRG4(r5) 422 + PPC_LD(r3, VCPU_SHARED_SPRG4, r5) 423 423 mtspr SPRN_SPRG4W, r3 424 - lwz r3, VCPU_SHARED_SPRG5(r5) 424 + PPC_LD(r3, VCPU_SHARED_SPRG5, r5) 425 425 mtspr SPRN_SPRG5W, r3 426 - lwz r3, VCPU_SHARED_SPRG6(r5) 426 + PPC_LD(r3, VCPU_SHARED_SPRG6, r5) 427 427 mtspr SPRN_SPRG6W, r3 428 - lwz r3, VCPU_SHARED_SPRG7(r5) 428 + PPC_LD(r3, VCPU_SHARED_SPRG7, r5) 429 429 mtspr SPRN_SPRG7W, r3 430 430 431 431 #ifdef CONFIG_KVM_EXIT_TIMING
+8 -8
arch/powerpc/kvm/bookehv_interrupts.S
··· 316 316 PPC_STL r5, VCPU_LR(r4) 317 317 mfspr r7, SPRN_SPRG5 318 318 PPC_STL r3, VCPU_VRSAVE(r4) 319 - PPC_STL r6, VCPU_SHARED_SPRG4(r11) 319 + PPC_STD(r6, VCPU_SHARED_SPRG4, r11) 320 320 mfspr r8, SPRN_SPRG6 321 - PPC_STL r7, VCPU_SHARED_SPRG5(r11) 321 + PPC_STD(r7, VCPU_SHARED_SPRG5, r11) 322 322 mfspr r9, SPRN_SPRG7 323 - PPC_STL r8, VCPU_SHARED_SPRG6(r11) 323 + PPC_STD(r8, VCPU_SHARED_SPRG6, r11) 324 324 mfxer r3 325 - PPC_STL r9, VCPU_SHARED_SPRG7(r11) 325 + PPC_STD(r9, VCPU_SHARED_SPRG7, r11) 326 326 327 327 /* save guest MAS registers and restore host mas4 & mas6 */ 328 328 mfspr r5, SPRN_MAS0 ··· 537 537 * SPRGs, so we need to reload them here with the guest's values. 538 538 */ 539 539 lwz r3, VCPU_VRSAVE(r4) 540 - lwz r5, VCPU_SHARED_SPRG4(r11) 540 + PPC_LD(r5, VCPU_SHARED_SPRG4, r11) 541 541 mtspr SPRN_VRSAVE, r3 542 - lwz r6, VCPU_SHARED_SPRG5(r11) 542 + PPC_LD(r6, VCPU_SHARED_SPRG5, r11) 543 543 mtspr SPRN_SPRG4W, r5 544 - lwz r7, VCPU_SHARED_SPRG6(r11) 544 + PPC_LD(r7, VCPU_SHARED_SPRG6, r11) 545 545 mtspr SPRN_SPRG5W, r6 546 - lwz r8, VCPU_SHARED_SPRG7(r11) 546 + PPC_LD(r8, VCPU_SHARED_SPRG7, r11) 547 547 mtspr SPRN_SPRG6W, r7 548 548 mtspr SPRN_SPRG7W, r8 549 549