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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: host1x: Deduplicate hardware headers
Host1x class information and opcodes are unchanged or backwards
compatible across SoCs so let's not duplicate them for each one
but have them in a shared header file.
At the same time, add opcode functions for acquire/release_mlock.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Mikko Perttunen
and committed by
Thierry Reding
3000c4ac
bf0297ac
+156
-703
+1
-113
drivers/gpu/host1x/hw/host1x01_hardware.h
+1
-113
drivers/gpu/host1x/hw/host1x01_hardware.h
···
15
15
#include "hw_host1x01_sync.h"
16
16
#include "hw_host1x01_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
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return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
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static inline u32 host1x_class_host_load_syncpt_base(
26
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unsigned indx, unsigned threshold)
27
-
{
28
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return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
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static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
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return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
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| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
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| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
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}
39
-
40
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static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
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return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
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return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
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static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
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u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
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| host1x_uclass_indoff_indmodid_f(mod_id)
59
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| host1x_uclass_indoff_indroffset_f(offset);
60
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if (auto_inc)
61
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v |= host1x_uclass_indoff_autoinc_f(1);
62
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return v;
63
-
}
64
-
65
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static inline u32 host1x_class_host_indoff_reg_read(
66
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unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
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u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
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| host1x_uclass_indoff_rwn_read_v();
71
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if (auto_inc)
72
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v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
77
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/* cdma opcodes */
78
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static inline u32 host1x_opcode_setclass(
79
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unsigned class_id, unsigned offset, unsigned mask)
80
-
{
81
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return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82
-
}
83
-
84
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static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85
-
{
86
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return (1 << 28) | (offset << 16) | count;
87
-
}
88
-
89
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static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90
-
{
91
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return (2 << 28) | (offset << 16) | count;
92
-
}
93
-
94
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static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95
-
{
96
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return (3 << 28) | (offset << 16) | mask;
97
-
}
98
-
99
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static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100
-
{
101
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return (4 << 28) | (offset << 16) | value;
102
-
}
103
-
104
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static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105
-
{
106
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return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107
-
host1x_class_host_incr_syncpt(cond, indx));
108
-
}
109
-
110
-
static inline u32 host1x_opcode_restart(unsigned address)
111
-
{
112
-
return (5 << 28) | (address >> 4);
113
-
}
114
-
115
-
static inline u32 host1x_opcode_gather(unsigned count)
116
-
{
117
-
return (6 << 28) | count;
118
-
}
119
-
120
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121
-
{
122
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
123
-
}
124
-
125
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static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126
-
{
127
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128
-
}
129
-
130
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
131
19
132
20
#endif
+1
-112
drivers/gpu/host1x/hw/host1x02_hardware.h
+1
-112
drivers/gpu/host1x/hw/host1x02_hardware.h
···
15
15
#include "hw_host1x02_sync.h"
16
16
#include "hw_host1x02_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
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| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
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| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
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| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
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| host1x_uclass_indoff_indroffset_f(offset);
60
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if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
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| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
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v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
/* cdma opcodes */
77
-
static inline u32 host1x_opcode_setclass(
78
-
unsigned class_id, unsigned offset, unsigned mask)
79
-
{
80
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
81
-
}
82
-
83
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
84
-
{
85
-
return (1 << 28) | (offset << 16) | count;
86
-
}
87
-
88
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
89
-
{
90
-
return (2 << 28) | (offset << 16) | count;
91
-
}
92
-
93
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
94
-
{
95
-
return (3 << 28) | (offset << 16) | mask;
96
-
}
97
-
98
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
99
-
{
100
-
return (4 << 28) | (offset << 16) | value;
101
-
}
102
-
103
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
104
-
{
105
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106
-
host1x_class_host_incr_syncpt(cond, indx));
107
-
}
108
-
109
-
static inline u32 host1x_opcode_restart(unsigned address)
110
-
{
111
-
return (5 << 28) | (address >> 4);
112
-
}
113
-
114
-
static inline u32 host1x_opcode_gather(unsigned count)
115
-
{
116
-
return (6 << 28) | count;
117
-
}
118
-
119
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
120
-
{
121
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
122
-
}
123
-
124
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
125
-
{
126
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
127
-
}
128
-
129
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
130
19
131
20
#endif
+1
-112
drivers/gpu/host1x/hw/host1x04_hardware.h
+1
-112
drivers/gpu/host1x/hw/host1x04_hardware.h
···
15
15
#include "hw_host1x04_sync.h"
16
16
#include "hw_host1x04_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
-
| host1x_uclass_indoff_indroffset_f(offset);
60
-
if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
-
| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
-
v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
/* cdma opcodes */
77
-
static inline u32 host1x_opcode_setclass(
78
-
unsigned class_id, unsigned offset, unsigned mask)
79
-
{
80
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
81
-
}
82
-
83
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
84
-
{
85
-
return (1 << 28) | (offset << 16) | count;
86
-
}
87
-
88
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
89
-
{
90
-
return (2 << 28) | (offset << 16) | count;
91
-
}
92
-
93
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
94
-
{
95
-
return (3 << 28) | (offset << 16) | mask;
96
-
}
97
-
98
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
99
-
{
100
-
return (4 << 28) | (offset << 16) | value;
101
-
}
102
-
103
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
104
-
{
105
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106
-
host1x_class_host_incr_syncpt(cond, indx));
107
-
}
108
-
109
-
static inline u32 host1x_opcode_restart(unsigned address)
110
-
{
111
-
return (5 << 28) | (address >> 4);
112
-
}
113
-
114
-
static inline u32 host1x_opcode_gather(unsigned count)
115
-
{
116
-
return (6 << 28) | count;
117
-
}
118
-
119
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
120
-
{
121
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
122
-
}
123
-
124
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
125
-
{
126
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
127
-
}
128
-
129
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
130
19
131
20
#endif
+1
-112
drivers/gpu/host1x/hw/host1x05_hardware.h
+1
-112
drivers/gpu/host1x/hw/host1x05_hardware.h
···
15
15
#include "hw_host1x05_sync.h"
16
16
#include "hw_host1x05_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
-
| host1x_uclass_indoff_indroffset_f(offset);
60
-
if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
-
| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
-
v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
/* cdma opcodes */
77
-
static inline u32 host1x_opcode_setclass(
78
-
unsigned class_id, unsigned offset, unsigned mask)
79
-
{
80
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
81
-
}
82
-
83
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
84
-
{
85
-
return (1 << 28) | (offset << 16) | count;
86
-
}
87
-
88
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
89
-
{
90
-
return (2 << 28) | (offset << 16) | count;
91
-
}
92
-
93
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
94
-
{
95
-
return (3 << 28) | (offset << 16) | mask;
96
-
}
97
-
98
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
99
-
{
100
-
return (4 << 28) | (offset << 16) | value;
101
-
}
102
-
103
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
104
-
{
105
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106
-
host1x_class_host_incr_syncpt(cond, indx));
107
-
}
108
-
109
-
static inline u32 host1x_opcode_restart(unsigned address)
110
-
{
111
-
return (5 << 28) | (address >> 4);
112
-
}
113
-
114
-
static inline u32 host1x_opcode_gather(unsigned count)
115
-
{
116
-
return (6 << 28) | count;
117
-
}
118
-
119
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
120
-
{
121
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
122
-
}
123
-
124
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
125
-
{
126
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
127
-
}
128
-
129
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
130
19
131
20
#endif
+1
-127
drivers/gpu/host1x/hw/host1x06_hardware.h
+1
-127
drivers/gpu/host1x/hw/host1x06_hardware.h
···
16
16
#include "hw_host1x06_vm.h"
17
17
#include "hw_host1x06_hypervisor.h"
18
18
19
-
static inline u32 host1x_class_host_wait_syncpt(
20
-
unsigned indx, unsigned threshold)
21
-
{
22
-
return host1x_uclass_wait_syncpt_indx_f(indx)
23
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
24
-
}
25
-
26
-
static inline u32 host1x_class_host_load_syncpt_base(
27
-
unsigned indx, unsigned threshold)
28
-
{
29
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
30
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
31
-
}
32
-
33
-
static inline u32 host1x_class_host_wait_syncpt_base(
34
-
unsigned indx, unsigned base_indx, unsigned offset)
35
-
{
36
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
37
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
38
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
39
-
}
40
-
41
-
static inline u32 host1x_class_host_incr_syncpt_base(
42
-
unsigned base_indx, unsigned offset)
43
-
{
44
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
45
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
46
-
}
47
-
48
-
static inline u32 host1x_class_host_incr_syncpt(
49
-
unsigned cond, unsigned indx)
50
-
{
51
-
return host1x_uclass_incr_syncpt_cond_f(cond)
52
-
| host1x_uclass_incr_syncpt_indx_f(indx);
53
-
}
54
-
55
-
static inline u32 host1x_class_host_indoff_reg_write(
56
-
unsigned mod_id, unsigned offset, bool auto_inc)
57
-
{
58
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
59
-
| host1x_uclass_indoff_indmodid_f(mod_id)
60
-
| host1x_uclass_indoff_indroffset_f(offset);
61
-
if (auto_inc)
62
-
v |= host1x_uclass_indoff_autoinc_f(1);
63
-
return v;
64
-
}
65
-
66
-
static inline u32 host1x_class_host_indoff_reg_read(
67
-
unsigned mod_id, unsigned offset, bool auto_inc)
68
-
{
69
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
70
-
| host1x_uclass_indoff_indroffset_f(offset)
71
-
| host1x_uclass_indoff_rwn_read_v();
72
-
if (auto_inc)
73
-
v |= host1x_uclass_indoff_autoinc_f(1);
74
-
return v;
75
-
}
76
-
77
-
/* cdma opcodes */
78
-
static inline u32 host1x_opcode_setclass(
79
-
unsigned class_id, unsigned offset, unsigned mask)
80
-
{
81
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82
-
}
83
-
84
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85
-
{
86
-
return (1 << 28) | (offset << 16) | count;
87
-
}
88
-
89
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90
-
{
91
-
return (2 << 28) | (offset << 16) | count;
92
-
}
93
-
94
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95
-
{
96
-
return (3 << 28) | (offset << 16) | mask;
97
-
}
98
-
99
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100
-
{
101
-
return (4 << 28) | (offset << 16) | value;
102
-
}
103
-
104
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105
-
{
106
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107
-
host1x_class_host_incr_syncpt(cond, indx));
108
-
}
109
-
110
-
static inline u32 host1x_opcode_restart(unsigned address)
111
-
{
112
-
return (5 << 28) | (address >> 4);
113
-
}
114
-
115
-
static inline u32 host1x_opcode_gather(unsigned count)
116
-
{
117
-
return (6 << 28) | count;
118
-
}
119
-
120
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121
-
{
122
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
123
-
}
124
-
125
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126
-
{
127
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128
-
}
129
-
130
-
static inline u32 host1x_opcode_setstreamid(unsigned streamid)
131
-
{
132
-
return (7 << 28) | streamid;
133
-
}
134
-
135
-
static inline u32 host1x_opcode_setpayload(unsigned payload)
136
-
{
137
-
return (9 << 28) | payload;
138
-
}
139
-
140
-
static inline u32 host1x_opcode_gather_wide(unsigned count)
141
-
{
142
-
return (12 << 28) | count;
143
-
}
144
-
145
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
19
+
#include "opcodes.h"
146
20
147
21
#endif
+1
-127
drivers/gpu/host1x/hw/host1x07_hardware.h
+1
-127
drivers/gpu/host1x/hw/host1x07_hardware.h
···
16
16
#include "hw_host1x07_vm.h"
17
17
#include "hw_host1x07_hypervisor.h"
18
18
19
-
static inline u32 host1x_class_host_wait_syncpt(
20
-
unsigned indx, unsigned threshold)
21
-
{
22
-
return host1x_uclass_wait_syncpt_indx_f(indx)
23
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
24
-
}
25
-
26
-
static inline u32 host1x_class_host_load_syncpt_base(
27
-
unsigned indx, unsigned threshold)
28
-
{
29
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
30
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
31
-
}
32
-
33
-
static inline u32 host1x_class_host_wait_syncpt_base(
34
-
unsigned indx, unsigned base_indx, unsigned offset)
35
-
{
36
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
37
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
38
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
39
-
}
40
-
41
-
static inline u32 host1x_class_host_incr_syncpt_base(
42
-
unsigned base_indx, unsigned offset)
43
-
{
44
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
45
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
46
-
}
47
-
48
-
static inline u32 host1x_class_host_incr_syncpt(
49
-
unsigned cond, unsigned indx)
50
-
{
51
-
return host1x_uclass_incr_syncpt_cond_f(cond)
52
-
| host1x_uclass_incr_syncpt_indx_f(indx);
53
-
}
54
-
55
-
static inline u32 host1x_class_host_indoff_reg_write(
56
-
unsigned mod_id, unsigned offset, bool auto_inc)
57
-
{
58
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
59
-
| host1x_uclass_indoff_indmodid_f(mod_id)
60
-
| host1x_uclass_indoff_indroffset_f(offset);
61
-
if (auto_inc)
62
-
v |= host1x_uclass_indoff_autoinc_f(1);
63
-
return v;
64
-
}
65
-
66
-
static inline u32 host1x_class_host_indoff_reg_read(
67
-
unsigned mod_id, unsigned offset, bool auto_inc)
68
-
{
69
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
70
-
| host1x_uclass_indoff_indroffset_f(offset)
71
-
| host1x_uclass_indoff_rwn_read_v();
72
-
if (auto_inc)
73
-
v |= host1x_uclass_indoff_autoinc_f(1);
74
-
return v;
75
-
}
76
-
77
-
/* cdma opcodes */
78
-
static inline u32 host1x_opcode_setclass(
79
-
unsigned class_id, unsigned offset, unsigned mask)
80
-
{
81
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82
-
}
83
-
84
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85
-
{
86
-
return (1 << 28) | (offset << 16) | count;
87
-
}
88
-
89
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90
-
{
91
-
return (2 << 28) | (offset << 16) | count;
92
-
}
93
-
94
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95
-
{
96
-
return (3 << 28) | (offset << 16) | mask;
97
-
}
98
-
99
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100
-
{
101
-
return (4 << 28) | (offset << 16) | value;
102
-
}
103
-
104
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105
-
{
106
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107
-
host1x_class_host_incr_syncpt(cond, indx));
108
-
}
109
-
110
-
static inline u32 host1x_opcode_restart(unsigned address)
111
-
{
112
-
return (5 << 28) | (address >> 4);
113
-
}
114
-
115
-
static inline u32 host1x_opcode_gather(unsigned count)
116
-
{
117
-
return (6 << 28) | count;
118
-
}
119
-
120
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121
-
{
122
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
123
-
}
124
-
125
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126
-
{
127
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128
-
}
129
-
130
-
static inline u32 host1x_opcode_setstreamid(unsigned streamid)
131
-
{
132
-
return (7 << 28) | streamid;
133
-
}
134
-
135
-
static inline u32 host1x_opcode_setpayload(unsigned payload)
136
-
{
137
-
return (9 << 28) | payload;
138
-
}
139
-
140
-
static inline u32 host1x_opcode_gather_wide(unsigned count)
141
-
{
142
-
return (12 << 28) | count;
143
-
}
144
-
145
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
19
+
#include "opcodes.h"
146
20
147
21
#endif
+150
drivers/gpu/host1x/hw/opcodes.h
+150
drivers/gpu/host1x/hw/opcodes.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Tegra host1x opcodes
4
+
*
5
+
* Copyright (c) 2022 NVIDIA Corporation.
6
+
*/
7
+
8
+
#ifndef __HOST1X_OPCODES_H
9
+
#define __HOST1X_OPCODES_H
10
+
11
+
#include <linux/types.h>
12
+
13
+
static inline u32 host1x_class_host_wait_syncpt(
14
+
unsigned indx, unsigned threshold)
15
+
{
16
+
return host1x_uclass_wait_syncpt_indx_f(indx)
17
+
| host1x_uclass_wait_syncpt_thresh_f(threshold);
18
+
}
19
+
20
+
static inline u32 host1x_class_host_load_syncpt_base(
21
+
unsigned indx, unsigned threshold)
22
+
{
23
+
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
24
+
| host1x_uclass_load_syncpt_base_value_f(threshold);
25
+
}
26
+
27
+
static inline u32 host1x_class_host_wait_syncpt_base(
28
+
unsigned indx, unsigned base_indx, unsigned offset)
29
+
{
30
+
return host1x_uclass_wait_syncpt_base_indx_f(indx)
31
+
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
32
+
| host1x_uclass_wait_syncpt_base_offset_f(offset);
33
+
}
34
+
35
+
static inline u32 host1x_class_host_incr_syncpt_base(
36
+
unsigned base_indx, unsigned offset)
37
+
{
38
+
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
39
+
| host1x_uclass_incr_syncpt_base_offset_f(offset);
40
+
}
41
+
42
+
static inline u32 host1x_class_host_incr_syncpt(
43
+
unsigned cond, unsigned indx)
44
+
{
45
+
return host1x_uclass_incr_syncpt_cond_f(cond)
46
+
| host1x_uclass_incr_syncpt_indx_f(indx);
47
+
}
48
+
49
+
static inline u32 host1x_class_host_indoff_reg_write(
50
+
unsigned mod_id, unsigned offset, bool auto_inc)
51
+
{
52
+
u32 v = host1x_uclass_indoff_indbe_f(0xf)
53
+
| host1x_uclass_indoff_indmodid_f(mod_id)
54
+
| host1x_uclass_indoff_indroffset_f(offset);
55
+
if (auto_inc)
56
+
v |= host1x_uclass_indoff_autoinc_f(1);
57
+
return v;
58
+
}
59
+
60
+
static inline u32 host1x_class_host_indoff_reg_read(
61
+
unsigned mod_id, unsigned offset, bool auto_inc)
62
+
{
63
+
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
64
+
| host1x_uclass_indoff_indroffset_f(offset)
65
+
| host1x_uclass_indoff_rwn_read_v();
66
+
if (auto_inc)
67
+
v |= host1x_uclass_indoff_autoinc_f(1);
68
+
return v;
69
+
}
70
+
71
+
static inline u32 host1x_opcode_setclass(
72
+
unsigned class_id, unsigned offset, unsigned mask)
73
+
{
74
+
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
75
+
}
76
+
77
+
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
78
+
{
79
+
return (1 << 28) | (offset << 16) | count;
80
+
}
81
+
82
+
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
83
+
{
84
+
return (2 << 28) | (offset << 16) | count;
85
+
}
86
+
87
+
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
88
+
{
89
+
return (3 << 28) | (offset << 16) | mask;
90
+
}
91
+
92
+
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
93
+
{
94
+
return (4 << 28) | (offset << 16) | value;
95
+
}
96
+
97
+
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
98
+
{
99
+
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
100
+
host1x_class_host_incr_syncpt(cond, indx));
101
+
}
102
+
103
+
static inline u32 host1x_opcode_restart(unsigned address)
104
+
{
105
+
return (5 << 28) | (address >> 4);
106
+
}
107
+
108
+
static inline u32 host1x_opcode_gather(unsigned count)
109
+
{
110
+
return (6 << 28) | count;
111
+
}
112
+
113
+
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
114
+
{
115
+
return (6 << 28) | (offset << 16) | BIT(15) | count;
116
+
}
117
+
118
+
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
119
+
{
120
+
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
121
+
}
122
+
123
+
static inline u32 host1x_opcode_setstreamid(unsigned streamid)
124
+
{
125
+
return (7 << 28) | streamid;
126
+
}
127
+
128
+
static inline u32 host1x_opcode_setpayload(unsigned payload)
129
+
{
130
+
return (9 << 28) | payload;
131
+
}
132
+
133
+
static inline u32 host1x_opcode_gather_wide(unsigned count)
134
+
{
135
+
return (12 << 28) | count;
136
+
}
137
+
138
+
static inline u32 host1x_opcode_acquire_mlock(unsigned mlock)
139
+
{
140
+
return (14 << 28) | (0 << 24) | mlock;
141
+
}
142
+
143
+
static inline u32 host1x_opcode_release_mlock(unsigned mlock)
144
+
{
145
+
return (14 << 28) | (1 << 24) | mlock;
146
+
}
147
+
148
+
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
149
+
150
+
#endif