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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: mediatek: pwrap: add support for MT6359 PMIC
MT6359 is a new power management IC and it is used for
MT6779 SoCs. To define mt6359_regs for pmic register mapping
and pmic_mt6359 for accessing register.
Signed-off-by: Argus Lin <argus.lin@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
authored by
Argus Lin
and committed by
Matthias Brugger
2faccb56
adc4e8fc
+71
+71
drivers/soc/mediatek/mtk-pmic-wrap.c
+71
drivers/soc/mediatek/mtk-pmic-wrap.c
···
111
111
PWRAP_RG_SPI_CON13,
112
112
PWRAP_SPISLV_KEY,
113
113
114
+
/* MT6359 only regs */
115
+
PWRAP_DEW_CRC_SWRST,
116
+
PWRAP_DEW_RG_EN_RECORD,
117
+
PWRAP_DEW_RECORD_CMD0,
118
+
PWRAP_DEW_RECORD_CMD1,
119
+
PWRAP_DEW_RECORD_CMD2,
120
+
PWRAP_DEW_RECORD_CMD3,
121
+
PWRAP_DEW_RECORD_CMD4,
122
+
PWRAP_DEW_RECORD_CMD5,
123
+
PWRAP_DEW_RECORD_WDATA0,
124
+
PWRAP_DEW_RECORD_WDATA1,
125
+
PWRAP_DEW_RECORD_WDATA2,
126
+
PWRAP_DEW_RECORD_WDATA3,
127
+
PWRAP_DEW_RECORD_WDATA4,
128
+
PWRAP_DEW_RECORD_WDATA5,
129
+
PWRAP_DEW_RG_ADDR_TARGET,
130
+
PWRAP_DEW_RG_ADDR_MASK,
131
+
PWRAP_DEW_RG_WDATA_TARGET,
132
+
PWRAP_DEW_RG_WDATA_MASK,
133
+
PWRAP_DEW_RG_SPI_RECORD_CLR,
134
+
PWRAP_DEW_RG_CMD_ALERT_CLR,
135
+
114
136
/* MT6397 only regs */
115
137
PWRAP_DEW_EVENT_OUT_EN,
116
138
PWRAP_DEW_EVENT_SRC_EN,
···
216
194
[PWRAP_RG_SPI_CON7] = 0x043c,
217
195
[PWRAP_RG_SPI_CON8] = 0x043e,
218
196
[PWRAP_RG_SPI_CON13] = 0x0448,
197
+
[PWRAP_SPISLV_KEY] = 0x044a,
198
+
};
199
+
200
+
static const u32 mt6359_regs[] = {
201
+
[PWRAP_DEW_RG_EN_RECORD] = 0x040a,
202
+
[PWRAP_DEW_DIO_EN] = 0x040c,
203
+
[PWRAP_DEW_READ_TEST] = 0x040e,
204
+
[PWRAP_DEW_WRITE_TEST] = 0x0410,
205
+
[PWRAP_DEW_CRC_SWRST] = 0x0412,
206
+
[PWRAP_DEW_CRC_EN] = 0x0414,
207
+
[PWRAP_DEW_CRC_VAL] = 0x0416,
208
+
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
209
+
[PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
210
+
[PWRAP_DEW_CIPHER_EN] = 0x041c,
211
+
[PWRAP_DEW_CIPHER_RDY] = 0x041e,
212
+
[PWRAP_DEW_CIPHER_MODE] = 0x0420,
213
+
[PWRAP_DEW_CIPHER_SWRST] = 0x0422,
214
+
[PWRAP_DEW_RDDMY_NO] = 0x0424,
215
+
[PWRAP_DEW_RECORD_CMD0] = 0x0428,
216
+
[PWRAP_DEW_RECORD_CMD1] = 0x042a,
217
+
[PWRAP_DEW_RECORD_CMD2] = 0x042c,
218
+
[PWRAP_DEW_RECORD_CMD3] = 0x042e,
219
+
[PWRAP_DEW_RECORD_CMD4] = 0x0430,
220
+
[PWRAP_DEW_RECORD_CMD5] = 0x0432,
221
+
[PWRAP_DEW_RECORD_WDATA0] = 0x0434,
222
+
[PWRAP_DEW_RECORD_WDATA1] = 0x0436,
223
+
[PWRAP_DEW_RECORD_WDATA2] = 0x0438,
224
+
[PWRAP_DEW_RECORD_WDATA3] = 0x043a,
225
+
[PWRAP_DEW_RECORD_WDATA4] = 0x043c,
226
+
[PWRAP_DEW_RECORD_WDATA5] = 0x043e,
227
+
[PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
228
+
[PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
229
+
[PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
230
+
[PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
231
+
[PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
232
+
[PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
219
233
[PWRAP_SPISLV_KEY] = 0x044a,
220
234
};
221
235
···
1035
977
PMIC_MT6351,
1036
978
PMIC_MT6357,
1037
979
PMIC_MT6358,
980
+
PMIC_MT6359,
1038
981
PMIC_MT6380,
1039
982
PMIC_MT6397,
1040
983
};
···
1811
1752
.pwrap_write = pwrap_write16,
1812
1753
};
1813
1754
1755
+
static const struct pwrap_slv_type pmic_mt6359 = {
1756
+
.dew_regs = mt6359_regs,
1757
+
.type = PMIC_MT6359,
1758
+
.regmap = &pwrap_regmap_config16,
1759
+
.caps = PWRAP_SLV_CAP_DUALIO,
1760
+
.pwrap_read = pwrap_read16,
1761
+
.pwrap_write = pwrap_write16,
1762
+
};
1763
+
1814
1764
static const struct pwrap_slv_type pmic_mt6380 = {
1815
1765
.dew_regs = NULL,
1816
1766
.type = PMIC_MT6380,
···
1852
1784
}, {
1853
1785
.compatible = "mediatek,mt6358",
1854
1786
.data = &pmic_mt6358,
1787
+
}, {
1788
+
.compatible = "mediatek,mt6359",
1789
+
.data = &pmic_mt6359,
1855
1790
}, {
1856
1791
/* The MT6380 PMIC only implements a regulator, so we bind it
1857
1792
* directly instead of using a MFD.