tjh.dev / kernel
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kernel os linux
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ASoC: AMD : add ACP 2.2 register headers

These are register headers for the ACP (Audio CoProcessor) v2.2

Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Maruthi Srinivas Bayyavarapu and committed by
Mark Brown 2fa86e94 a242cac1

+3969
+609
sound/soc/amd/include/acp_2_2_d.h
··· 1 + /* 2 + * ACP_2_2 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef ACP_2_2_D_H 25 + #define ACP_2_2_D_H 26 + 27 + #define mmACP_DMA_CNTL_0 0x5000 28 + #define mmACP_DMA_CNTL_1 0x5001 29 + #define mmACP_DMA_CNTL_2 0x5002 30 + #define mmACP_DMA_CNTL_3 0x5003 31 + #define mmACP_DMA_CNTL_4 0x5004 32 + #define mmACP_DMA_CNTL_5 0x5005 33 + #define mmACP_DMA_CNTL_6 0x5006 34 + #define mmACP_DMA_CNTL_7 0x5007 35 + #define mmACP_DMA_CNTL_8 0x5008 36 + #define mmACP_DMA_CNTL_9 0x5009 37 + #define mmACP_DMA_CNTL_10 0x500a 38 + #define mmACP_DMA_CNTL_11 0x500b 39 + #define mmACP_DMA_CNTL_12 0x500c 40 + #define mmACP_DMA_CNTL_13 0x500d 41 + #define mmACP_DMA_CNTL_14 0x500e 42 + #define mmACP_DMA_CNTL_15 0x500f 43 + #define mmACP_DMA_DSCR_STRT_IDX_0 0x5010 44 + #define mmACP_DMA_DSCR_STRT_IDX_1 0x5011 45 + #define mmACP_DMA_DSCR_STRT_IDX_2 0x5012 46 + #define mmACP_DMA_DSCR_STRT_IDX_3 0x5013 47 + #define mmACP_DMA_DSCR_STRT_IDX_4 0x5014 48 + #define mmACP_DMA_DSCR_STRT_IDX_5 0x5015 49 + #define mmACP_DMA_DSCR_STRT_IDX_6 0x5016 50 + #define mmACP_DMA_DSCR_STRT_IDX_7 0x5017 51 + #define mmACP_DMA_DSCR_STRT_IDX_8 0x5018 52 + #define mmACP_DMA_DSCR_STRT_IDX_9 0x5019 53 + #define mmACP_DMA_DSCR_STRT_IDX_10 0x501a 54 + #define mmACP_DMA_DSCR_STRT_IDX_11 0x501b 55 + #define mmACP_DMA_DSCR_STRT_IDX_12 0x501c 56 + #define mmACP_DMA_DSCR_STRT_IDX_13 0x501d 57 + #define mmACP_DMA_DSCR_STRT_IDX_14 0x501e 58 + #define mmACP_DMA_DSCR_STRT_IDX_15 0x501f 59 + #define mmACP_DMA_DSCR_CNT_0 0x5020 60 + #define mmACP_DMA_DSCR_CNT_1 0x5021 61 + #define mmACP_DMA_DSCR_CNT_2 0x5022 62 + #define mmACP_DMA_DSCR_CNT_3 0x5023 63 + #define mmACP_DMA_DSCR_CNT_4 0x5024 64 + #define mmACP_DMA_DSCR_CNT_5 0x5025 65 + #define mmACP_DMA_DSCR_CNT_6 0x5026 66 + #define mmACP_DMA_DSCR_CNT_7 0x5027 67 + #define mmACP_DMA_DSCR_CNT_8 0x5028 68 + #define mmACP_DMA_DSCR_CNT_9 0x5029 69 + #define mmACP_DMA_DSCR_CNT_10 0x502a 70 + #define mmACP_DMA_DSCR_CNT_11 0x502b 71 + #define mmACP_DMA_DSCR_CNT_12 0x502c 72 + #define mmACP_DMA_DSCR_CNT_13 0x502d 73 + #define mmACP_DMA_DSCR_CNT_14 0x502e 74 + #define mmACP_DMA_DSCR_CNT_15 0x502f 75 + #define mmACP_DMA_PRIO_0 0x5030 76 + #define mmACP_DMA_PRIO_1 0x5031 77 + #define mmACP_DMA_PRIO_2 0x5032 78 + #define mmACP_DMA_PRIO_3 0x5033 79 + #define mmACP_DMA_PRIO_4 0x5034 80 + #define mmACP_DMA_PRIO_5 0x5035 81 + #define mmACP_DMA_PRIO_6 0x5036 82 + #define mmACP_DMA_PRIO_7 0x5037 83 + #define mmACP_DMA_PRIO_8 0x5038 84 + #define mmACP_DMA_PRIO_9 0x5039 85 + #define mmACP_DMA_PRIO_10 0x503a 86 + #define mmACP_DMA_PRIO_11 0x503b 87 + #define mmACP_DMA_PRIO_12 0x503c 88 + #define mmACP_DMA_PRIO_13 0x503d 89 + #define mmACP_DMA_PRIO_14 0x503e 90 + #define mmACP_DMA_PRIO_15 0x503f 91 + #define mmACP_DMA_CUR_DSCR_0 0x5040 92 + #define mmACP_DMA_CUR_DSCR_1 0x5041 93 + #define mmACP_DMA_CUR_DSCR_2 0x5042 94 + #define mmACP_DMA_CUR_DSCR_3 0x5043 95 + #define mmACP_DMA_CUR_DSCR_4 0x5044 96 + #define mmACP_DMA_CUR_DSCR_5 0x5045 97 + #define mmACP_DMA_CUR_DSCR_6 0x5046 98 + #define mmACP_DMA_CUR_DSCR_7 0x5047 99 + #define mmACP_DMA_CUR_DSCR_8 0x5048 100 + #define mmACP_DMA_CUR_DSCR_9 0x5049 101 + #define mmACP_DMA_CUR_DSCR_10 0x504a 102 + #define mmACP_DMA_CUR_DSCR_11 0x504b 103 + #define mmACP_DMA_CUR_DSCR_12 0x504c 104 + #define mmACP_DMA_CUR_DSCR_13 0x504d 105 + #define mmACP_DMA_CUR_DSCR_14 0x504e 106 + #define mmACP_DMA_CUR_DSCR_15 0x504f 107 + #define mmACP_DMA_CUR_TRANS_CNT_0 0x5050 108 + #define mmACP_DMA_CUR_TRANS_CNT_1 0x5051 109 + #define mmACP_DMA_CUR_TRANS_CNT_2 0x5052 110 + #define mmACP_DMA_CUR_TRANS_CNT_3 0x5053 111 + #define mmACP_DMA_CUR_TRANS_CNT_4 0x5054 112 + #define mmACP_DMA_CUR_TRANS_CNT_5 0x5055 113 + #define mmACP_DMA_CUR_TRANS_CNT_6 0x5056 114 + #define mmACP_DMA_CUR_TRANS_CNT_7 0x5057 115 + #define mmACP_DMA_CUR_TRANS_CNT_8 0x5058 116 + #define mmACP_DMA_CUR_TRANS_CNT_9 0x5059 117 + #define mmACP_DMA_CUR_TRANS_CNT_10 0x505a 118 + #define mmACP_DMA_CUR_TRANS_CNT_11 0x505b 119 + #define mmACP_DMA_CUR_TRANS_CNT_12 0x505c 120 + #define mmACP_DMA_CUR_TRANS_CNT_13 0x505d 121 + #define mmACP_DMA_CUR_TRANS_CNT_14 0x505e 122 + #define mmACP_DMA_CUR_TRANS_CNT_15 0x505f 123 + #define mmACP_DMA_ERR_STS_0 0x5060 124 + #define mmACP_DMA_ERR_STS_1 0x5061 125 + #define mmACP_DMA_ERR_STS_2 0x5062 126 + #define mmACP_DMA_ERR_STS_3 0x5063 127 + #define mmACP_DMA_ERR_STS_4 0x5064 128 + #define mmACP_DMA_ERR_STS_5 0x5065 129 + #define mmACP_DMA_ERR_STS_6 0x5066 130 + #define mmACP_DMA_ERR_STS_7 0x5067 131 + #define mmACP_DMA_ERR_STS_8 0x5068 132 + #define mmACP_DMA_ERR_STS_9 0x5069 133 + #define mmACP_DMA_ERR_STS_10 0x506a 134 + #define mmACP_DMA_ERR_STS_11 0x506b 135 + #define mmACP_DMA_ERR_STS_12 0x506c 136 + #define mmACP_DMA_ERR_STS_13 0x506d 137 + #define mmACP_DMA_ERR_STS_14 0x506e 138 + #define mmACP_DMA_ERR_STS_15 0x506f 139 + #define mmACP_DMA_DESC_BASE_ADDR 0x5070 140 + #define mmACP_DMA_DESC_MAX_NUM_DSCR 0x5071 141 + #define mmACP_DMA_CH_STS 0x5072 142 + #define mmACP_DMA_CH_GROUP 0x5073 143 + #define mmACP_DSP0_CACHE_OFFSET0 0x5078 144 + #define mmACP_DSP0_CACHE_SIZE0 0x5079 145 + #define mmACP_DSP0_CACHE_OFFSET1 0x507a 146 + #define mmACP_DSP0_CACHE_SIZE1 0x507b 147 + #define mmACP_DSP0_CACHE_OFFSET2 0x507c 148 + #define mmACP_DSP0_CACHE_SIZE2 0x507d 149 + #define mmACP_DSP0_CACHE_OFFSET3 0x507e 150 + #define mmACP_DSP0_CACHE_SIZE3 0x507f 151 + #define mmACP_DSP0_CACHE_OFFSET4 0x5080 152 + #define mmACP_DSP0_CACHE_SIZE4 0x5081 153 + #define mmACP_DSP0_CACHE_OFFSET5 0x5082 154 + #define mmACP_DSP0_CACHE_SIZE5 0x5083 155 + #define mmACP_DSP0_CACHE_OFFSET6 0x5084 156 + #define mmACP_DSP0_CACHE_SIZE6 0x5085 157 + #define mmACP_DSP0_CACHE_OFFSET7 0x5086 158 + #define mmACP_DSP0_CACHE_SIZE7 0x5087 159 + #define mmACP_DSP0_CACHE_OFFSET8 0x5088 160 + #define mmACP_DSP0_CACHE_SIZE8 0x5089 161 + #define mmACP_DSP0_NONCACHE_OFFSET0 0x508a 162 + #define mmACP_DSP0_NONCACHE_SIZE0 0x508b 163 + #define mmACP_DSP0_NONCACHE_OFFSET1 0x508c 164 + #define mmACP_DSP0_NONCACHE_SIZE1 0x508d 165 + #define mmACP_DSP0_DEBUG_PC 0x508e 166 + #define mmACP_DSP0_NMI_SEL 0x508f 167 + #define mmACP_DSP0_CLKRST_CNTL 0x5090 168 + #define mmACP_DSP0_RUNSTALL 0x5091 169 + #define mmACP_DSP0_OCD_HALT_ON_RST 0x5092 170 + #define mmACP_DSP0_WAIT_MODE 0x5093 171 + #define mmACP_DSP0_VECT_SEL 0x5094 172 + #define mmACP_DSP0_DEBUG_REG1 0x5095 173 + #define mmACP_DSP0_DEBUG_REG2 0x5096 174 + #define mmACP_DSP0_DEBUG_REG3 0x5097 175 + #define mmACP_DSP1_CACHE_OFFSET0 0x509d 176 + #define mmACP_DSP1_CACHE_SIZE0 0x509e 177 + #define mmACP_DSP1_CACHE_OFFSET1 0x509f 178 + #define mmACP_DSP1_CACHE_SIZE1 0x50a0 179 + #define mmACP_DSP1_CACHE_OFFSET2 0x50a1 180 + #define mmACP_DSP1_CACHE_SIZE2 0x50a2 181 + #define mmACP_DSP1_CACHE_OFFSET3 0x50a3 182 + #define mmACP_DSP1_CACHE_SIZE3 0x50a4 183 + #define mmACP_DSP1_CACHE_OFFSET4 0x50a5 184 + #define mmACP_DSP1_CACHE_SIZE4 0x50a6 185 + #define mmACP_DSP1_CACHE_OFFSET5 0x50a7 186 + #define mmACP_DSP1_CACHE_SIZE5 0x50a8 187 + #define mmACP_DSP1_CACHE_OFFSET6 0x50a9 188 + #define mmACP_DSP1_CACHE_SIZE6 0x50aa 189 + #define mmACP_DSP1_CACHE_OFFSET7 0x50ab 190 + #define mmACP_DSP1_CACHE_SIZE7 0x50ac 191 + #define mmACP_DSP1_CACHE_OFFSET8 0x50ad 192 + #define mmACP_DSP1_CACHE_SIZE8 0x50ae 193 + #define mmACP_DSP1_NONCACHE_OFFSET0 0x50af 194 + #define mmACP_DSP1_NONCACHE_SIZE0 0x50b0 195 + #define mmACP_DSP1_NONCACHE_OFFSET1 0x50b1 196 + #define mmACP_DSP1_NONCACHE_SIZE1 0x50b2 197 + #define mmACP_DSP1_DEBUG_PC 0x50b3 198 + #define mmACP_DSP1_NMI_SEL 0x50b4 199 + #define mmACP_DSP1_CLKRST_CNTL 0x50b5 200 + #define mmACP_DSP1_RUNSTALL 0x50b6 201 + #define mmACP_DSP1_OCD_HALT_ON_RST 0x50b7 202 + #define mmACP_DSP1_WAIT_MODE 0x50b8 203 + #define mmACP_DSP1_VECT_SEL 0x50b9 204 + #define mmACP_DSP1_DEBUG_REG1 0x50ba 205 + #define mmACP_DSP1_DEBUG_REG2 0x50bb 206 + #define mmACP_DSP1_DEBUG_REG3 0x50bc 207 + #define mmACP_DSP2_CACHE_OFFSET0 0x50c2 208 + #define mmACP_DSP2_CACHE_SIZE0 0x50c3 209 + #define mmACP_DSP2_CACHE_OFFSET1 0x50c4 210 + #define mmACP_DSP2_CACHE_SIZE1 0x50c5 211 + #define mmACP_DSP2_CACHE_OFFSET2 0x50c6 212 + #define mmACP_DSP2_CACHE_SIZE2 0x50c7 213 + #define mmACP_DSP2_CACHE_OFFSET3 0x50c8 214 + #define mmACP_DSP2_CACHE_SIZE3 0x50c9 215 + #define mmACP_DSP2_CACHE_OFFSET4 0x50ca 216 + #define mmACP_DSP2_CACHE_SIZE4 0x50cb 217 + #define mmACP_DSP2_CACHE_OFFSET5 0x50cc 218 + #define mmACP_DSP2_CACHE_SIZE5 0x50cd 219 + #define mmACP_DSP2_CACHE_OFFSET6 0x50ce 220 + #define mmACP_DSP2_CACHE_SIZE6 0x50cf 221 + #define mmACP_DSP2_CACHE_OFFSET7 0x50d0 222 + #define mmACP_DSP2_CACHE_SIZE7 0x50d1 223 + #define mmACP_DSP2_CACHE_OFFSET8 0x50d2 224 + #define mmACP_DSP2_CACHE_SIZE8 0x50d3 225 + #define mmACP_DSP2_NONCACHE_OFFSET0 0x50d4 226 + #define mmACP_DSP2_NONCACHE_SIZE0 0x50d5 227 + #define mmACP_DSP2_NONCACHE_OFFSET1 0x50d6 228 + #define mmACP_DSP2_NONCACHE_SIZE1 0x50d7 229 + #define mmACP_DSP2_DEBUG_PC 0x50d8 230 + #define mmACP_DSP2_NMI_SEL 0x50d9 231 + #define mmACP_DSP2_CLKRST_CNTL 0x50da 232 + #define mmACP_DSP2_RUNSTALL 0x50db 233 + #define mmACP_DSP2_OCD_HALT_ON_RST 0x50dc 234 + #define mmACP_DSP2_WAIT_MODE 0x50dd 235 + #define mmACP_DSP2_VECT_SEL 0x50de 236 + #define mmACP_DSP2_DEBUG_REG1 0x50df 237 + #define mmACP_DSP2_DEBUG_REG2 0x50e0 238 + #define mmACP_DSP2_DEBUG_REG3 0x50e1 239 + #define mmACP_AXI2DAGB_ONION_CNTL 0x50e7 240 + #define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR 0x50e8 241 + #define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD 0x50e9 242 + #define mmACP_DAGB_Onion_TransPerf_Counter_Control 0x50ea 243 + #define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current 0x50eb 244 + #define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak 0x50ec 245 + #define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current 0x50ed 246 + #define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak 0x50ee 247 + #define mmACP_AXI2DAGB_GARLIC_CNTL 0x50f3 248 + #define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR 0x50f4 249 + #define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD 0x50f5 250 + #define mmACP_DAGB_Garlic_TransPerf_Counter_Control 0x50f6 251 + #define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current 0x50f7 252 + #define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak 0x50f8 253 + #define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current 0x50f9 254 + #define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak 0x50fa 255 + #define mmACP_DAGB_PAGE_SIZE_GRP_1 0x50ff 256 + #define mmACP_DAGB_BASE_ADDR_GRP_1 0x5100 257 + #define mmACP_DAGB_PAGE_SIZE_GRP_2 0x5101 258 + #define mmACP_DAGB_BASE_ADDR_GRP_2 0x5102 259 + #define mmACP_DAGB_PAGE_SIZE_GRP_3 0x5103 260 + #define mmACP_DAGB_BASE_ADDR_GRP_3 0x5104 261 + #define mmACP_DAGB_PAGE_SIZE_GRP_4 0x5105 262 + #define mmACP_DAGB_BASE_ADDR_GRP_4 0x5106 263 + #define mmACP_DAGB_PAGE_SIZE_GRP_5 0x5107 264 + #define mmACP_DAGB_BASE_ADDR_GRP_5 0x5108 265 + #define mmACP_DAGB_PAGE_SIZE_GRP_6 0x5109 266 + #define mmACP_DAGB_BASE_ADDR_GRP_6 0x510a 267 + #define mmACP_DAGB_PAGE_SIZE_GRP_7 0x510b 268 + #define mmACP_DAGB_BASE_ADDR_GRP_7 0x510c 269 + #define mmACP_DAGB_PAGE_SIZE_GRP_8 0x510d 270 + #define mmACP_DAGB_BASE_ADDR_GRP_8 0x510e 271 + #define mmACP_DAGB_ATU_CTRL 0x510f 272 + #define mmACP_CONTROL 0x5131 273 + #define mmACP_STATUS 0x5133 274 + #define mmACP_SOFT_RESET 0x5134 275 + #define mmACP_PwrMgmt_CNTL 0x5135 276 + #define mmACP_CAC_INDICATOR_CONTROL 0x5136 277 + #define mmACP_SMU_MAILBOX 0x5137 278 + #define mmACP_FUTURE_REG_SCLK_0 0x5138 279 + #define mmACP_FUTURE_REG_SCLK_1 0x5139 280 + #define mmACP_FUTURE_REG_SCLK_2 0x513a 281 + #define mmACP_FUTURE_REG_SCLK_3 0x513b 282 + #define mmACP_FUTURE_REG_SCLK_4 0x513c 283 + #define mmACP_DAGB_DEBUG_CNT_ENABLE 0x513d 284 + #define mmACP_DAGBG_WR_ASK_CNT 0x513e 285 + #define mmACP_DAGBG_WR_GO_CNT 0x513f 286 + #define mmACP_DAGBG_WR_EXP_RESP_CNT 0x5140 287 + #define mmACP_DAGBG_WR_ACTUAL_RESP_CNT 0x5141 288 + #define mmACP_DAGBG_RD_ASK_CNT 0x5142 289 + #define mmACP_DAGBG_RD_GO_CNT 0x5143 290 + #define mmACP_DAGBG_RD_EXP_RESP_CNT 0x5144 291 + #define mmACP_DAGBG_RD_ACTUAL_RESP_CNT 0x5145 292 + #define mmACP_DAGBO_WR_ASK_CNT 0x5146 293 + #define mmACP_DAGBO_WR_GO_CNT 0x5147 294 + #define mmACP_DAGBO_WR_EXP_RESP_CNT 0x5148 295 + #define mmACP_DAGBO_WR_ACTUAL_RESP_CNT 0x5149 296 + #define mmACP_DAGBO_RD_ASK_CNT 0x514a 297 + #define mmACP_DAGBO_RD_GO_CNT 0x514b 298 + #define mmACP_DAGBO_RD_EXP_RESP_CNT 0x514c 299 + #define mmACP_DAGBO_RD_ACTUAL_RESP_CNT 0x514d 300 + #define mmACP_BRB_CONTROL 0x5156 301 + #define mmACP_EXTERNAL_INTR_ENB 0x5157 302 + #define mmACP_EXTERNAL_INTR_CNTL 0x5158 303 + #define mmACP_ERROR_SOURCE_STS 0x5159 304 + #define mmACP_DSP_SW_INTR_TRIG 0x515a 305 + #define mmACP_DSP_SW_INTR_CNTL 0x515b 306 + #define mmACP_DAGBG_TIMEOUT_CNTL 0x515c 307 + #define mmACP_DAGBO_TIMEOUT_CNTL 0x515d 308 + #define mmACP_EXTERNAL_INTR_STAT 0x515e 309 + #define mmACP_DSP_SW_INTR_STAT 0x515f 310 + #define mmACP_DSP0_INTR_CNTL 0x5160 311 + #define mmACP_DSP0_INTR_STAT 0x5161 312 + #define mmACP_DSP0_TIMEOUT_CNTL 0x5162 313 + #define mmACP_DSP1_INTR_CNTL 0x5163 314 + #define mmACP_DSP1_INTR_STAT 0x5164 315 + #define mmACP_DSP1_TIMEOUT_CNTL 0x5165 316 + #define mmACP_DSP2_INTR_CNTL 0x5166 317 + #define mmACP_DSP2_INTR_STAT 0x5167 318 + #define mmACP_DSP2_TIMEOUT_CNTL 0x5168 319 + #define mmACP_DSP0_EXT_TIMER_CNTL 0x5169 320 + #define mmACP_DSP1_EXT_TIMER_CNTL 0x516a 321 + #define mmACP_DSP2_EXT_TIMER_CNTL 0x516b 322 + #define mmACP_AXI2DAGB_SEM_0 0x516c 323 + #define mmACP_AXI2DAGB_SEM_1 0x516d 324 + #define mmACP_AXI2DAGB_SEM_2 0x516e 325 + #define mmACP_AXI2DAGB_SEM_3 0x516f 326 + #define mmACP_AXI2DAGB_SEM_4 0x5170 327 + #define mmACP_AXI2DAGB_SEM_5 0x5171 328 + #define mmACP_AXI2DAGB_SEM_6 0x5172 329 + #define mmACP_AXI2DAGB_SEM_7 0x5173 330 + #define mmACP_AXI2DAGB_SEM_8 0x5174 331 + #define mmACP_AXI2DAGB_SEM_9 0x5175 332 + #define mmACP_AXI2DAGB_SEM_10 0x5176 333 + #define mmACP_AXI2DAGB_SEM_11 0x5177 334 + #define mmACP_AXI2DAGB_SEM_12 0x5178 335 + #define mmACP_AXI2DAGB_SEM_13 0x5179 336 + #define mmACP_AXI2DAGB_SEM_14 0x517a 337 + #define mmACP_AXI2DAGB_SEM_15 0x517b 338 + #define mmACP_AXI2DAGB_SEM_16 0x517c 339 + #define mmACP_AXI2DAGB_SEM_17 0x517d 340 + #define mmACP_AXI2DAGB_SEM_18 0x517e 341 + #define mmACP_AXI2DAGB_SEM_19 0x517f 342 + #define mmACP_AXI2DAGB_SEM_20 0x5180 343 + #define mmACP_AXI2DAGB_SEM_21 0x5181 344 + #define mmACP_AXI2DAGB_SEM_22 0x5182 345 + #define mmACP_AXI2DAGB_SEM_23 0x5183 346 + #define mmACP_AXI2DAGB_SEM_24 0x5184 347 + #define mmACP_AXI2DAGB_SEM_25 0x5185 348 + #define mmACP_AXI2DAGB_SEM_26 0x5186 349 + #define mmACP_AXI2DAGB_SEM_27 0x5187 350 + #define mmACP_AXI2DAGB_SEM_28 0x5188 351 + #define mmACP_AXI2DAGB_SEM_29 0x5189 352 + #define mmACP_AXI2DAGB_SEM_30 0x518a 353 + #define mmACP_AXI2DAGB_SEM_31 0x518b 354 + #define mmACP_AXI2DAGB_SEM_32 0x518c 355 + #define mmACP_AXI2DAGB_SEM_33 0x518d 356 + #define mmACP_AXI2DAGB_SEM_34 0x518e 357 + #define mmACP_AXI2DAGB_SEM_35 0x518f 358 + #define mmACP_AXI2DAGB_SEM_36 0x5190 359 + #define mmACP_AXI2DAGB_SEM_37 0x5191 360 + #define mmACP_AXI2DAGB_SEM_38 0x5192 361 + #define mmACP_AXI2DAGB_SEM_39 0x5193 362 + #define mmACP_AXI2DAGB_SEM_40 0x5194 363 + #define mmACP_AXI2DAGB_SEM_41 0x5195 364 + #define mmACP_AXI2DAGB_SEM_42 0x5196 365 + #define mmACP_AXI2DAGB_SEM_43 0x5197 366 + #define mmACP_AXI2DAGB_SEM_44 0x5198 367 + #define mmACP_AXI2DAGB_SEM_45 0x5199 368 + #define mmACP_AXI2DAGB_SEM_46 0x519a 369 + #define mmACP_AXI2DAGB_SEM_47 0x519b 370 + #define mmACP_SRBM_Client_Base_Addr 0x519c 371 + #define mmACP_SRBM_Client_RDDATA 0x519d 372 + #define mmACP_SRBM_Cycle_Sts 0x519e 373 + #define mmACP_SRBM_Targ_Idx_Addr 0x519f 374 + #define mmACP_SRBM_Targ_Idx_Data 0x51a0 375 + #define mmACP_SEMA_ADDR_LOW 0x51a1 376 + #define mmACP_SEMA_ADDR_HIGH 0x51a2 377 + #define mmACP_SEMA_CMD 0x51a3 378 + #define mmACP_SEMA_STS 0x51a4 379 + #define mmACP_SEMA_REQ 0x51a5 380 + #define mmACP_FW_STATUS 0x51a6 381 + #define mmACP_FUTURE_REG_ACLK_0 0x51a7 382 + #define mmACP_FUTURE_REG_ACLK_1 0x51a8 383 + #define mmACP_FUTURE_REG_ACLK_2 0x51a9 384 + #define mmACP_FUTURE_REG_ACLK_3 0x51aa 385 + #define mmACP_FUTURE_REG_ACLK_4 0x51ab 386 + #define mmACP_TIMER 0x51ac 387 + #define mmACP_TIMER_CNTL 0x51ad 388 + #define mmACP_DSP0_TIMER 0x51ae 389 + #define mmACP_DSP1_TIMER 0x51af 390 + #define mmACP_DSP2_TIMER 0x51b0 391 + #define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH 0x51b1 392 + #define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW 0x51b2 393 + #define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH 0x51b3 394 + #define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW 0x51b4 395 + #define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH 0x51b5 396 + #define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW 0x51b6 397 + #define mmACP_DSP0_CS_STATE 0x51b7 398 + #define mmACP_DSP1_CS_STATE 0x51b8 399 + #define mmACP_DSP2_CS_STATE 0x51b9 400 + #define mmACP_SCRATCH_REG_BASE_ADDR 0x51ba 401 + #define mmCC_ACP_EFUSE 0x51c8 402 + #define mmACP_PGFSM_RETAIN_REG 0x51c9 403 + #define mmACP_PGFSM_CONFIG_REG 0x51ca 404 + #define mmACP_PGFSM_WRITE_REG 0x51cb 405 + #define mmACP_PGFSM_READ_REG_0 0x51cc 406 + #define mmACP_PGFSM_READ_REG_1 0x51cd 407 + #define mmACP_PGFSM_READ_REG_2 0x51ce 408 + #define mmACP_PGFSM_READ_REG_3 0x51cf 409 + #define mmACP_PGFSM_READ_REG_4 0x51d0 410 + #define mmACP_PGFSM_READ_REG_5 0x51d1 411 + #define mmACP_IP_PGFSM_ENABLE 0x51d2 412 + #define mmACP_I2S_PIN_CONFIG 0x51d3 413 + #define mmACP_AZALIA_I2S_SELECT 0x51d4 414 + #define mmACP_CHIP_PKG_FOR_PAD_ISOLATION 0x51d5 415 + #define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL 0x51d6 416 + #define mmACP_BT_UART_PAD_SEL 0x51d7 417 + #define mmACP_SCRATCH_REG_0 0x52c0 418 + #define mmACP_SCRATCH_REG_1 0x52c1 419 + #define mmACP_SCRATCH_REG_2 0x52c2 420 + #define mmACP_SCRATCH_REG_3 0x52c3 421 + #define mmACP_SCRATCH_REG_4 0x52c4 422 + #define mmACP_SCRATCH_REG_5 0x52c5 423 + #define mmACP_SCRATCH_REG_6 0x52c6 424 + #define mmACP_SCRATCH_REG_7 0x52c7 425 + #define mmACP_SCRATCH_REG_8 0x52c8 426 + #define mmACP_SCRATCH_REG_9 0x52c9 427 + #define mmACP_SCRATCH_REG_10 0x52ca 428 + #define mmACP_SCRATCH_REG_11 0x52cb 429 + #define mmACP_SCRATCH_REG_12 0x52cc 430 + #define mmACP_SCRATCH_REG_13 0x52cd 431 + #define mmACP_SCRATCH_REG_14 0x52ce 432 + #define mmACP_SCRATCH_REG_15 0x52cf 433 + #define mmACP_SCRATCH_REG_16 0x52d0 434 + #define mmACP_SCRATCH_REG_17 0x52d1 435 + #define mmACP_SCRATCH_REG_18 0x52d2 436 + #define mmACP_SCRATCH_REG_19 0x52d3 437 + #define mmACP_SCRATCH_REG_20 0x52d4 438 + #define mmACP_SCRATCH_REG_21 0x52d5 439 + #define mmACP_SCRATCH_REG_22 0x52d6 440 + #define mmACP_SCRATCH_REG_23 0x52d7 441 + #define mmACP_SCRATCH_REG_24 0x52d8 442 + #define mmACP_SCRATCH_REG_25 0x52d9 443 + #define mmACP_SCRATCH_REG_26 0x52da 444 + #define mmACP_SCRATCH_REG_27 0x52db 445 + #define mmACP_SCRATCH_REG_28 0x52dc 446 + #define mmACP_SCRATCH_REG_29 0x52dd 447 + #define mmACP_SCRATCH_REG_30 0x52de 448 + #define mmACP_SCRATCH_REG_31 0x52df 449 + #define mmACP_SCRATCH_REG_32 0x52e0 450 + #define mmACP_SCRATCH_REG_33 0x52e1 451 + #define mmACP_SCRATCH_REG_34 0x52e2 452 + #define mmACP_SCRATCH_REG_35 0x52e3 453 + #define mmACP_SCRATCH_REG_36 0x52e4 454 + #define mmACP_SCRATCH_REG_37 0x52e5 455 + #define mmACP_SCRATCH_REG_38 0x52e6 456 + #define mmACP_SCRATCH_REG_39 0x52e7 457 + #define mmACP_SCRATCH_REG_40 0x52e8 458 + #define mmACP_SCRATCH_REG_41 0x52e9 459 + #define mmACP_SCRATCH_REG_42 0x52ea 460 + #define mmACP_SCRATCH_REG_43 0x52eb 461 + #define mmACP_SCRATCH_REG_44 0x52ec 462 + #define mmACP_SCRATCH_REG_45 0x52ed 463 + #define mmACP_SCRATCH_REG_46 0x52ee 464 + #define mmACP_SCRATCH_REG_47 0x52ef 465 + #define mmACP_VOICE_WAKEUP_ENABLE 0x51e8 466 + #define mmACP_VOICE_WAKEUP_STATUS 0x51e9 467 + #define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD 0x51ea 468 + #define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD 0x51eb 469 + #define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES 0x51ec 470 + #define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS 0x51ed 471 + #define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS 0x51ee 472 + #define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION 0x51ef 473 + #define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH 0x51f0 474 + #define mmI2S_VOICE_WAKEUP_DATA_POINTER 0x51f1 475 + #define mmI2S_VOICE_WAKEUP_AUTH_MATCH 0x51f2 476 + #define mmI2S_VOICE_WAKEUP_8KB_WRAP 0x51f3 477 + #define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH 0x51f4 478 + #define mmACP_I2S_RECEIVED_BYTE_CNT_LOW 0x51f5 479 + #define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH 0x51f6 480 + #define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW 0x51f7 481 + #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 482 + #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 483 + #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 484 + #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 485 + #define mmACP_MEM_DEEP_SLEEP_REQ_LO 0x51fc 486 + #define mmACP_MEM_DEEP_SLEEP_REQ_HI 0x51fd 487 + #define mmACP_MEM_DEEP_SLEEP_STS_LO 0x51fe 488 + #define mmACP_MEM_DEEP_SLEEP_STS_HI 0x51ff 489 + #define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO 0x5200 490 + #define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI 0x5201 491 + #define mmACP_MEM_WAKEUP_FROM_SLEEP_LO 0x5202 492 + #define mmACP_MEM_WAKEUP_FROM_SLEEP_HI 0x5203 493 + #define mmACP_I2SSP_IER 0x5210 494 + #define mmACP_I2SSP_IRER 0x5211 495 + #define mmACP_I2SSP_ITER 0x5212 496 + #define mmACP_I2SSP_CER 0x5213 497 + #define mmACP_I2SSP_CCR 0x5214 498 + #define mmACP_I2SSP_RXFFR 0x5215 499 + #define mmACP_I2SSP_TXFFR 0x5216 500 + #define mmACP_I2SSP_LRBR0 0x5218 501 + #define mmACP_I2SSP_RRBR0 0x5219 502 + #define mmACP_I2SSP_RER0 0x521a 503 + #define mmACP_I2SSP_TER0 0x521b 504 + #define mmACP_I2SSP_RCR0 0x521c 505 + #define mmACP_I2SSP_TCR0 0x521d 506 + #define mmACP_I2SSP_ISR0 0x521e 507 + #define mmACP_I2SSP_IMR0 0x521f 508 + #define mmACP_I2SSP_ROR0 0x5220 509 + #define mmACP_I2SSP_TOR0 0x5221 510 + #define mmACP_I2SSP_RFCR0 0x5222 511 + #define mmACP_I2SSP_TFCR0 0x5223 512 + #define mmACP_I2SSP_RFF0 0x5224 513 + #define mmACP_I2SSP_TFF0 0x5225 514 + #define mmACP_I2SSP_RXDMA 0x5226 515 + #define mmACP_I2SSP_RRXDMA 0x5227 516 + #define mmACP_I2SSP_TXDMA 0x5228 517 + #define mmACP_I2SSP_RTXDMA 0x5229 518 + #define mmACP_I2SSP_COMP_PARAM_2 0x522a 519 + #define mmACP_I2SSP_COMP_PARAM_1 0x522b 520 + #define mmACP_I2SSP_COMP_VERSION 0x522c 521 + #define mmACP_I2SSP_COMP_TYPE 0x522d 522 + #define mmACP_I2SMICSP_IER 0x522e 523 + #define mmACP_I2SMICSP_IRER 0x522f 524 + #define mmACP_I2SMICSP_ITER 0x5230 525 + #define mmACP_I2SMICSP_CER 0x5231 526 + #define mmACP_I2SMICSP_CCR 0x5232 527 + #define mmACP_I2SMICSP_RXFFR 0x5233 528 + #define mmACP_I2SMICSP_TXFFR 0x5234 529 + #define mmACP_I2SMICSP_LRBR0 0x5236 530 + #define mmACP_I2SMICSP_RRBR0 0x5237 531 + #define mmACP_I2SMICSP_RER0 0x5238 532 + #define mmACP_I2SMICSP_TER0 0x5239 533 + #define mmACP_I2SMICSP_RCR0 0x523a 534 + #define mmACP_I2SMICSP_TCR0 0x523b 535 + #define mmACP_I2SMICSP_ISR0 0x523c 536 + #define mmACP_I2SMICSP_IMR0 0x523d 537 + #define mmACP_I2SMICSP_ROR0 0x523e 538 + #define mmACP_I2SMICSP_TOR0 0x523f 539 + #define mmACP_I2SMICSP_RFCR0 0x5240 540 + #define mmACP_I2SMICSP_TFCR0 0x5241 541 + #define mmACP_I2SMICSP_RFF0 0x5242 542 + #define mmACP_I2SMICSP_TFF0 0x5243 543 + #define mmACP_I2SMICSP_LRBR1 0x5246 544 + #define mmACP_I2SMICSP_RRBR1 0x5247 545 + #define mmACP_I2SMICSP_RER1 0x5248 546 + #define mmACP_I2SMICSP_TER1 0x5249 547 + #define mmACP_I2SMICSP_RCR1 0x524a 548 + #define mmACP_I2SMICSP_TCR1 0x524b 549 + #define mmACP_I2SMICSP_ISR1 0x524c 550 + #define mmACP_I2SMICSP_IMR1 0x524d 551 + #define mmACP_I2SMICSP_ROR1 0x524e 552 + #define mmACP_I2SMICSP_TOR1 0x524f 553 + #define mmACP_I2SMICSP_RFCR1 0x5250 554 + #define mmACP_I2SMICSP_TFCR1 0x5251 555 + #define mmACP_I2SMICSP_RFF1 0x5252 556 + #define mmACP_I2SMICSP_TFF1 0x5253 557 + #define mmACP_I2SMICSP_RXDMA 0x5254 558 + #define mmACP_I2SMICSP_RRXDMA 0x5255 559 + #define mmACP_I2SMICSP_TXDMA 0x5256 560 + #define mmACP_I2SMICSP_RTXDMA 0x5257 561 + #define mmACP_I2SMICSP_COMP_PARAM_2 0x5258 562 + #define mmACP_I2SMICSP_COMP_PARAM_1 0x5259 563 + #define mmACP_I2SMICSP_COMP_VERSION 0x525a 564 + #define mmACP_I2SMICSP_COMP_TYPE 0x525b 565 + #define mmACP_I2SBT_IER 0x525c 566 + #define mmACP_I2SBT_IRER 0x525d 567 + #define mmACP_I2SBT_ITER 0x525e 568 + #define mmACP_I2SBT_CER 0x525f 569 + #define mmACP_I2SBT_CCR 0x5260 570 + #define mmACP_I2SBT_RXFFR 0x5261 571 + #define mmACP_I2SBT_TXFFR 0x5262 572 + #define mmACP_I2SBT_LRBR0 0x5264 573 + #define mmACP_I2SBT_RRBR0 0x5265 574 + #define mmACP_I2SBT_RER0 0x5266 575 + #define mmACP_I2SBT_TER0 0x5267 576 + #define mmACP_I2SBT_RCR0 0x5268 577 + #define mmACP_I2SBT_TCR0 0x5269 578 + #define mmACP_I2SBT_ISR0 0x526a 579 + #define mmACP_I2SBT_IMR0 0x526b 580 + #define mmACP_I2SBT_ROR0 0x526c 581 + #define mmACP_I2SBT_TOR0 0x526d 582 + #define mmACP_I2SBT_RFCR0 0x526e 583 + #define mmACP_I2SBT_TFCR0 0x526f 584 + #define mmACP_I2SBT_RFF0 0x5270 585 + #define mmACP_I2SBT_TFF0 0x5271 586 + #define mmACP_I2SBT_LRBR1 0x5274 587 + #define mmACP_I2SBT_RRBR1 0x5275 588 + #define mmACP_I2SBT_RER1 0x5276 589 + #define mmACP_I2SBT_TER1 0x5277 590 + #define mmACP_I2SBT_RCR1 0x5278 591 + #define mmACP_I2SBT_TCR1 0x5279 592 + #define mmACP_I2SBT_ISR1 0x527a 593 + #define mmACP_I2SBT_IMR1 0x527b 594 + #define mmACP_I2SBT_ROR1 0x527c 595 + #define mmACP_I2SBT_TOR1 0x527d 596 + #define mmACP_I2SBT_RFCR1 0x527e 597 + #define mmACP_I2SBT_TFCR1 0x527f 598 + #define mmACP_I2SBT_RFF1 0x5280 599 + #define mmACP_I2SBT_TFF1 0x5281 600 + #define mmACP_I2SBT_RXDMA 0x5282 601 + #define mmACP_I2SBT_RRXDMA 0x5283 602 + #define mmACP_I2SBT_TXDMA 0x5284 603 + #define mmACP_I2SBT_RTXDMA 0x5285 604 + #define mmACP_I2SBT_COMP_PARAM_2 0x5286 605 + #define mmACP_I2SBT_COMP_PARAM_1 0x5287 606 + #define mmACP_I2SBT_COMP_VERSION 0x5288 607 + #define mmACP_I2SBT_COMP_TYPE 0x5289 608 + 609 + #endif /* ACP_2_2_D_H */
+1068
sound/soc/amd/include/acp_2_2_enum.h
··· 1 + /* 2 + * ACP_2_2 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef ACP_2_2_ENUM_H 25 + #define ACP_2_2_ENUM_H 26 + 27 + typedef enum DebugBlockId { 28 + DBG_BLOCK_ID_RESERVED = 0x0, 29 + DBG_BLOCK_ID_DBG = 0x1, 30 + DBG_BLOCK_ID_VMC = 0x2, 31 + DBG_BLOCK_ID_PDMA = 0x3, 32 + DBG_BLOCK_ID_CG = 0x4, 33 + DBG_BLOCK_ID_SRBM = 0x5, 34 + DBG_BLOCK_ID_GRBM = 0x6, 35 + DBG_BLOCK_ID_RLC = 0x7, 36 + DBG_BLOCK_ID_CSC = 0x8, 37 + DBG_BLOCK_ID_SEM = 0x9, 38 + DBG_BLOCK_ID_IH = 0xa, 39 + DBG_BLOCK_ID_SC = 0xb, 40 + DBG_BLOCK_ID_SQ = 0xc, 41 + DBG_BLOCK_ID_UVDU = 0xd, 42 + DBG_BLOCK_ID_SQA = 0xe, 43 + DBG_BLOCK_ID_SDMA0 = 0xf, 44 + DBG_BLOCK_ID_SDMA1 = 0x10, 45 + DBG_BLOCK_ID_SPIM = 0x11, 46 + DBG_BLOCK_ID_GDS = 0x12, 47 + DBG_BLOCK_ID_VC0 = 0x13, 48 + DBG_BLOCK_ID_VC1 = 0x14, 49 + DBG_BLOCK_ID_PA0 = 0x15, 50 + DBG_BLOCK_ID_PA1 = 0x16, 51 + DBG_BLOCK_ID_CP0 = 0x17, 52 + DBG_BLOCK_ID_CP1 = 0x18, 53 + DBG_BLOCK_ID_CP2 = 0x19, 54 + DBG_BLOCK_ID_XBR = 0x1a, 55 + DBG_BLOCK_ID_UVDM = 0x1b, 56 + DBG_BLOCK_ID_VGT0 = 0x1c, 57 + DBG_BLOCK_ID_VGT1 = 0x1d, 58 + DBG_BLOCK_ID_IA = 0x1e, 59 + DBG_BLOCK_ID_SXM0 = 0x1f, 60 + DBG_BLOCK_ID_SXM1 = 0x20, 61 + DBG_BLOCK_ID_SCT0 = 0x21, 62 + DBG_BLOCK_ID_SCT1 = 0x22, 63 + DBG_BLOCK_ID_SPM0 = 0x23, 64 + DBG_BLOCK_ID_SPM1 = 0x24, 65 + DBG_BLOCK_ID_UNUSED0 = 0x25, 66 + DBG_BLOCK_ID_UNUSED1 = 0x26, 67 + DBG_BLOCK_ID_TCAA = 0x27, 68 + DBG_BLOCK_ID_TCAB = 0x28, 69 + DBG_BLOCK_ID_TCCA = 0x29, 70 + DBG_BLOCK_ID_TCCB = 0x2a, 71 + DBG_BLOCK_ID_MCC0 = 0x2b, 72 + DBG_BLOCK_ID_MCC1 = 0x2c, 73 + DBG_BLOCK_ID_MCC2 = 0x2d, 74 + DBG_BLOCK_ID_MCC3 = 0x2e, 75 + DBG_BLOCK_ID_SXS0 = 0x2f, 76 + DBG_BLOCK_ID_SXS1 = 0x30, 77 + DBG_BLOCK_ID_SXS2 = 0x31, 78 + DBG_BLOCK_ID_SXS3 = 0x32, 79 + DBG_BLOCK_ID_SXS4 = 0x33, 80 + DBG_BLOCK_ID_SXS5 = 0x34, 81 + DBG_BLOCK_ID_SXS6 = 0x35, 82 + DBG_BLOCK_ID_SXS7 = 0x36, 83 + DBG_BLOCK_ID_SXS8 = 0x37, 84 + DBG_BLOCK_ID_SXS9 = 0x38, 85 + DBG_BLOCK_ID_BCI0 = 0x39, 86 + DBG_BLOCK_ID_BCI1 = 0x3a, 87 + DBG_BLOCK_ID_BCI2 = 0x3b, 88 + DBG_BLOCK_ID_BCI3 = 0x3c, 89 + DBG_BLOCK_ID_MCB = 0x3d, 90 + DBG_BLOCK_ID_UNUSED6 = 0x3e, 91 + DBG_BLOCK_ID_SQA00 = 0x3f, 92 + DBG_BLOCK_ID_SQA01 = 0x40, 93 + DBG_BLOCK_ID_SQA02 = 0x41, 94 + DBG_BLOCK_ID_SQA10 = 0x42, 95 + DBG_BLOCK_ID_SQA11 = 0x43, 96 + DBG_BLOCK_ID_SQA12 = 0x44, 97 + DBG_BLOCK_ID_UNUSED7 = 0x45, 98 + DBG_BLOCK_ID_UNUSED8 = 0x46, 99 + DBG_BLOCK_ID_SQB00 = 0x47, 100 + DBG_BLOCK_ID_SQB01 = 0x48, 101 + DBG_BLOCK_ID_SQB10 = 0x49, 102 + DBG_BLOCK_ID_SQB11 = 0x4a, 103 + DBG_BLOCK_ID_SQ00 = 0x4b, 104 + DBG_BLOCK_ID_SQ01 = 0x4c, 105 + DBG_BLOCK_ID_SQ10 = 0x4d, 106 + DBG_BLOCK_ID_SQ11 = 0x4e, 107 + DBG_BLOCK_ID_CB00 = 0x4f, 108 + DBG_BLOCK_ID_CB01 = 0x50, 109 + DBG_BLOCK_ID_CB02 = 0x51, 110 + DBG_BLOCK_ID_CB03 = 0x52, 111 + DBG_BLOCK_ID_CB04 = 0x53, 112 + DBG_BLOCK_ID_UNUSED9 = 0x54, 113 + DBG_BLOCK_ID_UNUSED10 = 0x55, 114 + DBG_BLOCK_ID_UNUSED11 = 0x56, 115 + DBG_BLOCK_ID_CB10 = 0x57, 116 + DBG_BLOCK_ID_CB11 = 0x58, 117 + DBG_BLOCK_ID_CB12 = 0x59, 118 + DBG_BLOCK_ID_CB13 = 0x5a, 119 + DBG_BLOCK_ID_CB14 = 0x5b, 120 + DBG_BLOCK_ID_UNUSED12 = 0x5c, 121 + DBG_BLOCK_ID_UNUSED13 = 0x5d, 122 + DBG_BLOCK_ID_UNUSED14 = 0x5e, 123 + DBG_BLOCK_ID_TCP0 = 0x5f, 124 + DBG_BLOCK_ID_TCP1 = 0x60, 125 + DBG_BLOCK_ID_TCP2 = 0x61, 126 + DBG_BLOCK_ID_TCP3 = 0x62, 127 + DBG_BLOCK_ID_TCP4 = 0x63, 128 + DBG_BLOCK_ID_TCP5 = 0x64, 129 + DBG_BLOCK_ID_TCP6 = 0x65, 130 + DBG_BLOCK_ID_TCP7 = 0x66, 131 + DBG_BLOCK_ID_TCP8 = 0x67, 132 + DBG_BLOCK_ID_TCP9 = 0x68, 133 + DBG_BLOCK_ID_TCP10 = 0x69, 134 + DBG_BLOCK_ID_TCP11 = 0x6a, 135 + DBG_BLOCK_ID_TCP12 = 0x6b, 136 + DBG_BLOCK_ID_TCP13 = 0x6c, 137 + DBG_BLOCK_ID_TCP14 = 0x6d, 138 + DBG_BLOCK_ID_TCP15 = 0x6e, 139 + DBG_BLOCK_ID_TCP16 = 0x6f, 140 + DBG_BLOCK_ID_TCP17 = 0x70, 141 + DBG_BLOCK_ID_TCP18 = 0x71, 142 + DBG_BLOCK_ID_TCP19 = 0x72, 143 + DBG_BLOCK_ID_TCP20 = 0x73, 144 + DBG_BLOCK_ID_TCP21 = 0x74, 145 + DBG_BLOCK_ID_TCP22 = 0x75, 146 + DBG_BLOCK_ID_TCP23 = 0x76, 147 + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, 148 + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, 149 + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, 150 + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, 151 + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, 152 + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, 153 + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, 154 + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, 155 + DBG_BLOCK_ID_DB00 = 0x7f, 156 + DBG_BLOCK_ID_DB01 = 0x80, 157 + DBG_BLOCK_ID_DB02 = 0x81, 158 + DBG_BLOCK_ID_DB03 = 0x82, 159 + DBG_BLOCK_ID_DB04 = 0x83, 160 + DBG_BLOCK_ID_UNUSED15 = 0x84, 161 + DBG_BLOCK_ID_UNUSED16 = 0x85, 162 + DBG_BLOCK_ID_UNUSED17 = 0x86, 163 + DBG_BLOCK_ID_DB10 = 0x87, 164 + DBG_BLOCK_ID_DB11 = 0x88, 165 + DBG_BLOCK_ID_DB12 = 0x89, 166 + DBG_BLOCK_ID_DB13 = 0x8a, 167 + DBG_BLOCK_ID_DB14 = 0x8b, 168 + DBG_BLOCK_ID_UNUSED18 = 0x8c, 169 + DBG_BLOCK_ID_UNUSED19 = 0x8d, 170 + DBG_BLOCK_ID_UNUSED20 = 0x8e, 171 + DBG_BLOCK_ID_TCC0 = 0x8f, 172 + DBG_BLOCK_ID_TCC1 = 0x90, 173 + DBG_BLOCK_ID_TCC2 = 0x91, 174 + DBG_BLOCK_ID_TCC3 = 0x92, 175 + DBG_BLOCK_ID_TCC4 = 0x93, 176 + DBG_BLOCK_ID_TCC5 = 0x94, 177 + DBG_BLOCK_ID_TCC6 = 0x95, 178 + DBG_BLOCK_ID_TCC7 = 0x96, 179 + DBG_BLOCK_ID_SPS00 = 0x97, 180 + DBG_BLOCK_ID_SPS01 = 0x98, 181 + DBG_BLOCK_ID_SPS02 = 0x99, 182 + DBG_BLOCK_ID_SPS10 = 0x9a, 183 + DBG_BLOCK_ID_SPS11 = 0x9b, 184 + DBG_BLOCK_ID_SPS12 = 0x9c, 185 + DBG_BLOCK_ID_UNUSED21 = 0x9d, 186 + DBG_BLOCK_ID_UNUSED22 = 0x9e, 187 + DBG_BLOCK_ID_TA00 = 0x9f, 188 + DBG_BLOCK_ID_TA01 = 0xa0, 189 + DBG_BLOCK_ID_TA02 = 0xa1, 190 + DBG_BLOCK_ID_TA03 = 0xa2, 191 + DBG_BLOCK_ID_TA04 = 0xa3, 192 + DBG_BLOCK_ID_TA05 = 0xa4, 193 + DBG_BLOCK_ID_TA06 = 0xa5, 194 + DBG_BLOCK_ID_TA07 = 0xa6, 195 + DBG_BLOCK_ID_TA08 = 0xa7, 196 + DBG_BLOCK_ID_TA09 = 0xa8, 197 + DBG_BLOCK_ID_TA0A = 0xa9, 198 + DBG_BLOCK_ID_TA0B = 0xaa, 199 + DBG_BLOCK_ID_UNUSED23 = 0xab, 200 + DBG_BLOCK_ID_UNUSED24 = 0xac, 201 + DBG_BLOCK_ID_UNUSED25 = 0xad, 202 + DBG_BLOCK_ID_UNUSED26 = 0xae, 203 + DBG_BLOCK_ID_TA10 = 0xaf, 204 + DBG_BLOCK_ID_TA11 = 0xb0, 205 + DBG_BLOCK_ID_TA12 = 0xb1, 206 + DBG_BLOCK_ID_TA13 = 0xb2, 207 + DBG_BLOCK_ID_TA14 = 0xb3, 208 + DBG_BLOCK_ID_TA15 = 0xb4, 209 + DBG_BLOCK_ID_TA16 = 0xb5, 210 + DBG_BLOCK_ID_TA17 = 0xb6, 211 + DBG_BLOCK_ID_TA18 = 0xb7, 212 + DBG_BLOCK_ID_TA19 = 0xb8, 213 + DBG_BLOCK_ID_TA1A = 0xb9, 214 + DBG_BLOCK_ID_TA1B = 0xba, 215 + DBG_BLOCK_ID_UNUSED27 = 0xbb, 216 + DBG_BLOCK_ID_UNUSED28 = 0xbc, 217 + DBG_BLOCK_ID_UNUSED29 = 0xbd, 218 + DBG_BLOCK_ID_UNUSED30 = 0xbe, 219 + DBG_BLOCK_ID_TD00 = 0xbf, 220 + DBG_BLOCK_ID_TD01 = 0xc0, 221 + DBG_BLOCK_ID_TD02 = 0xc1, 222 + DBG_BLOCK_ID_TD03 = 0xc2, 223 + DBG_BLOCK_ID_TD04 = 0xc3, 224 + DBG_BLOCK_ID_TD05 = 0xc4, 225 + DBG_BLOCK_ID_TD06 = 0xc5, 226 + DBG_BLOCK_ID_TD07 = 0xc6, 227 + DBG_BLOCK_ID_TD08 = 0xc7, 228 + DBG_BLOCK_ID_TD09 = 0xc8, 229 + DBG_BLOCK_ID_TD0A = 0xc9, 230 + DBG_BLOCK_ID_TD0B = 0xca, 231 + DBG_BLOCK_ID_UNUSED31 = 0xcb, 232 + DBG_BLOCK_ID_UNUSED32 = 0xcc, 233 + DBG_BLOCK_ID_UNUSED33 = 0xcd, 234 + DBG_BLOCK_ID_UNUSED34 = 0xce, 235 + DBG_BLOCK_ID_TD10 = 0xcf, 236 + DBG_BLOCK_ID_TD11 = 0xd0, 237 + DBG_BLOCK_ID_TD12 = 0xd1, 238 + DBG_BLOCK_ID_TD13 = 0xd2, 239 + DBG_BLOCK_ID_TD14 = 0xd3, 240 + DBG_BLOCK_ID_TD15 = 0xd4, 241 + DBG_BLOCK_ID_TD16 = 0xd5, 242 + DBG_BLOCK_ID_TD17 = 0xd6, 243 + DBG_BLOCK_ID_TD18 = 0xd7, 244 + DBG_BLOCK_ID_TD19 = 0xd8, 245 + DBG_BLOCK_ID_TD1A = 0xd9, 246 + DBG_BLOCK_ID_TD1B = 0xda, 247 + DBG_BLOCK_ID_UNUSED35 = 0xdb, 248 + DBG_BLOCK_ID_UNUSED36 = 0xdc, 249 + DBG_BLOCK_ID_UNUSED37 = 0xdd, 250 + DBG_BLOCK_ID_UNUSED38 = 0xde, 251 + DBG_BLOCK_ID_LDS00 = 0xdf, 252 + DBG_BLOCK_ID_LDS01 = 0xe0, 253 + DBG_BLOCK_ID_LDS02 = 0xe1, 254 + DBG_BLOCK_ID_LDS03 = 0xe2, 255 + DBG_BLOCK_ID_LDS04 = 0xe3, 256 + DBG_BLOCK_ID_LDS05 = 0xe4, 257 + DBG_BLOCK_ID_LDS06 = 0xe5, 258 + DBG_BLOCK_ID_LDS07 = 0xe6, 259 + DBG_BLOCK_ID_LDS08 = 0xe7, 260 + DBG_BLOCK_ID_LDS09 = 0xe8, 261 + DBG_BLOCK_ID_LDS0A = 0xe9, 262 + DBG_BLOCK_ID_LDS0B = 0xea, 263 + DBG_BLOCK_ID_UNUSED39 = 0xeb, 264 + DBG_BLOCK_ID_UNUSED40 = 0xec, 265 + DBG_BLOCK_ID_UNUSED41 = 0xed, 266 + DBG_BLOCK_ID_UNUSED42 = 0xee, 267 + DBG_BLOCK_ID_LDS10 = 0xef, 268 + DBG_BLOCK_ID_LDS11 = 0xf0, 269 + DBG_BLOCK_ID_LDS12 = 0xf1, 270 + DBG_BLOCK_ID_LDS13 = 0xf2, 271 + DBG_BLOCK_ID_LDS14 = 0xf3, 272 + DBG_BLOCK_ID_LDS15 = 0xf4, 273 + DBG_BLOCK_ID_LDS16 = 0xf5, 274 + DBG_BLOCK_ID_LDS17 = 0xf6, 275 + DBG_BLOCK_ID_LDS18 = 0xf7, 276 + DBG_BLOCK_ID_LDS19 = 0xf8, 277 + DBG_BLOCK_ID_LDS1A = 0xf9, 278 + DBG_BLOCK_ID_LDS1B = 0xfa, 279 + DBG_BLOCK_ID_UNUSED43 = 0xfb, 280 + DBG_BLOCK_ID_UNUSED44 = 0xfc, 281 + DBG_BLOCK_ID_UNUSED45 = 0xfd, 282 + DBG_BLOCK_ID_UNUSED46 = 0xfe, 283 + } DebugBlockId; 284 + typedef enum DebugBlockId_BY2 { 285 + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 286 + DBG_BLOCK_ID_VMC_BY2 = 0x1, 287 + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, 288 + DBG_BLOCK_ID_GRBM_BY2 = 0x3, 289 + DBG_BLOCK_ID_CSC_BY2 = 0x4, 290 + DBG_BLOCK_ID_IH_BY2 = 0x5, 291 + DBG_BLOCK_ID_SQ_BY2 = 0x6, 292 + DBG_BLOCK_ID_UVD_BY2 = 0x7, 293 + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, 294 + DBG_BLOCK_ID_SPIM_BY2 = 0x9, 295 + DBG_BLOCK_ID_VC0_BY2 = 0xa, 296 + DBG_BLOCK_ID_PA_BY2 = 0xb, 297 + DBG_BLOCK_ID_CP0_BY2 = 0xc, 298 + DBG_BLOCK_ID_CP2_BY2 = 0xd, 299 + DBG_BLOCK_ID_PC0_BY2 = 0xe, 300 + DBG_BLOCK_ID_BCI0_BY2 = 0xf, 301 + DBG_BLOCK_ID_SXM0_BY2 = 0x10, 302 + DBG_BLOCK_ID_SCT0_BY2 = 0x11, 303 + DBG_BLOCK_ID_SPM0_BY2 = 0x12, 304 + DBG_BLOCK_ID_BCI2_BY2 = 0x13, 305 + DBG_BLOCK_ID_TCA_BY2 = 0x14, 306 + DBG_BLOCK_ID_TCCA_BY2 = 0x15, 307 + DBG_BLOCK_ID_MCC_BY2 = 0x16, 308 + DBG_BLOCK_ID_MCC2_BY2 = 0x17, 309 + DBG_BLOCK_ID_MCD_BY2 = 0x18, 310 + DBG_BLOCK_ID_MCD2_BY2 = 0x19, 311 + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, 312 + DBG_BLOCK_ID_MCB_BY2 = 0x1b, 313 + DBG_BLOCK_ID_SQA_BY2 = 0x1c, 314 + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 315 + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, 316 + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, 317 + DBG_BLOCK_ID_SQB_BY2 = 0x20, 318 + DBG_BLOCK_ID_SQB10_BY2 = 0x21, 319 + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, 320 + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, 321 + DBG_BLOCK_ID_CB_BY2 = 0x24, 322 + DBG_BLOCK_ID_CB02_BY2 = 0x25, 323 + DBG_BLOCK_ID_CB10_BY2 = 0x26, 324 + DBG_BLOCK_ID_CB12_BY2 = 0x27, 325 + DBG_BLOCK_ID_SXS_BY2 = 0x28, 326 + DBG_BLOCK_ID_SXS2_BY2 = 0x29, 327 + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, 328 + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, 329 + DBG_BLOCK_ID_DB_BY2 = 0x2c, 330 + DBG_BLOCK_ID_DB02_BY2 = 0x2d, 331 + DBG_BLOCK_ID_DB10_BY2 = 0x2e, 332 + DBG_BLOCK_ID_DB12_BY2 = 0x2f, 333 + DBG_BLOCK_ID_TCP_BY2 = 0x30, 334 + DBG_BLOCK_ID_TCP2_BY2 = 0x31, 335 + DBG_BLOCK_ID_TCP4_BY2 = 0x32, 336 + DBG_BLOCK_ID_TCP6_BY2 = 0x33, 337 + DBG_BLOCK_ID_TCP8_BY2 = 0x34, 338 + DBG_BLOCK_ID_TCP10_BY2 = 0x35, 339 + DBG_BLOCK_ID_TCP12_BY2 = 0x36, 340 + DBG_BLOCK_ID_TCP14_BY2 = 0x37, 341 + DBG_BLOCK_ID_TCP16_BY2 = 0x38, 342 + DBG_BLOCK_ID_TCP18_BY2 = 0x39, 343 + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 344 + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 345 + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 346 + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 347 + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 348 + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 349 + DBG_BLOCK_ID_TCC_BY2 = 0x40, 350 + DBG_BLOCK_ID_TCC2_BY2 = 0x41, 351 + DBG_BLOCK_ID_TCC4_BY2 = 0x42, 352 + DBG_BLOCK_ID_TCC6_BY2 = 0x43, 353 + DBG_BLOCK_ID_SPS_BY2 = 0x44, 354 + DBG_BLOCK_ID_SPS02_BY2 = 0x45, 355 + DBG_BLOCK_ID_SPS11_BY2 = 0x46, 356 + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, 357 + DBG_BLOCK_ID_TA_BY2 = 0x48, 358 + DBG_BLOCK_ID_TA02_BY2 = 0x49, 359 + DBG_BLOCK_ID_TA04_BY2 = 0x4a, 360 + DBG_BLOCK_ID_TA06_BY2 = 0x4b, 361 + DBG_BLOCK_ID_TA08_BY2 = 0x4c, 362 + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, 363 + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, 364 + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, 365 + DBG_BLOCK_ID_TA10_BY2 = 0x50, 366 + DBG_BLOCK_ID_TA12_BY2 = 0x51, 367 + DBG_BLOCK_ID_TA14_BY2 = 0x52, 368 + DBG_BLOCK_ID_TA16_BY2 = 0x53, 369 + DBG_BLOCK_ID_TA18_BY2 = 0x54, 370 + DBG_BLOCK_ID_TA1A_BY2 = 0x55, 371 + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, 372 + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, 373 + DBG_BLOCK_ID_TD_BY2 = 0x58, 374 + DBG_BLOCK_ID_TD02_BY2 = 0x59, 375 + DBG_BLOCK_ID_TD04_BY2 = 0x5a, 376 + DBG_BLOCK_ID_TD06_BY2 = 0x5b, 377 + DBG_BLOCK_ID_TD08_BY2 = 0x5c, 378 + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, 379 + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, 380 + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, 381 + DBG_BLOCK_ID_TD10_BY2 = 0x60, 382 + DBG_BLOCK_ID_TD12_BY2 = 0x61, 383 + DBG_BLOCK_ID_TD14_BY2 = 0x62, 384 + DBG_BLOCK_ID_TD16_BY2 = 0x63, 385 + DBG_BLOCK_ID_TD18_BY2 = 0x64, 386 + DBG_BLOCK_ID_TD1A_BY2 = 0x65, 387 + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, 388 + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, 389 + DBG_BLOCK_ID_LDS_BY2 = 0x68, 390 + DBG_BLOCK_ID_LDS02_BY2 = 0x69, 391 + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, 392 + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, 393 + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, 394 + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, 395 + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, 396 + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, 397 + DBG_BLOCK_ID_LDS10_BY2 = 0x70, 398 + DBG_BLOCK_ID_LDS12_BY2 = 0x71, 399 + DBG_BLOCK_ID_LDS14_BY2 = 0x72, 400 + DBG_BLOCK_ID_LDS16_BY2 = 0x73, 401 + DBG_BLOCK_ID_LDS18_BY2 = 0x74, 402 + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, 403 + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, 404 + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, 405 + } DebugBlockId_BY2; 406 + typedef enum DebugBlockId_BY4 { 407 + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 408 + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, 409 + DBG_BLOCK_ID_CSC_BY4 = 0x2, 410 + DBG_BLOCK_ID_SQ_BY4 = 0x3, 411 + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, 412 + DBG_BLOCK_ID_VC0_BY4 = 0x5, 413 + DBG_BLOCK_ID_CP0_BY4 = 0x6, 414 + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, 415 + DBG_BLOCK_ID_SXM0_BY4 = 0x8, 416 + DBG_BLOCK_ID_SPM0_BY4 = 0x9, 417 + DBG_BLOCK_ID_TCAA_BY4 = 0xa, 418 + DBG_BLOCK_ID_MCC_BY4 = 0xb, 419 + DBG_BLOCK_ID_MCD_BY4 = 0xc, 420 + DBG_BLOCK_ID_MCD4_BY4 = 0xd, 421 + DBG_BLOCK_ID_SQA_BY4 = 0xe, 422 + DBG_BLOCK_ID_SQA11_BY4 = 0xf, 423 + DBG_BLOCK_ID_SQB_BY4 = 0x10, 424 + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, 425 + DBG_BLOCK_ID_CB_BY4 = 0x12, 426 + DBG_BLOCK_ID_CB10_BY4 = 0x13, 427 + DBG_BLOCK_ID_SXS_BY4 = 0x14, 428 + DBG_BLOCK_ID_SXS4_BY4 = 0x15, 429 + DBG_BLOCK_ID_DB_BY4 = 0x16, 430 + DBG_BLOCK_ID_DB10_BY4 = 0x17, 431 + DBG_BLOCK_ID_TCP_BY4 = 0x18, 432 + DBG_BLOCK_ID_TCP4_BY4 = 0x19, 433 + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 434 + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 435 + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 436 + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 437 + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 438 + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 439 + DBG_BLOCK_ID_TCC_BY4 = 0x20, 440 + DBG_BLOCK_ID_TCC4_BY4 = 0x21, 441 + DBG_BLOCK_ID_SPS_BY4 = 0x22, 442 + DBG_BLOCK_ID_SPS11_BY4 = 0x23, 443 + DBG_BLOCK_ID_TA_BY4 = 0x24, 444 + DBG_BLOCK_ID_TA04_BY4 = 0x25, 445 + DBG_BLOCK_ID_TA08_BY4 = 0x26, 446 + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, 447 + DBG_BLOCK_ID_TA10_BY4 = 0x28, 448 + DBG_BLOCK_ID_TA14_BY4 = 0x29, 449 + DBG_BLOCK_ID_TA18_BY4 = 0x2a, 450 + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, 451 + DBG_BLOCK_ID_TD_BY4 = 0x2c, 452 + DBG_BLOCK_ID_TD04_BY4 = 0x2d, 453 + DBG_BLOCK_ID_TD08_BY4 = 0x2e, 454 + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, 455 + DBG_BLOCK_ID_TD10_BY4 = 0x30, 456 + DBG_BLOCK_ID_TD14_BY4 = 0x31, 457 + DBG_BLOCK_ID_TD18_BY4 = 0x32, 458 + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, 459 + DBG_BLOCK_ID_LDS_BY4 = 0x34, 460 + DBG_BLOCK_ID_LDS04_BY4 = 0x35, 461 + DBG_BLOCK_ID_LDS08_BY4 = 0x36, 462 + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, 463 + DBG_BLOCK_ID_LDS10_BY4 = 0x38, 464 + DBG_BLOCK_ID_LDS14_BY4 = 0x39, 465 + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, 466 + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, 467 + } DebugBlockId_BY4; 468 + typedef enum DebugBlockId_BY8 { 469 + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 470 + DBG_BLOCK_ID_CSC_BY8 = 0x1, 471 + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, 472 + DBG_BLOCK_ID_CP0_BY8 = 0x3, 473 + DBG_BLOCK_ID_SXM0_BY8 = 0x4, 474 + DBG_BLOCK_ID_TCA_BY8 = 0x5, 475 + DBG_BLOCK_ID_MCD_BY8 = 0x6, 476 + DBG_BLOCK_ID_SQA_BY8 = 0x7, 477 + DBG_BLOCK_ID_SQB_BY8 = 0x8, 478 + DBG_BLOCK_ID_CB_BY8 = 0x9, 479 + DBG_BLOCK_ID_SXS_BY8 = 0xa, 480 + DBG_BLOCK_ID_DB_BY8 = 0xb, 481 + DBG_BLOCK_ID_TCP_BY8 = 0xc, 482 + DBG_BLOCK_ID_TCP8_BY8 = 0xd, 483 + DBG_BLOCK_ID_TCP16_BY8 = 0xe, 484 + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 485 + DBG_BLOCK_ID_TCC_BY8 = 0x10, 486 + DBG_BLOCK_ID_SPS_BY8 = 0x11, 487 + DBG_BLOCK_ID_TA_BY8 = 0x12, 488 + DBG_BLOCK_ID_TA08_BY8 = 0x13, 489 + DBG_BLOCK_ID_TA10_BY8 = 0x14, 490 + DBG_BLOCK_ID_TA18_BY8 = 0x15, 491 + DBG_BLOCK_ID_TD_BY8 = 0x16, 492 + DBG_BLOCK_ID_TD08_BY8 = 0x17, 493 + DBG_BLOCK_ID_TD10_BY8 = 0x18, 494 + DBG_BLOCK_ID_TD18_BY8 = 0x19, 495 + DBG_BLOCK_ID_LDS_BY8 = 0x1a, 496 + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, 497 + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, 498 + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 499 + } DebugBlockId_BY8; 500 + typedef enum DebugBlockId_BY16 { 501 + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 502 + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, 503 + DBG_BLOCK_ID_SXM_BY16 = 0x2, 504 + DBG_BLOCK_ID_MCD_BY16 = 0x3, 505 + DBG_BLOCK_ID_SQB_BY16 = 0x4, 506 + DBG_BLOCK_ID_SXS_BY16 = 0x5, 507 + DBG_BLOCK_ID_TCP_BY16 = 0x6, 508 + DBG_BLOCK_ID_TCP16_BY16 = 0x7, 509 + DBG_BLOCK_ID_TCC_BY16 = 0x8, 510 + DBG_BLOCK_ID_TA_BY16 = 0x9, 511 + DBG_BLOCK_ID_TA10_BY16 = 0xa, 512 + DBG_BLOCK_ID_TD_BY16 = 0xb, 513 + DBG_BLOCK_ID_TD10_BY16 = 0xc, 514 + DBG_BLOCK_ID_LDS_BY16 = 0xd, 515 + DBG_BLOCK_ID_LDS10_BY16 = 0xe, 516 + } DebugBlockId_BY16; 517 + typedef enum SurfaceEndian { 518 + ENDIAN_NONE = 0x0, 519 + ENDIAN_8IN16 = 0x1, 520 + ENDIAN_8IN32 = 0x2, 521 + ENDIAN_8IN64 = 0x3, 522 + } SurfaceEndian; 523 + typedef enum ArrayMode { 524 + ARRAY_LINEAR_GENERAL = 0x0, 525 + ARRAY_LINEAR_ALIGNED = 0x1, 526 + ARRAY_1D_TILED_THIN1 = 0x2, 527 + ARRAY_1D_TILED_THICK = 0x3, 528 + ARRAY_2D_TILED_THIN1 = 0x4, 529 + ARRAY_PRT_TILED_THIN1 = 0x5, 530 + ARRAY_PRT_2D_TILED_THIN1 = 0x6, 531 + ARRAY_2D_TILED_THICK = 0x7, 532 + ARRAY_2D_TILED_XTHICK = 0x8, 533 + ARRAY_PRT_TILED_THICK = 0x9, 534 + ARRAY_PRT_2D_TILED_THICK = 0xa, 535 + ARRAY_PRT_3D_TILED_THIN1 = 0xb, 536 + ARRAY_3D_TILED_THIN1 = 0xc, 537 + ARRAY_3D_TILED_THICK = 0xd, 538 + ARRAY_3D_TILED_XTHICK = 0xe, 539 + ARRAY_PRT_3D_TILED_THICK = 0xf, 540 + } ArrayMode; 541 + typedef enum PipeTiling { 542 + CONFIG_1_PIPE = 0x0, 543 + CONFIG_2_PIPE = 0x1, 544 + CONFIG_4_PIPE = 0x2, 545 + CONFIG_8_PIPE = 0x3, 546 + } PipeTiling; 547 + typedef enum BankTiling { 548 + CONFIG_4_BANK = 0x0, 549 + CONFIG_8_BANK = 0x1, 550 + } BankTiling; 551 + typedef enum GroupInterleave { 552 + CONFIG_256B_GROUP = 0x0, 553 + CONFIG_512B_GROUP = 0x1, 554 + } GroupInterleave; 555 + typedef enum RowTiling { 556 + CONFIG_1KB_ROW = 0x0, 557 + CONFIG_2KB_ROW = 0x1, 558 + CONFIG_4KB_ROW = 0x2, 559 + CONFIG_8KB_ROW = 0x3, 560 + CONFIG_1KB_ROW_OPT = 0x4, 561 + CONFIG_2KB_ROW_OPT = 0x5, 562 + CONFIG_4KB_ROW_OPT = 0x6, 563 + CONFIG_8KB_ROW_OPT = 0x7, 564 + } RowTiling; 565 + typedef enum BankSwapBytes { 566 + CONFIG_128B_SWAPS = 0x0, 567 + CONFIG_256B_SWAPS = 0x1, 568 + CONFIG_512B_SWAPS = 0x2, 569 + CONFIG_1KB_SWAPS = 0x3, 570 + } BankSwapBytes; 571 + typedef enum SampleSplitBytes { 572 + CONFIG_1KB_SPLIT = 0x0, 573 + CONFIG_2KB_SPLIT = 0x1, 574 + CONFIG_4KB_SPLIT = 0x2, 575 + CONFIG_8KB_SPLIT = 0x3, 576 + } SampleSplitBytes; 577 + typedef enum NumPipes { 578 + ADDR_CONFIG_1_PIPE = 0x0, 579 + ADDR_CONFIG_2_PIPE = 0x1, 580 + ADDR_CONFIG_4_PIPE = 0x2, 581 + ADDR_CONFIG_8_PIPE = 0x3, 582 + } NumPipes; 583 + typedef enum PipeInterleaveSize { 584 + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 585 + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 586 + } PipeInterleaveSize; 587 + typedef enum BankInterleaveSize { 588 + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 589 + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 590 + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 591 + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 592 + } BankInterleaveSize; 593 + typedef enum NumShaderEngines { 594 + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 595 + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 596 + } NumShaderEngines; 597 + typedef enum ShaderEngineTileSize { 598 + ADDR_CONFIG_SE_TILE_16 = 0x0, 599 + ADDR_CONFIG_SE_TILE_32 = 0x1, 600 + } ShaderEngineTileSize; 601 + typedef enum NumGPUs { 602 + ADDR_CONFIG_1_GPU = 0x0, 603 + ADDR_CONFIG_2_GPU = 0x1, 604 + ADDR_CONFIG_4_GPU = 0x2, 605 + } NumGPUs; 606 + typedef enum MultiGPUTileSize { 607 + ADDR_CONFIG_GPU_TILE_16 = 0x0, 608 + ADDR_CONFIG_GPU_TILE_32 = 0x1, 609 + ADDR_CONFIG_GPU_TILE_64 = 0x2, 610 + ADDR_CONFIG_GPU_TILE_128 = 0x3, 611 + } MultiGPUTileSize; 612 + typedef enum RowSize { 613 + ADDR_CONFIG_1KB_ROW = 0x0, 614 + ADDR_CONFIG_2KB_ROW = 0x1, 615 + ADDR_CONFIG_4KB_ROW = 0x2, 616 + } RowSize; 617 + typedef enum NumLowerPipes { 618 + ADDR_CONFIG_1_LOWER_PIPES = 0x0, 619 + ADDR_CONFIG_2_LOWER_PIPES = 0x1, 620 + } NumLowerPipes; 621 + typedef enum ColorTransform { 622 + DCC_CT_AUTO = 0x0, 623 + DCC_CT_NONE = 0x1, 624 + ABGR_TO_A_BG_G_RB = 0x2, 625 + BGRA_TO_BG_G_RB_A = 0x3, 626 + } ColorTransform; 627 + typedef enum CompareRef { 628 + REF_NEVER = 0x0, 629 + REF_LESS = 0x1, 630 + REF_EQUAL = 0x2, 631 + REF_LEQUAL = 0x3, 632 + REF_GREATER = 0x4, 633 + REF_NOTEQUAL = 0x5, 634 + REF_GEQUAL = 0x6, 635 + REF_ALWAYS = 0x7, 636 + } CompareRef; 637 + typedef enum ReadSize { 638 + READ_256_BITS = 0x0, 639 + READ_512_BITS = 0x1, 640 + } ReadSize; 641 + typedef enum DepthFormat { 642 + DEPTH_INVALID = 0x0, 643 + DEPTH_16 = 0x1, 644 + DEPTH_X8_24 = 0x2, 645 + DEPTH_8_24 = 0x3, 646 + DEPTH_X8_24_FLOAT = 0x4, 647 + DEPTH_8_24_FLOAT = 0x5, 648 + DEPTH_32_FLOAT = 0x6, 649 + DEPTH_X24_8_32_FLOAT = 0x7, 650 + } DepthFormat; 651 + typedef enum ZFormat { 652 + Z_INVALID = 0x0, 653 + Z_16 = 0x1, 654 + Z_24 = 0x2, 655 + Z_32_FLOAT = 0x3, 656 + } ZFormat; 657 + typedef enum StencilFormat { 658 + STENCIL_INVALID = 0x0, 659 + STENCIL_8 = 0x1, 660 + } StencilFormat; 661 + typedef enum CmaskMode { 662 + CMASK_CLEAR_NONE = 0x0, 663 + CMASK_CLEAR_ONE = 0x1, 664 + CMASK_CLEAR_ALL = 0x2, 665 + CMASK_ANY_EXPANDED = 0x3, 666 + CMASK_ALPHA0_FRAG1 = 0x4, 667 + CMASK_ALPHA0_FRAG2 = 0x5, 668 + CMASK_ALPHA0_FRAG4 = 0x6, 669 + CMASK_ALPHA0_FRAGS = 0x7, 670 + CMASK_ALPHA1_FRAG1 = 0x8, 671 + CMASK_ALPHA1_FRAG2 = 0x9, 672 + CMASK_ALPHA1_FRAG4 = 0xa, 673 + CMASK_ALPHA1_FRAGS = 0xb, 674 + CMASK_ALPHAX_FRAG1 = 0xc, 675 + CMASK_ALPHAX_FRAG2 = 0xd, 676 + CMASK_ALPHAX_FRAG4 = 0xe, 677 + CMASK_ALPHAX_FRAGS = 0xf, 678 + } CmaskMode; 679 + typedef enum QuadExportFormat { 680 + EXPORT_UNUSED = 0x0, 681 + EXPORT_32_R = 0x1, 682 + EXPORT_32_GR = 0x2, 683 + EXPORT_32_AR = 0x3, 684 + EXPORT_FP16_ABGR = 0x4, 685 + EXPORT_UNSIGNED16_ABGR = 0x5, 686 + EXPORT_SIGNED16_ABGR = 0x6, 687 + EXPORT_32_ABGR = 0x7, 688 + } QuadExportFormat; 689 + typedef enum QuadExportFormatOld { 690 + EXPORT_4P_32BPC_ABGR = 0x0, 691 + EXPORT_4P_16BPC_ABGR = 0x1, 692 + EXPORT_4P_32BPC_GR = 0x2, 693 + EXPORT_4P_32BPC_AR = 0x3, 694 + EXPORT_2P_32BPC_ABGR = 0x4, 695 + EXPORT_8P_32BPC_R = 0x5, 696 + } QuadExportFormatOld; 697 + typedef enum ColorFormat { 698 + COLOR_INVALID = 0x0, 699 + COLOR_8 = 0x1, 700 + COLOR_16 = 0x2, 701 + COLOR_8_8 = 0x3, 702 + COLOR_32 = 0x4, 703 + COLOR_16_16 = 0x5, 704 + COLOR_10_11_11 = 0x6, 705 + COLOR_11_11_10 = 0x7, 706 + COLOR_10_10_10_2 = 0x8, 707 + COLOR_2_10_10_10 = 0x9, 708 + COLOR_8_8_8_8 = 0xa, 709 + COLOR_32_32 = 0xb, 710 + COLOR_16_16_16_16 = 0xc, 711 + COLOR_RESERVED_13 = 0xd, 712 + COLOR_32_32_32_32 = 0xe, 713 + COLOR_RESERVED_15 = 0xf, 714 + COLOR_5_6_5 = 0x10, 715 + COLOR_1_5_5_5 = 0x11, 716 + COLOR_5_5_5_1 = 0x12, 717 + COLOR_4_4_4_4 = 0x13, 718 + COLOR_8_24 = 0x14, 719 + COLOR_24_8 = 0x15, 720 + COLOR_X24_8_32_FLOAT = 0x16, 721 + COLOR_RESERVED_23 = 0x17, 722 + } ColorFormat; 723 + typedef enum SurfaceFormat { 724 + FMT_INVALID = 0x0, 725 + FMT_8 = 0x1, 726 + FMT_16 = 0x2, 727 + FMT_8_8 = 0x3, 728 + FMT_32 = 0x4, 729 + FMT_16_16 = 0x5, 730 + FMT_10_11_11 = 0x6, 731 + FMT_11_11_10 = 0x7, 732 + FMT_10_10_10_2 = 0x8, 733 + FMT_2_10_10_10 = 0x9, 734 + FMT_8_8_8_8 = 0xa, 735 + FMT_32_32 = 0xb, 736 + FMT_16_16_16_16 = 0xc, 737 + FMT_32_32_32 = 0xd, 738 + FMT_32_32_32_32 = 0xe, 739 + FMT_RESERVED_4 = 0xf, 740 + FMT_5_6_5 = 0x10, 741 + FMT_1_5_5_5 = 0x11, 742 + FMT_5_5_5_1 = 0x12, 743 + FMT_4_4_4_4 = 0x13, 744 + FMT_8_24 = 0x14, 745 + FMT_24_8 = 0x15, 746 + FMT_X24_8_32_FLOAT = 0x16, 747 + FMT_RESERVED_33 = 0x17, 748 + FMT_11_11_10_FLOAT = 0x18, 749 + FMT_16_FLOAT = 0x19, 750 + FMT_32_FLOAT = 0x1a, 751 + FMT_16_16_FLOAT = 0x1b, 752 + FMT_8_24_FLOAT = 0x1c, 753 + FMT_24_8_FLOAT = 0x1d, 754 + FMT_32_32_FLOAT = 0x1e, 755 + FMT_10_11_11_FLOAT = 0x1f, 756 + FMT_16_16_16_16_FLOAT = 0x20, 757 + FMT_3_3_2 = 0x21, 758 + FMT_6_5_5 = 0x22, 759 + FMT_32_32_32_32_FLOAT = 0x23, 760 + FMT_RESERVED_36 = 0x24, 761 + FMT_1 = 0x25, 762 + FMT_1_REVERSED = 0x26, 763 + FMT_GB_GR = 0x27, 764 + FMT_BG_RG = 0x28, 765 + FMT_32_AS_8 = 0x29, 766 + FMT_32_AS_8_8 = 0x2a, 767 + FMT_5_9_9_9_SHAREDEXP = 0x2b, 768 + FMT_8_8_8 = 0x2c, 769 + FMT_16_16_16 = 0x2d, 770 + FMT_16_16_16_FLOAT = 0x2e, 771 + FMT_4_4 = 0x2f, 772 + FMT_32_32_32_FLOAT = 0x30, 773 + FMT_BC1 = 0x31, 774 + FMT_BC2 = 0x32, 775 + FMT_BC3 = 0x33, 776 + FMT_BC4 = 0x34, 777 + FMT_BC5 = 0x35, 778 + FMT_BC6 = 0x36, 779 + FMT_BC7 = 0x37, 780 + FMT_32_AS_32_32_32_32 = 0x38, 781 + FMT_APC3 = 0x39, 782 + FMT_APC4 = 0x3a, 783 + FMT_APC5 = 0x3b, 784 + FMT_APC6 = 0x3c, 785 + FMT_APC7 = 0x3d, 786 + FMT_CTX1 = 0x3e, 787 + FMT_RESERVED_63 = 0x3f, 788 + } SurfaceFormat; 789 + typedef enum BUF_DATA_FORMAT { 790 + BUF_DATA_FORMAT_INVALID = 0x0, 791 + BUF_DATA_FORMAT_8 = 0x1, 792 + BUF_DATA_FORMAT_16 = 0x2, 793 + BUF_DATA_FORMAT_8_8 = 0x3, 794 + BUF_DATA_FORMAT_32 = 0x4, 795 + BUF_DATA_FORMAT_16_16 = 0x5, 796 + BUF_DATA_FORMAT_10_11_11 = 0x6, 797 + BUF_DATA_FORMAT_11_11_10 = 0x7, 798 + BUF_DATA_FORMAT_10_10_10_2 = 0x8, 799 + BUF_DATA_FORMAT_2_10_10_10 = 0x9, 800 + BUF_DATA_FORMAT_8_8_8_8 = 0xa, 801 + BUF_DATA_FORMAT_32_32 = 0xb, 802 + BUF_DATA_FORMAT_16_16_16_16 = 0xc, 803 + BUF_DATA_FORMAT_32_32_32 = 0xd, 804 + BUF_DATA_FORMAT_32_32_32_32 = 0xe, 805 + BUF_DATA_FORMAT_RESERVED_15 = 0xf, 806 + } BUF_DATA_FORMAT; 807 + typedef enum IMG_DATA_FORMAT { 808 + IMG_DATA_FORMAT_INVALID = 0x0, 809 + IMG_DATA_FORMAT_8 = 0x1, 810 + IMG_DATA_FORMAT_16 = 0x2, 811 + IMG_DATA_FORMAT_8_8 = 0x3, 812 + IMG_DATA_FORMAT_32 = 0x4, 813 + IMG_DATA_FORMAT_16_16 = 0x5, 814 + IMG_DATA_FORMAT_10_11_11 = 0x6, 815 + IMG_DATA_FORMAT_11_11_10 = 0x7, 816 + IMG_DATA_FORMAT_10_10_10_2 = 0x8, 817 + IMG_DATA_FORMAT_2_10_10_10 = 0x9, 818 + IMG_DATA_FORMAT_8_8_8_8 = 0xa, 819 + IMG_DATA_FORMAT_32_32 = 0xb, 820 + IMG_DATA_FORMAT_16_16_16_16 = 0xc, 821 + IMG_DATA_FORMAT_32_32_32 = 0xd, 822 + IMG_DATA_FORMAT_32_32_32_32 = 0xe, 823 + IMG_DATA_FORMAT_RESERVED_15 = 0xf, 824 + IMG_DATA_FORMAT_5_6_5 = 0x10, 825 + IMG_DATA_FORMAT_1_5_5_5 = 0x11, 826 + IMG_DATA_FORMAT_5_5_5_1 = 0x12, 827 + IMG_DATA_FORMAT_4_4_4_4 = 0x13, 828 + IMG_DATA_FORMAT_8_24 = 0x14, 829 + IMG_DATA_FORMAT_24_8 = 0x15, 830 + IMG_DATA_FORMAT_X24_8_32 = 0x16, 831 + IMG_DATA_FORMAT_RESERVED_23 = 0x17, 832 + IMG_DATA_FORMAT_RESERVED_24 = 0x18, 833 + IMG_DATA_FORMAT_RESERVED_25 = 0x19, 834 + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 835 + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 836 + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 837 + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 838 + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 839 + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 840 + IMG_DATA_FORMAT_GB_GR = 0x20, 841 + IMG_DATA_FORMAT_BG_RG = 0x21, 842 + IMG_DATA_FORMAT_5_9_9_9 = 0x22, 843 + IMG_DATA_FORMAT_BC1 = 0x23, 844 + IMG_DATA_FORMAT_BC2 = 0x24, 845 + IMG_DATA_FORMAT_BC3 = 0x25, 846 + IMG_DATA_FORMAT_BC4 = 0x26, 847 + IMG_DATA_FORMAT_BC5 = 0x27, 848 + IMG_DATA_FORMAT_BC6 = 0x28, 849 + IMG_DATA_FORMAT_BC7 = 0x29, 850 + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 851 + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 852 + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 853 + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 854 + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 855 + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 856 + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 857 + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 858 + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 859 + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 860 + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 861 + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 862 + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 863 + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 864 + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 865 + IMG_DATA_FORMAT_4_4 = 0x39, 866 + IMG_DATA_FORMAT_6_5_5 = 0x3a, 867 + IMG_DATA_FORMAT_1 = 0x3b, 868 + IMG_DATA_FORMAT_1_REVERSED = 0x3c, 869 + IMG_DATA_FORMAT_32_AS_8 = 0x3d, 870 + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 871 + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 872 + } IMG_DATA_FORMAT; 873 + typedef enum BUF_NUM_FORMAT { 874 + BUF_NUM_FORMAT_UNORM = 0x0, 875 + BUF_NUM_FORMAT_SNORM = 0x1, 876 + BUF_NUM_FORMAT_USCALED = 0x2, 877 + BUF_NUM_FORMAT_SSCALED = 0x3, 878 + BUF_NUM_FORMAT_UINT = 0x4, 879 + BUF_NUM_FORMAT_SINT = 0x5, 880 + BUF_NUM_FORMAT_RESERVED_6 = 0x6, 881 + BUF_NUM_FORMAT_FLOAT = 0x7, 882 + } BUF_NUM_FORMAT; 883 + typedef enum IMG_NUM_FORMAT { 884 + IMG_NUM_FORMAT_UNORM = 0x0, 885 + IMG_NUM_FORMAT_SNORM = 0x1, 886 + IMG_NUM_FORMAT_USCALED = 0x2, 887 + IMG_NUM_FORMAT_SSCALED = 0x3, 888 + IMG_NUM_FORMAT_UINT = 0x4, 889 + IMG_NUM_FORMAT_SINT = 0x5, 890 + IMG_NUM_FORMAT_RESERVED_6 = 0x6, 891 + IMG_NUM_FORMAT_FLOAT = 0x7, 892 + IMG_NUM_FORMAT_RESERVED_8 = 0x8, 893 + IMG_NUM_FORMAT_SRGB = 0x9, 894 + IMG_NUM_FORMAT_RESERVED_10 = 0xa, 895 + IMG_NUM_FORMAT_RESERVED_11 = 0xb, 896 + IMG_NUM_FORMAT_RESERVED_12 = 0xc, 897 + IMG_NUM_FORMAT_RESERVED_13 = 0xd, 898 + IMG_NUM_FORMAT_RESERVED_14 = 0xe, 899 + IMG_NUM_FORMAT_RESERVED_15 = 0xf, 900 + } IMG_NUM_FORMAT; 901 + typedef enum TileType { 902 + ARRAY_COLOR_TILE = 0x0, 903 + ARRAY_DEPTH_TILE = 0x1, 904 + } TileType; 905 + typedef enum NonDispTilingOrder { 906 + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 907 + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 908 + } NonDispTilingOrder; 909 + typedef enum MicroTileMode { 910 + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 911 + ADDR_SURF_THIN_MICRO_TILING = 0x1, 912 + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 913 + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 914 + ADDR_SURF_THICK_MICRO_TILING = 0x4, 915 + } MicroTileMode; 916 + typedef enum TileSplit { 917 + ADDR_SURF_TILE_SPLIT_64B = 0x0, 918 + ADDR_SURF_TILE_SPLIT_128B = 0x1, 919 + ADDR_SURF_TILE_SPLIT_256B = 0x2, 920 + ADDR_SURF_TILE_SPLIT_512B = 0x3, 921 + ADDR_SURF_TILE_SPLIT_1KB = 0x4, 922 + ADDR_SURF_TILE_SPLIT_2KB = 0x5, 923 + ADDR_SURF_TILE_SPLIT_4KB = 0x6, 924 + } TileSplit; 925 + typedef enum SampleSplit { 926 + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 927 + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 928 + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 929 + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 930 + } SampleSplit; 931 + typedef enum PipeConfig { 932 + ADDR_SURF_P2 = 0x0, 933 + ADDR_SURF_P2_RESERVED0 = 0x1, 934 + ADDR_SURF_P2_RESERVED1 = 0x2, 935 + ADDR_SURF_P2_RESERVED2 = 0x3, 936 + ADDR_SURF_P4_8x16 = 0x4, 937 + ADDR_SURF_P4_16x16 = 0x5, 938 + ADDR_SURF_P4_16x32 = 0x6, 939 + ADDR_SURF_P4_32x32 = 0x7, 940 + ADDR_SURF_P8_16x16_8x16 = 0x8, 941 + ADDR_SURF_P8_16x32_8x16 = 0x9, 942 + ADDR_SURF_P8_32x32_8x16 = 0xa, 943 + ADDR_SURF_P8_16x32_16x16 = 0xb, 944 + ADDR_SURF_P8_32x32_16x16 = 0xc, 945 + ADDR_SURF_P8_32x32_16x32 = 0xd, 946 + ADDR_SURF_P8_32x64_32x32 = 0xe, 947 + ADDR_SURF_P8_RESERVED0 = 0xf, 948 + ADDR_SURF_P16_32x32_8x16 = 0x10, 949 + ADDR_SURF_P16_32x32_16x16 = 0x11, 950 + } PipeConfig; 951 + typedef enum NumBanks { 952 + ADDR_SURF_2_BANK = 0x0, 953 + ADDR_SURF_4_BANK = 0x1, 954 + ADDR_SURF_8_BANK = 0x2, 955 + ADDR_SURF_16_BANK = 0x3, 956 + } NumBanks; 957 + typedef enum BankWidth { 958 + ADDR_SURF_BANK_WIDTH_1 = 0x0, 959 + ADDR_SURF_BANK_WIDTH_2 = 0x1, 960 + ADDR_SURF_BANK_WIDTH_4 = 0x2, 961 + ADDR_SURF_BANK_WIDTH_8 = 0x3, 962 + } BankWidth; 963 + typedef enum BankHeight { 964 + ADDR_SURF_BANK_HEIGHT_1 = 0x0, 965 + ADDR_SURF_BANK_HEIGHT_2 = 0x1, 966 + ADDR_SURF_BANK_HEIGHT_4 = 0x2, 967 + ADDR_SURF_BANK_HEIGHT_8 = 0x3, 968 + } BankHeight; 969 + typedef enum BankWidthHeight { 970 + ADDR_SURF_BANK_WH_1 = 0x0, 971 + ADDR_SURF_BANK_WH_2 = 0x1, 972 + ADDR_SURF_BANK_WH_4 = 0x2, 973 + ADDR_SURF_BANK_WH_8 = 0x3, 974 + } BankWidthHeight; 975 + typedef enum MacroTileAspect { 976 + ADDR_SURF_MACRO_ASPECT_1 = 0x0, 977 + ADDR_SURF_MACRO_ASPECT_2 = 0x1, 978 + ADDR_SURF_MACRO_ASPECT_4 = 0x2, 979 + ADDR_SURF_MACRO_ASPECT_8 = 0x3, 980 + } MacroTileAspect; 981 + typedef enum GATCL1RequestType { 982 + GATCL1_TYPE_NORMAL = 0x0, 983 + GATCL1_TYPE_SHOOTDOWN = 0x1, 984 + GATCL1_TYPE_BYPASS = 0x2, 985 + } GATCL1RequestType; 986 + typedef enum TCC_CACHE_POLICIES { 987 + TCC_CACHE_POLICY_LRU = 0x0, 988 + TCC_CACHE_POLICY_STREAM = 0x1, 989 + } TCC_CACHE_POLICIES; 990 + typedef enum MTYPE { 991 + MTYPE_NC_NV = 0x0, 992 + MTYPE_NC = 0x1, 993 + MTYPE_CC = 0x2, 994 + MTYPE_UC = 0x3, 995 + } MTYPE; 996 + typedef enum PERFMON_COUNTER_MODE { 997 + PERFMON_COUNTER_MODE_ACCUM = 0x0, 998 + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 999 + PERFMON_COUNTER_MODE_MAX = 0x2, 1000 + PERFMON_COUNTER_MODE_DIRTY = 0x3, 1001 + PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1002 + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1003 + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1004 + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1005 + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1006 + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1007 + PERFMON_COUNTER_MODE_RESERVED = 0xf, 1008 + } PERFMON_COUNTER_MODE; 1009 + typedef enum PERFMON_SPM_MODE { 1010 + PERFMON_SPM_MODE_OFF = 0x0, 1011 + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1012 + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1013 + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1014 + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1015 + PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1016 + PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1017 + PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1018 + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1019 + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1020 + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1021 + } PERFMON_SPM_MODE; 1022 + typedef enum SurfaceTiling { 1023 + ARRAY_LINEAR = 0x0, 1024 + ARRAY_TILED = 0x1, 1025 + } SurfaceTiling; 1026 + typedef enum SurfaceArray { 1027 + ARRAY_1D = 0x0, 1028 + ARRAY_2D = 0x1, 1029 + ARRAY_3D = 0x2, 1030 + ARRAY_3D_SLICE = 0x3, 1031 + } SurfaceArray; 1032 + typedef enum ColorArray { 1033 + ARRAY_2D_ALT_COLOR = 0x0, 1034 + ARRAY_2D_COLOR = 0x1, 1035 + ARRAY_3D_SLICE_COLOR = 0x3, 1036 + } ColorArray; 1037 + typedef enum DepthArray { 1038 + ARRAY_2D_ALT_DEPTH = 0x0, 1039 + ARRAY_2D_DEPTH = 0x1, 1040 + } DepthArray; 1041 + typedef enum ENUM_NUM_SIMD_PER_CU { 1042 + NUM_SIMD_PER_CU = 0x4, 1043 + } ENUM_NUM_SIMD_PER_CU; 1044 + typedef enum MEM_PWR_FORCE_CTRL { 1045 + NO_FORCE_REQUEST = 0x0, 1046 + FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1047 + FORCE_DEEP_SLEEP_REQUEST = 0x2, 1048 + FORCE_SHUT_DOWN_REQUEST = 0x3, 1049 + } MEM_PWR_FORCE_CTRL; 1050 + typedef enum MEM_PWR_FORCE_CTRL2 { 1051 + NO_FORCE_REQ = 0x0, 1052 + FORCE_LIGHT_SLEEP_REQ = 0x1, 1053 + } MEM_PWR_FORCE_CTRL2; 1054 + typedef enum MEM_PWR_DIS_CTRL { 1055 + ENABLE_MEM_PWR_CTRL = 0x0, 1056 + DISABLE_MEM_PWR_CTRL = 0x1, 1057 + } MEM_PWR_DIS_CTRL; 1058 + typedef enum MEM_PWR_SEL_CTRL { 1059 + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1060 + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1061 + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1062 + } MEM_PWR_SEL_CTRL; 1063 + typedef enum MEM_PWR_SEL_CTRL2 { 1064 + DYNAMIC_DEEP_SLEEP_EN = 0x0, 1065 + DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1066 + } MEM_PWR_SEL_CTRL2; 1067 + 1068 + #endif /* ACP_2_2_ENUM_H */
+2292
sound/soc/amd/include/acp_2_2_sh_mask.h
··· 1 + /* 2 + * ACP_2_2 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef ACP_2_2_SH_MASK_H 25 + #define ACP_2_2_SH_MASK_H 26 + 27 + #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1 28 + #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0 29 + #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2 30 + #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1 31 + #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4 32 + #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2 33 + #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8 34 + #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3 35 + #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10 36 + #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4 37 + #define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1 38 + #define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0 39 + #define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2 40 + #define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1 41 + #define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4 42 + #define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2 43 + #define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8 44 + #define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3 45 + #define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10 46 + #define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4 47 + #define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1 48 + #define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0 49 + #define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2 50 + #define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1 51 + #define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4 52 + #define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2 53 + #define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8 54 + #define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3 55 + #define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10 56 + #define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4 57 + #define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1 58 + #define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0 59 + #define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2 60 + #define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1 61 + #define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4 62 + #define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2 63 + #define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8 64 + #define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3 65 + #define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10 66 + #define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4 67 + #define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1 68 + #define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0 69 + #define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2 70 + #define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1 71 + #define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4 72 + #define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2 73 + #define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8 74 + #define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3 75 + #define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10 76 + #define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4 77 + #define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1 78 + #define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0 79 + #define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2 80 + #define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1 81 + #define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4 82 + #define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2 83 + #define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8 84 + #define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3 85 + #define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10 86 + #define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4 87 + #define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1 88 + #define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0 89 + #define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2 90 + #define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1 91 + #define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4 92 + #define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2 93 + #define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8 94 + #define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3 95 + #define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10 96 + #define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4 97 + #define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1 98 + #define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0 99 + #define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2 100 + #define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1 101 + #define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4 102 + #define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2 103 + #define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8 104 + #define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3 105 + #define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10 106 + #define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4 107 + #define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1 108 + #define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0 109 + #define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2 110 + #define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1 111 + #define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4 112 + #define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2 113 + #define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8 114 + #define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3 115 + #define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10 116 + #define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4 117 + #define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1 118 + #define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0 119 + #define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2 120 + #define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1 121 + #define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4 122 + #define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2 123 + #define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8 124 + #define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3 125 + #define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10 126 + #define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4 127 + #define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1 128 + #define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0 129 + #define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2 130 + #define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1 131 + #define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4 132 + #define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2 133 + #define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8 134 + #define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3 135 + #define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10 136 + #define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4 137 + #define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1 138 + #define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0 139 + #define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2 140 + #define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1 141 + #define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4 142 + #define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2 143 + #define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8 144 + #define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3 145 + #define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10 146 + #define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4 147 + #define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1 148 + #define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0 149 + #define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2 150 + #define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1 151 + #define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4 152 + #define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2 153 + #define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8 154 + #define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3 155 + #define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10 156 + #define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4 157 + #define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1 158 + #define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0 159 + #define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2 160 + #define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1 161 + #define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4 162 + #define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2 163 + #define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8 164 + #define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3 165 + #define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10 166 + #define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4 167 + #define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1 168 + #define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0 169 + #define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2 170 + #define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1 171 + #define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4 172 + #define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2 173 + #define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8 174 + #define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3 175 + #define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10 176 + #define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4 177 + #define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1 178 + #define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0 179 + #define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2 180 + #define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1 181 + #define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4 182 + #define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2 183 + #define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8 184 + #define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3 185 + #define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10 186 + #define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4 187 + #define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff 188 + #define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0 189 + #define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff 190 + #define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0 191 + #define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff 192 + #define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0 193 + #define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff 194 + #define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0 195 + #define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff 196 + #define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0 197 + #define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff 198 + #define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0 199 + #define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff 200 + #define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0 201 + #define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff 202 + #define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0 203 + #define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff 204 + #define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0 205 + #define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff 206 + #define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0 207 + #define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff 208 + #define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0 209 + #define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff 210 + #define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0 211 + #define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff 212 + #define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0 213 + #define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff 214 + #define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0 215 + #define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff 216 + #define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0 217 + #define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff 218 + #define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0 219 + #define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff 220 + #define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0 221 + #define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff 222 + #define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0 223 + #define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff 224 + #define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0 225 + #define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff 226 + #define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0 227 + #define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff 228 + #define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0 229 + #define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff 230 + #define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0 231 + #define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff 232 + #define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0 233 + #define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff 234 + #define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0 235 + #define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff 236 + #define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0 237 + #define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff 238 + #define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0 239 + #define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff 240 + #define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0 241 + #define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff 242 + #define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0 243 + #define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff 244 + #define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0 245 + #define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff 246 + #define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0 247 + #define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff 248 + #define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0 249 + #define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff 250 + #define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0 251 + #define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1 252 + #define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0 253 + #define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1 254 + #define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0 255 + #define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1 256 + #define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0 257 + #define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1 258 + #define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0 259 + #define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1 260 + #define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0 261 + #define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1 262 + #define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0 263 + #define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1 264 + #define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0 265 + #define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1 266 + #define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0 267 + #define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1 268 + #define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0 269 + #define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1 270 + #define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0 271 + #define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1 272 + #define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0 273 + #define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1 274 + #define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0 275 + #define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1 276 + #define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0 277 + #define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1 278 + #define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0 279 + #define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1 280 + #define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0 281 + #define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1 282 + #define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0 283 + #define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff 284 + #define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0 285 + #define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff 286 + #define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0 287 + #define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff 288 + #define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0 289 + #define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff 290 + #define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0 291 + #define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff 292 + #define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0 293 + #define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff 294 + #define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0 295 + #define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff 296 + #define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0 297 + #define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff 298 + #define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0 299 + #define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff 300 + #define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0 301 + #define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff 302 + #define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0 303 + #define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff 304 + #define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0 305 + #define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff 306 + #define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0 307 + #define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff 308 + #define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0 309 + #define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff 310 + #define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0 311 + #define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff 312 + #define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0 313 + #define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff 314 + #define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0 315 + #define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff 316 + #define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0 317 + #define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff 318 + #define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0 319 + #define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff 320 + #define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0 321 + #define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff 322 + #define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0 323 + #define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff 324 + #define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0 325 + #define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff 326 + #define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0 327 + #define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff 328 + #define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0 329 + #define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff 330 + #define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0 331 + #define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff 332 + #define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0 333 + #define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff 334 + #define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0 335 + #define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff 336 + #define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0 337 + #define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff 338 + #define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0 339 + #define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff 340 + #define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0 341 + #define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff 342 + #define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0 343 + #define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff 344 + #define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0 345 + #define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff 346 + #define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0 347 + #define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1 348 + #define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0 349 + #define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e 350 + #define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1 351 + #define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1 352 + #define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0 353 + #define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e 354 + #define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1 355 + #define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1 356 + #define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0 357 + #define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e 358 + #define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1 359 + #define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1 360 + #define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0 361 + #define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e 362 + #define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1 363 + #define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1 364 + #define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0 365 + #define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e 366 + #define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1 367 + #define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1 368 + #define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0 369 + #define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e 370 + #define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1 371 + #define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1 372 + #define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0 373 + #define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e 374 + #define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1 375 + #define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1 376 + #define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0 377 + #define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e 378 + #define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1 379 + #define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1 380 + #define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0 381 + #define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e 382 + #define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1 383 + #define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1 384 + #define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0 385 + #define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e 386 + #define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1 387 + #define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1 388 + #define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0 389 + #define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e 390 + #define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1 391 + #define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1 392 + #define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0 393 + #define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e 394 + #define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1 395 + #define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1 396 + #define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0 397 + #define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e 398 + #define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1 399 + #define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1 400 + #define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0 401 + #define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e 402 + #define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1 403 + #define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1 404 + #define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0 405 + #define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e 406 + #define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1 407 + #define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1 408 + #define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0 409 + #define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e 410 + #define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1 411 + #define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff 412 + #define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0 413 + #define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf 414 + #define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0 415 + #define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff 416 + #define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0 417 + #define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1 418 + #define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0 419 + #define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff 420 + #define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0 421 + #define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 422 + #define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f 423 + #define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff 424 + #define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0 425 + #define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000 426 + #define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f 427 + #define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff 428 + #define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0 429 + #define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 430 + #define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f 431 + #define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff 432 + #define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0 433 + #define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000 434 + #define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f 435 + #define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff 436 + #define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0 437 + #define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 438 + #define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f 439 + #define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff 440 + #define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0 441 + #define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000 442 + #define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f 443 + #define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff 444 + #define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0 445 + #define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 446 + #define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f 447 + #define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff 448 + #define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0 449 + #define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000 450 + #define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f 451 + #define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff 452 + #define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0 453 + #define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 454 + #define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f 455 + #define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff 456 + #define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0 457 + #define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000 458 + #define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f 459 + #define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff 460 + #define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0 461 + #define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 462 + #define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f 463 + #define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff 464 + #define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0 465 + #define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000 466 + #define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f 467 + #define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff 468 + #define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0 469 + #define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 470 + #define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f 471 + #define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff 472 + #define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0 473 + #define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000 474 + #define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f 475 + #define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff 476 + #define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0 477 + #define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 478 + #define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f 479 + #define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff 480 + #define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0 481 + #define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000 482 + #define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f 483 + #define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff 484 + #define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0 485 + #define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 486 + #define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f 487 + #define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff 488 + #define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0 489 + #define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000 490 + #define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f 491 + #define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff 492 + #define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0 493 + #define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 494 + #define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f 495 + #define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff 496 + #define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0 497 + #define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 498 + #define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f 499 + #define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff 500 + #define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0 501 + #define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 502 + #define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f 503 + #define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff 504 + #define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0 505 + #define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 506 + #define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f 507 + #define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff 508 + #define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0 509 + #define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1 510 + #define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0 511 + #define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1 512 + #define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0 513 + #define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2 514 + #define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 515 + #define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 516 + #define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 517 + #define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 518 + #define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 519 + #define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 520 + #define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 521 + #define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 522 + #define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 523 + #define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1 524 + #define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0 525 + #define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 526 + #define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 527 + #define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1 528 + #define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0 529 + #define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1 530 + #define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0 531 + #define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff 532 + #define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 533 + #define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff 534 + #define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 535 + #define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff 536 + #define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 537 + #define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff 538 + #define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0 539 + #define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 540 + #define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f 541 + #define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff 542 + #define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0 543 + #define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000 544 + #define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f 545 + #define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff 546 + #define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0 547 + #define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 548 + #define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f 549 + #define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff 550 + #define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0 551 + #define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000 552 + #define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f 553 + #define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff 554 + #define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0 555 + #define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 556 + #define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f 557 + #define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff 558 + #define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0 559 + #define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000 560 + #define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f 561 + #define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff 562 + #define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0 563 + #define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 564 + #define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f 565 + #define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff 566 + #define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0 567 + #define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000 568 + #define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f 569 + #define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff 570 + #define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0 571 + #define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 572 + #define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f 573 + #define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff 574 + #define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0 575 + #define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000 576 + #define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f 577 + #define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff 578 + #define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0 579 + #define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 580 + #define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f 581 + #define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff 582 + #define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0 583 + #define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000 584 + #define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f 585 + #define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff 586 + #define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0 587 + #define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 588 + #define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f 589 + #define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff 590 + #define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0 591 + #define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000 592 + #define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f 593 + #define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff 594 + #define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0 595 + #define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 596 + #define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f 597 + #define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff 598 + #define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0 599 + #define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000 600 + #define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f 601 + #define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff 602 + #define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0 603 + #define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 604 + #define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f 605 + #define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff 606 + #define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0 607 + #define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000 608 + #define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f 609 + #define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff 610 + #define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0 611 + #define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 612 + #define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f 613 + #define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff 614 + #define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0 615 + #define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 616 + #define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f 617 + #define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff 618 + #define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0 619 + #define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 620 + #define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f 621 + #define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff 622 + #define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0 623 + #define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 624 + #define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f 625 + #define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff 626 + #define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0 627 + #define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1 628 + #define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0 629 + #define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1 630 + #define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0 631 + #define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2 632 + #define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 633 + #define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 634 + #define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 635 + #define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 636 + #define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 637 + #define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 638 + #define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 639 + #define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 640 + #define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 641 + #define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1 642 + #define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0 643 + #define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 644 + #define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 645 + #define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1 646 + #define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0 647 + #define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1 648 + #define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0 649 + #define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff 650 + #define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 651 + #define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff 652 + #define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 653 + #define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff 654 + #define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 655 + #define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff 656 + #define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0 657 + #define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 658 + #define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f 659 + #define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff 660 + #define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0 661 + #define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000 662 + #define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f 663 + #define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff 664 + #define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0 665 + #define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 666 + #define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f 667 + #define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff 668 + #define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0 669 + #define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000 670 + #define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f 671 + #define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff 672 + #define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0 673 + #define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 674 + #define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f 675 + #define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff 676 + #define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0 677 + #define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000 678 + #define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f 679 + #define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff 680 + #define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0 681 + #define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 682 + #define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f 683 + #define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff 684 + #define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0 685 + #define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000 686 + #define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f 687 + #define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff 688 + #define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0 689 + #define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 690 + #define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f 691 + #define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff 692 + #define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0 693 + #define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000 694 + #define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f 695 + #define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff 696 + #define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0 697 + #define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 698 + #define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f 699 + #define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff 700 + #define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0 701 + #define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000 702 + #define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f 703 + #define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff 704 + #define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0 705 + #define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 706 + #define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f 707 + #define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff 708 + #define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0 709 + #define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000 710 + #define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f 711 + #define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff 712 + #define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0 713 + #define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 714 + #define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f 715 + #define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff 716 + #define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0 717 + #define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000 718 + #define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f 719 + #define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff 720 + #define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0 721 + #define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 722 + #define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f 723 + #define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff 724 + #define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0 725 + #define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000 726 + #define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f 727 + #define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff 728 + #define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0 729 + #define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 730 + #define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f 731 + #define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff 732 + #define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0 733 + #define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 734 + #define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f 735 + #define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff 736 + #define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0 737 + #define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 738 + #define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f 739 + #define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff 740 + #define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0 741 + #define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 742 + #define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f 743 + #define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff 744 + #define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0 745 + #define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1 746 + #define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0 747 + #define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1 748 + #define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0 749 + #define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2 750 + #define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 751 + #define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 752 + #define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 753 + #define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 754 + #define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 755 + #define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 756 + #define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 757 + #define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 758 + #define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 759 + #define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1 760 + #define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0 761 + #define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 762 + #define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 763 + #define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1 764 + #define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0 765 + #define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1 766 + #define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0 767 + #define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff 768 + #define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 769 + #define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff 770 + #define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 771 + #define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff 772 + #define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 773 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3 774 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 775 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 776 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 777 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 778 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 779 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 780 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 781 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80 782 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 783 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 784 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 785 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 786 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 787 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400 788 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa 789 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 790 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb 791 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000 792 + #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd 793 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 794 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 795 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 796 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a 797 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 798 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d 799 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 800 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e 801 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 802 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f 803 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 804 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 805 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 806 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a 807 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 808 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d 809 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 810 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e 811 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 812 + #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f 813 + #define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 814 + #define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 815 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff 816 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 817 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 818 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f 819 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff 820 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 821 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 822 + #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f 823 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff 824 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 825 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 826 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f 827 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff 828 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 829 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 830 + #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f 831 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3 832 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 833 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 834 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 835 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 836 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 837 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 838 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 839 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80 840 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 841 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 842 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 843 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 844 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 845 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400 846 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa 847 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 848 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb 849 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000 850 + #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd 851 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 852 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 853 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 854 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a 855 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 856 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d 857 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 858 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e 859 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 860 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f 861 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 862 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 863 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 864 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a 865 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 866 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d 867 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 868 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e 869 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 870 + #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f 871 + #define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 872 + #define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 873 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff 874 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 875 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 876 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f 877 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff 878 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 879 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 880 + #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f 881 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff 882 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 883 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 884 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f 885 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff 886 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 887 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 888 + #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f 889 + #define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3 890 + #define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0 891 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff 892 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0 893 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000 894 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d 895 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000 896 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e 897 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000 898 + #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f 899 + #define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3 900 + #define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0 901 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff 902 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0 903 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000 904 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d 905 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000 906 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e 907 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000 908 + #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f 909 + #define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3 910 + #define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0 911 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff 912 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0 913 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000 914 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d 915 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000 916 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e 917 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000 918 + #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f 919 + #define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3 920 + #define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0 921 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff 922 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0 923 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000 924 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d 925 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000 926 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e 927 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000 928 + #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f 929 + #define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3 930 + #define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0 931 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff 932 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0 933 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000 934 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d 935 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000 936 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e 937 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000 938 + #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f 939 + #define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3 940 + #define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0 941 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff 942 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0 943 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000 944 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d 945 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000 946 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e 947 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000 948 + #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f 949 + #define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3 950 + #define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0 951 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff 952 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0 953 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000 954 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d 955 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000 956 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e 957 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000 958 + #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f 959 + #define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3 960 + #define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0 961 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff 962 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0 963 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000 964 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d 965 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000 966 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e 967 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000 968 + #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f 969 + #define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1 970 + #define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0 971 + #define ACP_CONTROL__ClkEn_MASK 0x1 972 + #define ACP_CONTROL__ClkEn__SHIFT 0x0 973 + #define ACP_CONTROL__JtagEn_MASK 0x400 974 + #define ACP_CONTROL__JtagEn__SHIFT 0xa 975 + #define ACP_STATUS__ClkOn_MASK 0x1 976 + #define ACP_STATUS__ClkOn__SHIFT 0x0 977 + #define ACP_STATUS__ACPRefClkSpd_MASK 0x2 978 + #define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1 979 + #define ACP_STATUS__SMUStutterLastEdge_MASK 0x4 980 + #define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2 981 + #define ACP_STATUS__MCStutterLastEdge_MASK 0x8 982 + #define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3 983 + #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 984 + #define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8 985 + #define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 986 + #define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9 987 + #define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000 988 + #define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe 989 + #define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000 990 + #define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf 991 + #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 992 + #define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18 993 + #define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000 994 + #define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19 995 + #define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3 996 + #define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0 997 + #define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff 998 + #define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0 999 + #define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff 1000 + #define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0 1001 + #define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff 1002 + #define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0 1003 + #define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff 1004 + #define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0 1005 + #define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff 1006 + #define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0 1007 + #define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff 1008 + #define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0 1009 + #define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff 1010 + #define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0 1011 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1 1012 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0 1013 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2 1014 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1 1015 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4 1016 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2 1017 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8 1018 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3 1019 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10 1020 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4 1021 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20 1022 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5 1023 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40 1024 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6 1025 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80 1026 + #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7 1027 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100 1028 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8 1029 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 1030 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9 1031 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400 1032 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa 1033 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800 1034 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb 1035 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000 1036 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc 1037 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000 1038 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd 1039 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000 1040 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe 1041 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000 1042 + #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf 1043 + #define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff 1044 + #define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0 1045 + #define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff 1046 + #define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0 1047 + #define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff 1048 + #define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0 1049 + #define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff 1050 + #define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0 1051 + #define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff 1052 + #define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0 1053 + #define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff 1054 + #define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0 1055 + #define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff 1056 + #define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0 1057 + #define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff 1058 + #define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0 1059 + #define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff 1060 + #define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0 1061 + #define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff 1062 + #define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0 1063 + #define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff 1064 + #define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0 1065 + #define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff 1066 + #define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0 1067 + #define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff 1068 + #define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0 1069 + #define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff 1070 + #define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0 1071 + #define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff 1072 + #define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0 1073 + #define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff 1074 + #define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0 1075 + #define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf 1076 + #define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0 1077 + #define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1 1078 + #define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0 1079 + #define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1 1080 + #define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0 1081 + #define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 1082 + #define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 1083 + #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 1084 + #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 1085 + #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 1086 + #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 1087 + #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 1088 + #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 1089 + #define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40 1090 + #define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 1091 + #define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100 1092 + #define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8 1093 + #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 1094 + #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9 1095 + #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400 1096 + #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa 1097 + #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800 1098 + #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb 1099 + #define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 1100 + #define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10 1101 + #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1 1102 + #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0 1103 + #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe 1104 + #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1 1105 + #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10 1106 + #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4 1107 + #define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20 1108 + #define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5 1109 + #define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0 1110 + #define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6 1111 + #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400 1112 + #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa 1113 + #define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800 1114 + #define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb 1115 + #define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000 1116 + #define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc 1117 + #define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000 1118 + #define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd 1119 + #define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000 1120 + #define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe 1121 + #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000 1122 + #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf 1123 + #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000 1124 + #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10 1125 + #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000 1126 + #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13 1127 + #define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000 1128 + #define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14 1129 + #define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000 1130 + #define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15 1131 + #define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000 1132 + #define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19 1133 + #define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000 1134 + #define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a 1135 + #define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000 1136 + #define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c 1137 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1 1138 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0 1139 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2 1140 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1 1141 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4 1142 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2 1143 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x100 1144 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x8 1145 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 1146 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x9 1147 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x400 1148 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa 1149 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x10000 1150 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x10 1151 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x20000 1152 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x11 1153 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x40000 1154 + #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x12 1155 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x1 1156 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x0 1157 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x2 1158 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x1 1159 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x4 1160 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x2 1161 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x100 1162 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x8 1163 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 1164 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x9 1165 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x400 1166 + #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa 1167 + #define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x10000 1168 + #define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x10 1169 + #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x20000 1170 + #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x11 1171 + #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x40000 1172 + #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x12 1173 + #define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff 1174 + #define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x0 1175 + #define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x80000000 1176 + #define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f 1177 + #define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff 1178 + #define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x0 1179 + #define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x80000000 1180 + #define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f 1181 + #define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x1 1182 + #define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x0 1183 + #define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x1 1184 + #define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x0 1185 + #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x2 1186 + #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 1187 + #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x2 1188 + #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 1189 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 1190 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 1191 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 1192 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 1193 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 1194 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 1195 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 1196 + #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 1197 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x10 1198 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 1199 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x10 1200 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 1201 + #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x40 1202 + #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 1203 + #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x40 1204 + #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 1205 + #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x100 1206 + #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x8 1207 + #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x100 1208 + #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x8 1209 + #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 1210 + #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x9 1211 + #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 1212 + #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x9 1213 + #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x400 1214 + #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa 1215 + #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x400 1216 + #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa 1217 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x800 1218 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb 1219 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x800 1220 + #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb 1221 + #define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff0000 1222 + #define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x10 1223 + #define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff0000 1224 + #define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x10 1225 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x1 1226 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x0 1227 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x1 1228 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x0 1229 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x2 1230 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x1 1231 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x2 1232 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x1 1233 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x4 1234 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x2 1235 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x4 1236 + #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x2 1237 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x100 1238 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x8 1239 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x100 1240 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x8 1241 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 1242 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x9 1243 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x200 1244 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x9 1245 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x400 1246 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa 1247 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x400 1248 + #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa 1249 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x10000 1250 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x10 1251 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x10000 1252 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x10 1253 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x20000 1254 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x11 1255 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x20000 1256 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x11 1257 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x40000 1258 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x12 1259 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x40000 1260 + #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x12 1261 + #define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x1 1262 + #define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x0 1263 + #define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 1264 + #define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 1265 + #define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 1266 + #define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 1267 + #define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 1268 + #define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 1269 + #define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 1270 + #define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 1271 + #define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x40 1272 + #define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 1273 + #define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 1274 + #define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 1275 + #define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 1276 + #define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 1277 + #define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x400 1278 + #define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa 1279 + #define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x800 1280 + #define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb 1281 + #define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x1000 1282 + #define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc 1283 + #define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 1284 + #define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd 1285 + #define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 1286 + #define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x10 1287 + #define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x1 1288 + #define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x0 1289 + #define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x1 1290 + #define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x0 1291 + #define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x2 1292 + #define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 1293 + #define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x2 1294 + #define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 1295 + #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 1296 + #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 1297 + #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 1298 + #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 1299 + #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 1300 + #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 1301 + #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 1302 + #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 1303 + #define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x10 1304 + #define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 1305 + #define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x10 1306 + #define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 1307 + #define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x40 1308 + #define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 1309 + #define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x40 1310 + #define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 1311 + #define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 1312 + #define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 1313 + #define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 1314 + #define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 1315 + #define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x200 1316 + #define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 1317 + #define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x200 1318 + #define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 1319 + #define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x400 1320 + #define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa 1321 + #define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x400 1322 + #define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa 1323 + #define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x800 1324 + #define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb 1325 + #define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x800 1326 + #define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb 1327 + #define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x1000 1328 + #define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc 1329 + #define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x1000 1330 + #define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc 1331 + #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 1332 + #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd 1333 + #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 1334 + #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd 1335 + #define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff0000 1336 + #define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x10 1337 + #define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff0000 1338 + #define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x10 1339 + #define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff 1340 + #define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x0 1341 + #define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x80000000 1342 + #define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f 1343 + #define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x1 1344 + #define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x0 1345 + #define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 1346 + #define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 1347 + #define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 1348 + #define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 1349 + #define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 1350 + #define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 1351 + #define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 1352 + #define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 1353 + #define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x40 1354 + #define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 1355 + #define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 1356 + #define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 1357 + #define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 1358 + #define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 1359 + #define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x400 1360 + #define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa 1361 + #define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x800 1362 + #define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb 1363 + #define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x1000 1364 + #define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc 1365 + #define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 1366 + #define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd 1367 + #define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 1368 + #define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x10 1369 + #define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x1 1370 + #define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x0 1371 + #define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x1 1372 + #define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x0 1373 + #define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x2 1374 + #define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 1375 + #define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x2 1376 + #define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 1377 + #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 1378 + #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 1379 + #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 1380 + #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 1381 + #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 1382 + #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 1383 + #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 1384 + #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 1385 + #define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x10 1386 + #define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 1387 + #define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x10 1388 + #define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 1389 + #define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x40 1390 + #define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 1391 + #define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x40 1392 + #define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 1393 + #define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 1394 + #define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 1395 + #define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 1396 + #define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 1397 + #define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x200 1398 + #define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 1399 + #define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x200 1400 + #define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 1401 + #define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x400 1402 + #define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa 1403 + #define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x400 1404 + #define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa 1405 + #define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x800 1406 + #define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb 1407 + #define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x800 1408 + #define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb 1409 + #define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x1000 1410 + #define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc 1411 + #define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x1000 1412 + #define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc 1413 + #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 1414 + #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd 1415 + #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 1416 + #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd 1417 + #define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff0000 1418 + #define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x10 1419 + #define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff0000 1420 + #define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x10 1421 + #define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff 1422 + #define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x0 1423 + #define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x80000000 1424 + #define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f 1425 + #define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x1 1426 + #define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x0 1427 + #define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 1428 + #define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 1429 + #define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 1430 + #define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 1431 + #define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 1432 + #define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 1433 + #define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 1434 + #define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 1435 + #define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x40 1436 + #define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 1437 + #define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 1438 + #define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 1439 + #define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 1440 + #define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 1441 + #define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x400 1442 + #define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa 1443 + #define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x800 1444 + #define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb 1445 + #define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x1000 1446 + #define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc 1447 + #define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 1448 + #define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd 1449 + #define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 1450 + #define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x10 1451 + #define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x1 1452 + #define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x0 1453 + #define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x1 1454 + #define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x0 1455 + #define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x2 1456 + #define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 1457 + #define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x2 1458 + #define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 1459 + #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 1460 + #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 1461 + #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 1462 + #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 1463 + #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 1464 + #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 1465 + #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 1466 + #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 1467 + #define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x10 1468 + #define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 1469 + #define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x10 1470 + #define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 1471 + #define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x40 1472 + #define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 1473 + #define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x40 1474 + #define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 1475 + #define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 1476 + #define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 1477 + #define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 1478 + #define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 1479 + #define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x200 1480 + #define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 1481 + #define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x200 1482 + #define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 1483 + #define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x400 1484 + #define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa 1485 + #define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x400 1486 + #define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa 1487 + #define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x800 1488 + #define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb 1489 + #define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x800 1490 + #define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb 1491 + #define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x1000 1492 + #define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc 1493 + #define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x1000 1494 + #define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc 1495 + #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 1496 + #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd 1497 + #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 1498 + #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd 1499 + #define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff0000 1500 + #define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x10 1501 + #define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff0000 1502 + #define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x10 1503 + #define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff 1504 + #define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x0 1505 + #define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x80000000 1506 + #define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f 1507 + #define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff 1508 + #define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 1509 + #define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 1510 + #define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e 1511 + #define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff 1512 + #define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 1513 + #define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 1514 + #define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e 1515 + #define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff 1516 + #define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 1517 + #define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 1518 + #define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e 1519 + #define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x1 1520 + #define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x0 1521 + #define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x1 1522 + #define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x0 1523 + #define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x1 1524 + #define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x0 1525 + #define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x1 1526 + #define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x0 1527 + #define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x1 1528 + #define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x0 1529 + #define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x1 1530 + #define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x0 1531 + #define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x1 1532 + #define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x0 1533 + #define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x1 1534 + #define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x0 1535 + #define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x1 1536 + #define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x0 1537 + #define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x1 1538 + #define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x0 1539 + #define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x1 1540 + #define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x0 1541 + #define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x1 1542 + #define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x0 1543 + #define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x1 1544 + #define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x0 1545 + #define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x1 1546 + #define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x0 1547 + #define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x1 1548 + #define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x0 1549 + #define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x1 1550 + #define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x0 1551 + #define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x1 1552 + #define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x0 1553 + #define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x1 1554 + #define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x0 1555 + #define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x1 1556 + #define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x0 1557 + #define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x1 1558 + #define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x0 1559 + #define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x1 1560 + #define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x0 1561 + #define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x1 1562 + #define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x0 1563 + #define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x1 1564 + #define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x0 1565 + #define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x1 1566 + #define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x0 1567 + #define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x1 1568 + #define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x0 1569 + #define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x1 1570 + #define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x0 1571 + #define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x1 1572 + #define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x0 1573 + #define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x1 1574 + #define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x0 1575 + #define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x1 1576 + #define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x0 1577 + #define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x1 1578 + #define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x0 1579 + #define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x1 1580 + #define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x0 1581 + #define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x1 1582 + #define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x0 1583 + #define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x1 1584 + #define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x0 1585 + #define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x1 1586 + #define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x0 1587 + #define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x1 1588 + #define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x0 1589 + #define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x1 1590 + #define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x0 1591 + #define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x1 1592 + #define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x0 1593 + #define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x1 1594 + #define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x0 1595 + #define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x1 1596 + #define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x0 1597 + #define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x1 1598 + #define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x0 1599 + #define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x1 1600 + #define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x0 1601 + #define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x1 1602 + #define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x0 1603 + #define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x1 1604 + #define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x0 1605 + #define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x1 1606 + #define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x0 1607 + #define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x1 1608 + #define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x0 1609 + #define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x1 1610 + #define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x0 1611 + #define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x1 1612 + #define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x0 1613 + #define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x1 1614 + #define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x0 1615 + #define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff 1616 + #define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x0 1617 + #define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff 1618 + #define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x0 1619 + #define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x1 1620 + #define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x0 1621 + #define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff 1622 + #define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x0 1623 + #define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff 1624 + #define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x0 1625 + #define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f 1626 + #define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x0 1627 + #define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff 1628 + #define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x0 1629 + #define ACP_SEMA_CMD__REQ_CMD_MASK 0xf 1630 + #define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x0 1631 + #define ACP_SEMA_CMD__WR_PHASE_MASK 0x30 1632 + #define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x4 1633 + #define ACP_SEMA_CMD__VMID_EN_MASK 0x80 1634 + #define ACP_SEMA_CMD__VMID_EN__SHIFT 0x7 1635 + #define ACP_SEMA_CMD__VMID_MASK 0xf00 1636 + #define ACP_SEMA_CMD__VMID__SHIFT 0x8 1637 + #define ACP_SEMA_CMD__ATC_MASK 0x1000 1638 + #define ACP_SEMA_CMD__ATC__SHIFT 0xc 1639 + #define ACP_SEMA_STS__REQ_STS_MASK 0x3 1640 + #define ACP_SEMA_STS__REQ_STS__SHIFT 0x0 1641 + #define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x100 1642 + #define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x8 1643 + #define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x1 1644 + #define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x0 1645 + #define ACP_FW_STATUS__RUN_MASK 0x1 1646 + #define ACP_FW_STATUS__RUN__SHIFT 0x0 1647 + #define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff 1648 + #define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x0 1649 + #define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff 1650 + #define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x0 1651 + #define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff 1652 + #define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x0 1653 + #define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff 1654 + #define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x0 1655 + #define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff 1656 + #define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x0 1657 + #define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff 1658 + #define ACP_TIMER__ACP_Timer_count__SHIFT 0x0 1659 + #define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x1 1660 + #define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x0 1661 + #define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff 1662 + #define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x0 1663 + #define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff 1664 + #define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x0 1665 + #define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff 1666 + #define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x0 1667 + #define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff 1668 + #define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x0 1669 + #define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff 1670 + #define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x0 1671 + #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff 1672 + #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x0 1673 + #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff 1674 + #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x0 1675 + #define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff 1676 + #define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x0 1677 + #define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff 1678 + #define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x0 1679 + #define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x1 1680 + #define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x0 1681 + #define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x1 1682 + #define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x0 1683 + #define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x1 1684 + #define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x0 1685 + #define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff 1686 + #define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x0 1687 + #define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x2 1688 + #define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x1 1689 + #define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x4 1690 + #define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x2 1691 + #define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x8 1692 + #define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x3 1693 + #define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x10 1694 + #define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x4 1695 + #define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x1 1696 + #define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x0 1697 + #define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x2 1698 + #define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x1 1699 + #define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x4 1700 + #define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x2 1701 + #define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x8 1702 + #define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x3 1703 + #define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x10 1704 + #define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x4 1705 + #define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x20 1706 + #define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x5 1707 + #define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff 1708 + #define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x0 1709 + #define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x100 1710 + #define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x8 1711 + #define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x200 1712 + #define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x9 1713 + #define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x400 1714 + #define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa 1715 + #define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x800 1716 + #define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb 1717 + #define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x1000 1718 + #define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc 1719 + #define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x2000 1720 + #define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd 1721 + #define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x4000 1722 + #define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe 1723 + #define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x8000 1724 + #define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf 1725 + #define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff0000 1726 + #define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x10 1727 + #define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x4000000 1728 + #define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a 1729 + #define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x8000000 1730 + #define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b 1731 + #define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf0000000 1732 + #define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c 1733 + #define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff 1734 + #define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x0 1735 + #define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff 1736 + #define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x0 1737 + #define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff 1738 + #define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x0 1739 + #define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff 1740 + #define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x0 1741 + #define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff 1742 + #define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x0 1743 + #define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff 1744 + #define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x0 1745 + #define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff 1746 + #define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x0 1747 + #define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x1 1748 + #define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x0 1749 + #define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x3 1750 + #define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x0 1751 + #define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x1 1752 + #define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x0 1753 + #define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x1 1754 + #define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x0 1755 + #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff 1756 + #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x0 1757 + #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff0000 1758 + #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x10 1759 + #define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x1 1760 + #define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x0 1761 + #define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff 1762 + #define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x0 1763 + #define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff 1764 + #define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x0 1765 + #define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff 1766 + #define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x0 1767 + #define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff 1768 + #define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x0 1769 + #define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff 1770 + #define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x0 1771 + #define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff 1772 + #define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x0 1773 + #define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff 1774 + #define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x0 1775 + #define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff 1776 + #define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x0 1777 + #define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff 1778 + #define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x0 1779 + #define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff 1780 + #define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x0 1781 + #define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff 1782 + #define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x0 1783 + #define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff 1784 + #define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x0 1785 + #define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff 1786 + #define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x0 1787 + #define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff 1788 + #define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x0 1789 + #define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff 1790 + #define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x0 1791 + #define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff 1792 + #define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x0 1793 + #define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff 1794 + #define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x0 1795 + #define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff 1796 + #define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x0 1797 + #define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff 1798 + #define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x0 1799 + #define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff 1800 + #define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x0 1801 + #define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff 1802 + #define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x0 1803 + #define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff 1804 + #define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x0 1805 + #define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff 1806 + #define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x0 1807 + #define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff 1808 + #define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x0 1809 + #define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff 1810 + #define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x0 1811 + #define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff 1812 + #define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x0 1813 + #define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff 1814 + #define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x0 1815 + #define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff 1816 + #define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x0 1817 + #define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff 1818 + #define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x0 1819 + #define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff 1820 + #define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x0 1821 + #define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff 1822 + #define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x0 1823 + #define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff 1824 + #define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x0 1825 + #define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff 1826 + #define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x0 1827 + #define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff 1828 + #define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x0 1829 + #define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff 1830 + #define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x0 1831 + #define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff 1832 + #define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x0 1833 + #define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff 1834 + #define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x0 1835 + #define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff 1836 + #define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x0 1837 + #define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff 1838 + #define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x0 1839 + #define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff 1840 + #define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x0 1841 + #define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff 1842 + #define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x0 1843 + #define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff 1844 + #define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x0 1845 + #define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff 1846 + #define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x0 1847 + #define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff 1848 + #define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x0 1849 + #define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff 1850 + #define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x0 1851 + #define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff 1852 + #define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x0 1853 + #define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff 1854 + #define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x0 1855 + #define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff 1856 + #define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x0 1857 + #define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x1 1858 + #define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x0 1859 + #define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x1 1860 + #define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x0 1861 + #define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff 1862 + #define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x0 1863 + #define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff 1864 + #define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x0 1865 + #define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff 1866 + #define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x0 1867 + #define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff 1868 + #define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x0 1869 + #define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff 1870 + #define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x0 1871 + #define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x1 1872 + #define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x0 1873 + #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x1 1874 + #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x0 1875 + #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x2 1876 + #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x1 1877 + #define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff 1878 + #define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x0 1879 + #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x1 1880 + #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x0 1881 + #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x2 1882 + #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x1 1883 + #define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x1 1884 + #define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x0 1885 + #define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff 1886 + #define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x0 1887 + #define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff 1888 + #define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x0 1889 + #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff 1890 + #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x0 1891 + #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff 1892 + #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x0 1893 + #define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff 1894 + #define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x0 1895 + #define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff 1896 + #define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x0 1897 + #define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff 1898 + #define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x0 1899 + #define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff 1900 + #define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x0 1901 + #define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff 1902 + #define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x0 1903 + #define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff 1904 + #define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x0 1905 + #define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff 1906 + #define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x0 1907 + #define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff 1908 + #define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x0 1909 + #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff 1910 + #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x0 1911 + #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff 1912 + #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x0 1913 + #define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff 1914 + #define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x0 1915 + #define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff 1916 + #define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x0 1917 + #define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x1 1918 + #define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x0 1919 + #define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x1 1920 + #define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x0 1921 + #define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x1 1922 + #define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x0 1923 + #define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x1 1924 + #define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x0 1925 + #define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x7 1926 + #define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x0 1927 + #define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x18 1928 + #define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x3 1929 + #define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x1 1930 + #define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x0 1931 + #define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x1 1932 + #define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x0 1933 + #define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff 1934 + #define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x0 1935 + #define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff 1936 + #define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x0 1937 + #define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x1 1938 + #define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x0 1939 + #define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x1 1940 + #define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x0 1941 + #define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x7 1942 + #define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x0 1943 + #define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x7 1944 + #define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x0 1945 + #define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x1 1946 + #define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x0 1947 + #define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x2 1948 + #define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x1 1949 + #define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x10 1950 + #define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x4 1951 + #define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x20 1952 + #define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x5 1953 + #define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x1 1954 + #define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x0 1955 + #define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x2 1956 + #define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x1 1957 + #define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x10 1958 + #define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x4 1959 + #define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x20 1960 + #define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x5 1961 + #define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x1 1962 + #define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x0 1963 + #define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x1 1964 + #define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x0 1965 + #define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf 1966 + #define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x0 1967 + #define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf 1968 + #define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x0 1969 + #define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x1 1970 + #define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x0 1971 + #define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x1 1972 + #define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x0 1973 + #define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff 1974 + #define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x0 1975 + #define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x1 1976 + #define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x0 1977 + #define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff 1978 + #define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x0 1979 + #define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x1 1980 + #define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x0 1981 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x7 1982 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x0 1983 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x38 1984 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x3 1985 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x380 1986 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x7 1987 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c00 1988 + #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa 1989 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x3 1990 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 1991 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc 1992 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 1993 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x10 1994 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x4 1995 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x20 1996 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x5 1997 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x40 1998 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x6 1999 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x180 2000 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x7 2001 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x600 2002 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x9 2003 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x70000 2004 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x10 2005 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x380000 2006 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x13 2007 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c00000 2008 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x16 2009 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe000000 2010 + #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x19 2011 + #define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff 2012 + #define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 2013 + #define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff 2014 + #define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x0 2015 + #define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x1 2016 + #define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x0 2017 + #define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x1 2018 + #define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x0 2019 + #define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x1 2020 + #define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x0 2021 + #define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x1 2022 + #define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x0 2023 + #define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x7 2024 + #define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x0 2025 + #define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x18 2026 + #define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x3 2027 + #define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x1 2028 + #define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x0 2029 + #define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x1 2030 + #define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x0 2031 + #define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff 2032 + #define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x0 2033 + #define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff 2034 + #define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x0 2035 + #define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x1 2036 + #define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x0 2037 + #define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x1 2038 + #define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x0 2039 + #define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x7 2040 + #define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x0 2041 + #define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x7 2042 + #define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x0 2043 + #define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x1 2044 + #define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x0 2045 + #define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x2 2046 + #define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x1 2047 + #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x10 2048 + #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x4 2049 + #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x20 2050 + #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x5 2051 + #define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x1 2052 + #define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x0 2053 + #define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x2 2054 + #define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x1 2055 + #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x10 2056 + #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x4 2057 + #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x20 2058 + #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x5 2059 + #define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x1 2060 + #define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x0 2061 + #define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x1 2062 + #define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x0 2063 + #define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf 2064 + #define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x0 2065 + #define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf 2066 + #define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x0 2067 + #define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x1 2068 + #define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x0 2069 + #define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x1 2070 + #define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x0 2071 + #define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff 2072 + #define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x0 2073 + #define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff 2074 + #define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x0 2075 + #define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x1 2076 + #define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x0 2077 + #define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x1 2078 + #define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x0 2079 + #define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x7 2080 + #define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x0 2081 + #define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x7 2082 + #define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x0 2083 + #define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x1 2084 + #define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x0 2085 + #define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x2 2086 + #define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x1 2087 + #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x10 2088 + #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x4 2089 + #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x20 2090 + #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x5 2091 + #define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x1 2092 + #define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x0 2093 + #define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x2 2094 + #define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x1 2095 + #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x10 2096 + #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x4 2097 + #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x20 2098 + #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x5 2099 + #define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x1 2100 + #define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x0 2101 + #define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x1 2102 + #define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x0 2103 + #define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf 2104 + #define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x0 2105 + #define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf 2106 + #define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x0 2107 + #define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x1 2108 + #define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x0 2109 + #define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x1 2110 + #define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x0 2111 + #define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff 2112 + #define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x0 2113 + #define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x1 2114 + #define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x0 2115 + #define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff 2116 + #define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x0 2117 + #define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x1 2118 + #define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x0 2119 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x7 2120 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x0 2121 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x38 2122 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x3 2123 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x380 2124 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x7 2125 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c00 2126 + #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa 2127 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x3 2128 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 2129 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc 2130 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 2131 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x10 2132 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x4 2133 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x20 2134 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x5 2135 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x40 2136 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x6 2137 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x180 2138 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x7 2139 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x600 2140 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x9 2141 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x70000 2142 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x10 2143 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x380000 2144 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x13 2145 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c00000 2146 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x16 2147 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe000000 2148 + #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x19 2149 + #define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff 2150 + #define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 2151 + #define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff 2152 + #define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x0 2153 + #define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x1 2154 + #define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x0 2155 + #define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x1 2156 + #define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x0 2157 + #define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x1 2158 + #define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x0 2159 + #define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x1 2160 + #define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x0 2161 + #define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x7 2162 + #define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x0 2163 + #define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x18 2164 + #define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x3 2165 + #define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x1 2166 + #define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x0 2167 + #define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x1 2168 + #define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x0 2169 + #define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff 2170 + #define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x0 2171 + #define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff 2172 + #define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x0 2173 + #define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x1 2174 + #define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x0 2175 + #define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x1 2176 + #define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x0 2177 + #define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x7 2178 + #define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x0 2179 + #define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x7 2180 + #define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x0 2181 + #define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x1 2182 + #define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x0 2183 + #define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x2 2184 + #define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x1 2185 + #define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x10 2186 + #define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x4 2187 + #define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x20 2188 + #define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x5 2189 + #define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x1 2190 + #define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x0 2191 + #define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x2 2192 + #define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x1 2193 + #define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x10 2194 + #define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x4 2195 + #define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x20 2196 + #define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x5 2197 + #define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x1 2198 + #define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x0 2199 + #define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x1 2200 + #define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x0 2201 + #define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf 2202 + #define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x0 2203 + #define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf 2204 + #define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x0 2205 + #define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x1 2206 + #define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x0 2207 + #define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x1 2208 + #define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x0 2209 + #define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff 2210 + #define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x0 2211 + #define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff 2212 + #define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x0 2213 + #define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x1 2214 + #define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x0 2215 + #define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x1 2216 + #define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x0 2217 + #define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x7 2218 + #define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x0 2219 + #define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x7 2220 + #define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x0 2221 + #define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x1 2222 + #define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x0 2223 + #define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x2 2224 + #define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x1 2225 + #define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x10 2226 + #define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x4 2227 + #define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x20 2228 + #define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x5 2229 + #define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x1 2230 + #define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x0 2231 + #define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x2 2232 + #define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x1 2233 + #define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x10 2234 + #define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x4 2235 + #define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x20 2236 + #define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x5 2237 + #define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x1 2238 + #define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x0 2239 + #define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x1 2240 + #define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x0 2241 + #define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf 2242 + #define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x0 2243 + #define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf 2244 + #define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x0 2245 + #define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x1 2246 + #define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x0 2247 + #define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x1 2248 + #define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x0 2249 + #define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff 2250 + #define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x0 2251 + #define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x1 2252 + #define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x0 2253 + #define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff 2254 + #define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x0 2255 + #define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x1 2256 + #define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x0 2257 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x7 2258 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x0 2259 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x38 2260 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x3 2261 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x380 2262 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x7 2263 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c00 2264 + #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa 2265 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x3 2266 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 2267 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc 2268 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x2 2269 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x10 2270 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x4 2271 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x20 2272 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x5 2273 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x40 2274 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x6 2275 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x180 2276 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x7 2277 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x600 2278 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x9 2279 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x70000 2280 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x10 2281 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x380000 2282 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x13 2283 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c00000 2284 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x16 2285 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe000000 2286 + #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x19 2287 + #define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff 2288 + #define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 2289 + #define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff 2290 + #define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x0 2291 + 2292 + #endif /* ACP_2_2_SH_MASK_H */