dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add the dt-bindings header for Nuvoton ma35d1, that gets shared
between the clock controller and clock references in the dts.
Add documentation to describe nuvoton ma35d1 clock driver.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

Jacky Huang and committed by

Arnd Bergmann 2 years ago 2f8b5eb5 4cc22724

+316

2 changed files

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Documentation

devicetree

bindings

clock

nuvoton,ma35d1-clk.yaml

include

dt-bindings

clock

nuvoton,ma35d1-clk.h

+63

Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Nuvoton MA35D1 Clock Controller Module 8 + 9 + maintainers: 10 + - Chi-Fang Li <cfli0@nuvoton.com> 11 + - Jacky Huang <ychuang3@nuvoton.com> 12 + 13 + description: | 14 + The MA35D1 clock controller generates clocks for the whole chip, 15 + including system clocks and all peripheral clocks. 16 + 17 + See also: 18 + include/dt-bindings/clock/ma35d1-clk.h 19 + 20 + properties: 21 + compatible: 22 + items: 23 + - const: nuvoton,ma35d1-clk 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + "#clock-cells": 29 + const: 1 30 + 31 + clocks: 32 + maxItems: 1 33 + 34 + nuvoton,pll-mode: 35 + description: 36 + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, 37 + EPLL, and VPLL in sequential. 38 + maxItems: 5 39 + items: 40 + enum: 41 + - integer 42 + - fractional 43 + - spread-spectrum 44 + $ref: /schemas/types.yaml#/definitions/non-unique-string-array 45 + 46 + required: 47 + - compatible 48 + - reg 49 + - "#clock-cells" 50 + - clocks 51 + 52 + additionalProperties: false 53 + 54 + examples: 55 + - | 56 + 57 + clock-controller@40460200 { 58 + compatible = "nuvoton,ma35d1-clk"; 59 + reg = <0x40460200 0x100>; 60 + #clock-cells = <1>; 61 + clocks = <&clk_hxt>; 62 + }; 63 + ...

+253

include/dt-bindings/clock/nuvoton,ma35d1-clk.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2023 Nuvoton Technologies. 4 + */ 5 + 6 + #ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H 7 + #define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H 8 + 9 + /* external and internal oscillator clocks */ 10 + #define HXT 0 11 + #define HXT_GATE 1 12 + #define LXT 2 13 + #define LXT_GATE 3 14 + #define HIRC 4 15 + #define HIRC_GATE 5 16 + #define LIRC 6 17 + #define LIRC_GATE 7 18 + /* PLLs */ 19 + #define CAPLL 8 20 + #define SYSPLL 9 21 + #define DDRPLL 10 22 + #define APLL 11 23 + #define EPLL 12 24 + #define VPLL 13 25 + /* EPLL divider */ 26 + #define EPLL_DIV2 14 27 + #define EPLL_DIV4 15 28 + #define EPLL_DIV8 16 29 + /* CPU clock, system clock, AXI, HCLK and PCLK */ 30 + #define CA35CLK_MUX 17 31 + #define AXICLK_DIV2 18 32 + #define AXICLK_DIV4 19 33 + #define AXICLK_MUX 20 34 + #define SYSCLK0_MUX 21 35 + #define SYSCLK1_MUX 22 36 + #define SYSCLK1_DIV2 23 37 + #define HCLK0 24 38 + #define HCLK1 25 39 + #define HCLK2 26 40 + #define PCLK0 27 41 + #define PCLK1 28 42 + #define PCLK2 29 43 + #define HCLK3 30 44 + #define PCLK3 31 45 + #define PCLK4 32 46 + /* AXI and AHB peripheral clocks */ 47 + #define USBPHY0 33 48 + #define USBPHY1 34 49 + #define DDR0_GATE 35 50 + #define DDR6_GATE 36 51 + #define CAN0_MUX 37 52 + #define CAN0_DIV 38 53 + #define CAN0_GATE 39 54 + #define CAN1_MUX 40 55 + #define CAN1_DIV 41 56 + #define CAN1_GATE 42 57 + #define CAN2_MUX 43 58 + #define CAN2_DIV 44 59 + #define CAN2_GATE 45 60 + #define CAN3_MUX 46 61 + #define CAN3_DIV 47 62 + #define CAN3_GATE 48 63 + #define SDH0_MUX 49 64 + #define SDH0_GATE 50 65 + #define SDH1_MUX 51 66 + #define SDH1_GATE 52 67 + #define NAND_GATE 53 68 + #define USBD_GATE 54 69 + #define USBH_GATE 55 70 + #define HUSBH0_GATE 56 71 + #define HUSBH1_GATE 57 72 + #define GFX_MUX 58 73 + #define GFX_GATE 59 74 + #define VC8K_GATE 60 75 + #define DCU_MUX 61 76 + #define DCU_GATE 62 77 + #define DCUP_DIV 63 78 + #define EMAC0_GATE 64 79 + #define EMAC1_GATE 65 80 + #define CCAP0_MUX 66 81 + #define CCAP0_DIV 67 82 + #define CCAP0_GATE 68 83 + #define CCAP1_MUX 69 84 + #define CCAP1_DIV 70 85 + #define CCAP1_GATE 71 86 + #define PDMA0_GATE 72 87 + #define PDMA1_GATE 73 88 + #define PDMA2_GATE 74 89 + #define PDMA3_GATE 75 90 + #define WH0_GATE 76 91 + #define WH1_GATE 77 92 + #define HWS_GATE 78 93 + #define EBI_GATE 79 94 + #define SRAM0_GATE 80 95 + #define SRAM1_GATE 81 96 + #define ROM_GATE 82 97 + #define TRA_GATE 83 98 + #define DBG_MUX 84 99 + #define DBG_GATE 85 100 + #define CKO_MUX 86 101 + #define CKO_DIV 87 102 + #define CKO_GATE 88 103 + #define GTMR_GATE 89 104 + #define GPA_GATE 90 105 + #define GPB_GATE 91 106 + #define GPC_GATE 92 107 + #define GPD_GATE 93 108 + #define GPE_GATE 94 109 + #define GPF_GATE 95 110 + #define GPG_GATE 96 111 + #define GPH_GATE 97 112 + #define GPI_GATE 98 113 + #define GPJ_GATE 99 114 + #define GPK_GATE 100 115 + #define GPL_GATE 101 116 + #define GPM_GATE 102 117 + #define GPN_GATE 103 118 + /* APB peripheral clocks */ 119 + #define TMR0_MUX 104 120 + #define TMR0_GATE 105 121 + #define TMR1_MUX 106 122 + #define TMR1_GATE 107 123 + #define TMR2_MUX 108 124 + #define TMR2_GATE 109 125 + #define TMR3_MUX 110 126 + #define TMR3_GATE 111 127 + #define TMR4_MUX 112 128 + #define TMR4_GATE 113 129 + #define TMR5_MUX 114 130 + #define TMR5_GATE 115 131 + #define TMR6_MUX 116 132 + #define TMR6_GATE 117 133 + #define TMR7_MUX 118 134 + #define TMR7_GATE 119 135 + #define TMR8_MUX 120 136 + #define TMR8_GATE 121 137 + #define TMR9_MUX 122 138 + #define TMR9_GATE 123 139 + #define TMR10_MUX 124 140 + #define TMR10_GATE 125 141 + #define TMR11_MUX 126 142 + #define TMR11_GATE 127 143 + #define UART0_MUX 128 144 + #define UART0_DIV 129 145 + #define UART0_GATE 130 146 + #define UART1_MUX 131 147 + #define UART1_DIV 132 148 + #define UART1_GATE 133 149 + #define UART2_MUX 134 150 + #define UART2_DIV 135 151 + #define UART2_GATE 136 152 + #define UART3_MUX 137 153 + #define UART3_DIV 138 154 + #define UART3_GATE 139 155 + #define UART4_MUX 140 156 + #define UART4_DIV 141 157 + #define UART4_GATE 142 158 + #define UART5_MUX 143 159 + #define UART5_DIV 144 160 + #define UART5_GATE 145 161 + #define UART6_MUX 146 162 + #define UART6_DIV 147 163 + #define UART6_GATE 148 164 + #define UART7_MUX 149 165 + #define UART7_DIV 150 166 + #define UART7_GATE 151 167 + #define UART8_MUX 152 168 + #define UART8_DIV 153 169 + #define UART8_GATE 154 170 + #define UART9_MUX 155 171 + #define UART9_DIV 156 172 + #define UART9_GATE 157 173 + #define UART10_MUX 158 174 + #define UART10_DIV 159 175 + #define UART10_GATE 160 176 + #define UART11_MUX 161 177 + #define UART11_DIV 162 178 + #define UART11_GATE 163 179 + #define UART12_MUX 164 180 + #define UART12_DIV 165 181 + #define UART12_GATE 166 182 + #define UART13_MUX 167 183 + #define UART13_DIV 168 184 + #define UART13_GATE 169 185 + #define UART14_MUX 170 186 + #define UART14_DIV 171 187 + #define UART14_GATE 172 188 + #define UART15_MUX 173 189 + #define UART15_DIV 174 190 + #define UART15_GATE 175 191 + #define UART16_MUX 176 192 + #define UART16_DIV 177 193 + #define UART16_GATE 178 194 + #define RTC_GATE 179 195 + #define DDR_GATE 180 196 + #define KPI_MUX 181 197 + #define KPI_DIV 182 198 + #define KPI_GATE 183 199 + #define I2C0_GATE 184 200 + #define I2C1_GATE 185 201 + #define I2C2_GATE 186 202 + #define I2C3_GATE 187 203 + #define I2C4_GATE 188 204 + #define I2C5_GATE 189 205 + #define QSPI0_MUX 190 206 + #define QSPI0_GATE 191 207 + #define QSPI1_MUX 192 208 + #define QSPI1_GATE 193 209 + #define SMC0_MUX 194 210 + #define SMC0_DIV 195 211 + #define SMC0_GATE 196 212 + #define SMC1_MUX 197 213 + #define SMC1_DIV 198 214 + #define SMC1_GATE 199 215 + #define WDT0_MUX 200 216 + #define WDT0_GATE 201 217 + #define WDT1_MUX 202 218 + #define WDT1_GATE 203 219 + #define WDT2_MUX 204 220 + #define WDT2_GATE 205 221 + #define WWDT0_MUX 206 222 + #define WWDT1_MUX 207 223 + #define WWDT2_MUX 208 224 + #define EPWM0_GATE 209 225 + #define EPWM1_GATE 210 226 + #define EPWM2_GATE 211 227 + #define I2S0_MUX 212 228 + #define I2S0_GATE 213 229 + #define I2S1_MUX 214 230 + #define I2S1_GATE 215 231 + #define SSMCC_GATE 216 232 + #define SSPCC_GATE 217 233 + #define SPI0_MUX 218 234 + #define SPI0_GATE 219 235 + #define SPI1_MUX 220 236 + #define SPI1_GATE 221 237 + #define SPI2_MUX 222 238 + #define SPI2_GATE 223 239 + #define SPI3_MUX 224 240 + #define SPI3_GATE 225 241 + #define ECAP0_GATE 226 242 + #define ECAP1_GATE 227 243 + #define ECAP2_GATE 228 244 + #define QEI0_GATE 229 245 + #define QEI1_GATE 230 246 + #define QEI2_GATE 231 247 + #define ADC_DIV 232 248 + #define ADC_GATE 233 249 + #define EADC_DIV 234 250 + #define EADC_GATE 235 251 + #define CLK_MAX_IDX 236 252 + 253 + #endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */