tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd: Expose the FRU SMU I2C bus

Expose both SMU I2C buses. Some boards use the same bus for both the RAS
and FRU EEPROMs and others use different buses. This enables the
additional I2C bus and sets the right buses to use for RAS and FRU EEPROM
access.

Cc: Roy Sun <Roy.Sun@amd.com>
Co-developed-by: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Luben Tuikov and committed by
Alex Deucher 2f60dd50 f06d9e4e

+272 -114
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
··· 75 75 { 76 76 int ret, size; 77 77 78 - ret = amdgpu_eeprom_read(&adev->pm.smu_i2c, addrptr, buff, 1); 78 + ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr, buff, 1); 79 79 if (ret < 1) { 80 80 DRM_WARN("FRU: Failed to get size field"); 81 81 return ret; ··· 86 86 */ 87 87 size = buff[0] - I2C_PRODUCT_INFO_OFFSET; 88 88 89 - ret = amdgpu_eeprom_read(&adev->pm.smu_i2c, addrptr + 1, buff, size); 89 + ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr + 1, buff, size); 90 90 if (ret < 1) { 91 91 DRM_WARN("FRU: Failed to get data field"); 92 92 return ret; ··· 109 109 offset = 0; 110 110 111 111 /* If algo exists, it means that the i2c_adapter's initialized */ 112 - if (!adev->pm.smu_i2c.algo) { 112 + if (!adev->pm.fru_eeprom_i2c_bus || !adev->pm.fru_eeprom_i2c_bus->algo) { 113 113 DRM_WARN("Cannot access FRU, EEPROM accessor not initialized"); 114 114 return -ENODEV; 115 115 }
+7 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
··· 194 194 195 195 /* i2c may be unstable in gpu reset */ 196 196 down_read(&adev->reset_sem); 197 - res = amdgpu_eeprom_write(&adev->pm.smu_i2c, 197 + res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 198 198 control->i2c_address + 199 199 control->ras_header_offset, 200 200 buf, RAS_TABLE_HEADER_SIZE); ··· 389 389 /* i2c may be unstable in gpu reset */ 390 390 down_read(&adev->reset_sem); 391 391 buf_size = num * RAS_TABLE_RECORD_SIZE; 392 - res = amdgpu_eeprom_write(&adev->pm.smu_i2c, 392 + res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 393 393 control->i2c_address + 394 394 RAS_INDEX_TO_OFFSET(control, fri), 395 395 buf, buf_size); ··· 548 548 } 549 549 550 550 down_read(&adev->reset_sem); 551 - res = amdgpu_eeprom_read(&adev->pm.smu_i2c, 551 + res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 552 552 control->i2c_address + 553 553 control->ras_record_offset, 554 554 buf, buf_size); ··· 644 644 /* i2c may be unstable in gpu reset */ 645 645 down_read(&adev->reset_sem); 646 646 buf_size = num * RAS_TABLE_RECORD_SIZE; 647 - res = amdgpu_eeprom_read(&adev->pm.smu_i2c, 647 + res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 648 648 control->i2c_address + 649 649 RAS_INDEX_TO_OFFSET(control, fri), 650 650 buf, buf_size); ··· 1009 1009 return -ENOMEM; 1010 1010 } 1011 1011 1012 - res = amdgpu_eeprom_read(&adev->pm.smu_i2c, 1012 + res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1013 1013 control->i2c_address + 1014 1014 control->ras_header_offset, 1015 1015 buf, buf_size); ··· 1045 1045 return 0; 1046 1046 1047 1047 /* Verify i2c adapter is initialized */ 1048 - if (!adev->pm.smu_i2c.algo) 1048 + if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1049 1049 return -ENOENT; 1050 1050 1051 1051 if (!__get_eeprom_i2c_addr(adev, control)) ··· 1057 1057 mutex_init(&control->ras_tbl_mutex); 1058 1058 1059 1059 /* Read the table header from EEPROM address */ 1060 - res = amdgpu_eeprom_read(&adev->pm.smu_i2c, 1060 + res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1061 1061 control->i2c_address + control->ras_header_offset, 1062 1062 buf, RAS_TABLE_HEADER_SIZE); 1063 1063 if (res < RAS_TABLE_HEADER_SIZE) {
+53 -27
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
··· 26 26 27 27 #include "smu_v11_0_i2c.h" 28 28 #include "amdgpu.h" 29 + #include "amdgpu_dpm.h" 29 30 #include "soc15_common.h" 30 31 #include <drm/drm_fixed.h> 31 32 #include <drm/drm_drv.h> ··· 44 43 45 44 #define I2C_X_RESTART BIT(31) 46 45 47 - #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 48 - 49 46 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) 50 47 { 51 - struct amdgpu_device *adev = to_amdgpu_device(control); 48 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 49 + struct amdgpu_device *adev = smu_i2c->adev; 52 50 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); 53 51 54 52 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); ··· 75 75 76 76 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) 77 77 { 78 - struct amdgpu_device *adev = to_amdgpu_device(control); 78 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 79 + struct amdgpu_device *adev = smu_i2c->adev; 79 80 80 81 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0); 81 82 ··· 101 100 102 101 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) 103 102 { 104 - struct amdgpu_device *adev = to_amdgpu_device(control); 103 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 104 + struct amdgpu_device *adev = smu_i2c->adev; 105 105 /* do */ 106 106 { 107 107 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); ··· 112 110 113 111 static void smu_v11_0_i2c_configure(struct i2c_adapter *control) 114 112 { 115 - struct amdgpu_device *adev = to_amdgpu_device(control); 113 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 114 + struct amdgpu_device *adev = smu_i2c->adev; 116 115 uint32_t reg = 0; 117 116 118 117 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); ··· 134 131 135 132 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) 136 133 { 137 - struct amdgpu_device *adev = to_amdgpu_device(control); 134 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 135 + struct amdgpu_device *adev = smu_i2c->adev; 138 136 139 137 /* 140 138 * Standard mode speed, These values are taken from SMUIO MAS, ··· 158 154 159 155 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address) 160 156 { 161 - struct amdgpu_device *adev = to_amdgpu_device(control); 157 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 158 + struct amdgpu_device *adev = smu_i2c->adev; 162 159 163 160 /* The IC_TAR::IC_TAR field is 10-bits wide. 164 161 * It takes a 7-bit or 10-bit addresses as an address, ··· 170 165 171 166 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) 172 167 { 173 - struct amdgpu_device *adev = to_amdgpu_device(control); 168 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 169 + struct amdgpu_device *adev = smu_i2c->adev; 174 170 uint32_t ret = I2C_OK; 175 171 uint32_t reg, reg_c_tx_abrt_source; 176 172 ··· 222 216 223 217 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) 224 218 { 225 - struct amdgpu_device *adev = to_amdgpu_device(control); 219 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 220 + struct amdgpu_device *adev = smu_i2c->adev; 226 221 uint32_t ret = I2C_OK; 227 222 uint32_t reg_ic_status, reg_c_tx_abrt_source; 228 223 ··· 269 262 u16 address, u8 *data, 270 263 u32 numbytes, u32 i2c_flag) 271 264 { 272 - struct amdgpu_device *adev = to_amdgpu_device(control); 265 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 266 + struct amdgpu_device *adev = smu_i2c->adev; 273 267 u32 bytes_sent, reg, ret = I2C_OK; 274 268 unsigned long timeout_counter; 275 269 ··· 368 360 u16 address, u8 *data, 369 361 u32 numbytes, u32 i2c_flag) 370 362 { 371 - struct amdgpu_device *adev = to_amdgpu_device(control); 363 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 364 + struct amdgpu_device *adev = smu_i2c->adev; 372 365 uint32_t bytes_received, ret = I2C_OK; 373 366 374 367 bytes_received = 0; ··· 440 431 441 432 static void smu_v11_0_i2c_abort(struct i2c_adapter *control) 442 433 { 443 - struct amdgpu_device *adev = to_amdgpu_device(control); 434 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 435 + struct amdgpu_device *adev = smu_i2c->adev; 444 436 uint32_t reg = 0; 445 437 446 438 /* Enable I2C engine; */ ··· 457 447 458 448 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control) 459 449 { 460 - struct amdgpu_device *adev = to_amdgpu_device(control); 450 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 451 + struct amdgpu_device *adev = smu_i2c->adev; 461 452 462 453 const uint32_t IDLE_TIMEOUT = 1024; 463 454 uint32_t timeout_count = 0; ··· 519 508 520 509 static void smu_v11_0_i2c_fini(struct i2c_adapter *control) 521 510 { 522 - struct amdgpu_device *adev = to_amdgpu_device(control); 511 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 512 + struct amdgpu_device *adev = smu_i2c->adev; 523 513 u32 status, enable, en_stat; 524 514 int res; 525 515 ··· 555 543 556 544 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control) 557 545 { 558 - struct amdgpu_device *adev = to_amdgpu_device(control); 546 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 547 + struct amdgpu_device *adev = smu_i2c->adev; 559 548 560 549 /* Send PPSMC_MSG_RequestI2CBus */ 561 550 if (!amdgpu_dpm_smu_i2c_bus_access(adev, true)) ··· 567 554 568 555 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control) 569 556 { 570 - struct amdgpu_device *adev = to_amdgpu_device(control); 557 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 558 + struct amdgpu_device *adev = smu_i2c->adev; 571 559 572 560 /* Send PPSMC_MSG_ReleaseI2CBus */ 573 561 if (!amdgpu_dpm_smu_i2c_bus_access(adev, false)) ··· 601 587 602 588 if (ret != I2C_OK) 603 589 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret); 604 - 590 + 605 591 return ret; 606 592 607 593 } 608 594 609 595 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 610 596 { 611 - struct amdgpu_device *adev = to_amdgpu_device(i2c); 597 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c); 598 + struct amdgpu_device *adev = smu_i2c->adev; 612 599 613 - mutex_lock(&adev->pm.smu_i2c_mutex); 600 + mutex_lock(&smu_i2c->mutex); 614 601 if (!smu_v11_0_i2c_bus_lock(i2c)) 615 602 DRM_ERROR("Failed to lock the bus from SMU"); 616 603 else ··· 626 611 627 612 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 628 613 { 629 - struct amdgpu_device *adev = to_amdgpu_device(i2c); 614 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c); 615 + struct amdgpu_device *adev = smu_i2c->adev; 630 616 631 617 if (!smu_v11_0_i2c_bus_unlock(i2c)) 632 618 DRM_ERROR("Failed to unlock the bus from SMU"); 633 619 else 634 620 adev->pm.bus_locked = false; 635 - mutex_unlock(&adev->pm.smu_i2c_mutex); 621 + mutex_unlock(&smu_i2c->mutex); 636 622 } 637 623 638 624 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { ··· 722 706 .flags = I2C_AQ_NO_ZERO_LEN, 723 707 }; 724 708 725 - int smu_v11_0_i2c_control_init(struct i2c_adapter *control) 709 + int smu_v11_0_i2c_control_init(struct amdgpu_device *adev) 726 710 { 727 - struct amdgpu_device *adev = to_amdgpu_device(control); 711 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 712 + struct i2c_adapter *control = &smu_i2c->adapter; 728 713 int res; 729 714 730 - mutex_init(&adev->pm.smu_i2c_mutex); 715 + smu_i2c->adev = adev; 716 + smu_i2c->port = 0; 717 + mutex_init(&smu_i2c->mutex); 731 718 control->owner = THIS_MODULE; 732 719 control->class = I2C_CLASS_HWMON; 733 720 control->dev.parent = &adev->pdev->dev; 734 721 control->algo = &smu_v11_0_i2c_algo; 735 - snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 722 + snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 736 723 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; 737 724 control->quirks = &smu_v11_0_i2c_control_quirks; 725 + i2c_set_adapdata(control, smu_i2c); 726 + 727 + adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 728 + adev->pm.fru_eeprom_i2c_bus = NULL; 738 729 739 730 res = i2c_add_adapter(control); 740 731 if (res) ··· 750 727 return res; 751 728 } 752 729 753 - void smu_v11_0_i2c_control_fini(struct i2c_adapter *control) 730 + void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev) 754 731 { 732 + struct i2c_adapter *control = adev->pm.ras_eeprom_i2c_bus; 733 + 755 734 i2c_del_adapter(control); 735 + adev->pm.ras_eeprom_i2c_bus = NULL; 756 736 } 757 737 758 738 /*
+3 -3
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
··· 26 26 27 27 #include <linux/types.h> 28 28 29 - struct i2c_adapter; 29 + struct amdgpu_device; 30 30 31 - int smu_v11_0_i2c_control_init(struct i2c_adapter *control); 32 - void smu_v11_0_i2c_control_fini(struct i2c_adapter *control); 31 + int smu_v11_0_i2c_control_init(struct amdgpu_device *adev); 32 + void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev); 33 33 34 34 #endif
+12 -2
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
··· 284 284 /* Used to mask smu debug modes */ 285 285 #define SMU_DEBUG_HALT_ON_ERROR 0x1 286 286 287 + #define MAX_SMU_I2C_BUSES 2 288 + 289 + struct amdgpu_smu_i2c_bus { 290 + struct i2c_adapter adapter; 291 + struct amdgpu_device *adev; 292 + int port; 293 + struct mutex mutex; 294 + }; 295 + 287 296 struct amdgpu_pm { 288 297 struct mutex mutex; 289 298 u32 current_sclk; ··· 325 316 uint32_t pp_feature; 326 317 327 318 /* Used for I2C access to various EEPROMs on relevant ASICs */ 328 - struct i2c_adapter smu_i2c; 329 - struct mutex smu_i2c_mutex; 319 + struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES]; 320 + struct i2c_adapter *ras_eeprom_i2c_bus; 321 + struct i2c_adapter *fru_eeprom_i2c_bus; 330 322 struct list_head pm_attr_list; 331 323 332 324 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM];
+2 -2
drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
··· 520 520 priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].version = 0x01; 521 521 priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t); 522 522 523 - ret = smu_v11_0_i2c_control_init(&adev->pm.smu_i2c); 523 + ret = smu_v11_0_i2c_control_init(adev); 524 524 if (ret) 525 525 goto err4; 526 526 ··· 558 558 (struct vega20_smumgr *)(hwmgr->smu_backend); 559 559 struct amdgpu_device *adev = hwmgr->adev; 560 560 561 - smu_v11_0_i2c_control_fini(&adev->pm.smu_i2c); 561 + smu_v11_0_i2c_control_fini(adev); 562 562 563 563 if (priv) { 564 564 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
+2 -2
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 886 886 if (ret) 887 887 return ret; 888 888 889 - ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 889 + ret = smu_i2c_init(smu); 890 890 if (ret) 891 891 return ret; 892 892 ··· 897 897 { 898 898 int ret; 899 899 900 - smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 900 + smu_i2c_fini(smu); 901 901 902 902 smu_free_dummy_read_table(smu); 903 903
+2 -2
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 816 816 * other devices. The i2c's EEPROM also stores bad page tables on boards 817 817 * with ECC. 818 818 */ 819 - int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control); 819 + int (*i2c_init)(struct smu_context *smu); 820 820 821 821 /** 822 822 * @i2c_fini: Tear down i2c. 823 823 */ 824 - void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control); 824 + void (*i2c_fini)(struct smu_context *smu); 825 825 826 826 /** 827 827 * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
+51 -18
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
··· 25 25 26 26 #include <linux/firmware.h> 27 27 #include "amdgpu.h" 28 + #include "amdgpu_dpm.h" 28 29 #include "amdgpu_smu.h" 29 30 #include "atomfirmware.h" 30 31 #include "amdgpu_atomfirmware.h" ··· 46 45 #include <linux/pci.h> 47 46 #include "amdgpu_ras.h" 48 47 #include "smu_cmn.h" 48 + #include "amdgpu_dpm.h" 49 49 50 50 /* 51 51 * DO NOT use these for err/warn/info/debug messages. ··· 57 55 #undef pr_warn 58 56 #undef pr_info 59 57 #undef pr_debug 60 - 61 - #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 62 58 63 59 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \ 64 60 [smu_feature] = {1, (arcturus_feature)} ··· 2062 2062 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap, 2063 2063 struct i2c_msg *msg, int num_msgs) 2064 2064 { 2065 - struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 2065 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2066 + struct amdgpu_device *adev = smu_i2c->adev; 2066 2067 struct smu_context *smu = adev->powerplay.pp_handle; 2067 2068 struct smu_table_context *smu_table = &smu->smu_table; 2068 2069 struct smu_table *table = &smu_table->driver_table; ··· 2075 2074 if (!req) 2076 2075 return -ENOMEM; 2077 2076 2078 - req->I2CcontrollerPort = 0; 2077 + req->I2CcontrollerPort = smu_i2c->port; 2079 2078 req->I2CSpeed = I2C_SPEED_FAST_400K; 2080 2079 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2081 2080 dir = msg[0].flags & I2C_M_RD; ··· 2154 2153 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2155 2154 }; 2156 2155 2157 - static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 2156 + static int arcturus_i2c_control_init(struct smu_context *smu) 2158 2157 { 2159 - struct amdgpu_device *adev = to_amdgpu_device(control); 2160 - int res; 2158 + struct amdgpu_device *adev = smu->adev; 2159 + int res, i; 2161 2160 2162 - control->owner = THIS_MODULE; 2163 - control->class = I2C_CLASS_HWMON; 2164 - control->dev.parent = &adev->pdev->dev; 2165 - control->algo = &arcturus_i2c_algo; 2166 - control->quirks = &arcturus_i2c_control_quirks; 2167 - snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 2161 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2162 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2163 + struct i2c_adapter *control = &smu_i2c->adapter; 2168 2164 2169 - res = i2c_add_adapter(control); 2170 - if (res) 2171 - DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2165 + smu_i2c->adev = adev; 2166 + smu_i2c->port = i; 2167 + mutex_init(&smu_i2c->mutex); 2168 + control->owner = THIS_MODULE; 2169 + control->class = I2C_CLASS_HWMON; 2170 + control->dev.parent = &adev->pdev->dev; 2171 + control->algo = &arcturus_i2c_algo; 2172 + control->quirks = &arcturus_i2c_control_quirks; 2173 + snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2174 + i2c_set_adapdata(control, smu_i2c); 2172 2175 2176 + res = i2c_add_adapter(control); 2177 + if (res) { 2178 + DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2179 + goto Out_err; 2180 + } 2181 + } 2182 + 2183 + adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2184 + adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2185 + 2186 + return 0; 2187 + Out_err: 2188 + for ( ; i >= 0; i--) { 2189 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2190 + struct i2c_adapter *control = &smu_i2c->adapter; 2191 + 2192 + i2c_del_adapter(control); 2193 + } 2173 2194 return res; 2174 2195 } 2175 2196 2176 - static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 2197 + static void arcturus_i2c_control_fini(struct smu_context *smu) 2177 2198 { 2178 - i2c_del_adapter(control); 2199 + struct amdgpu_device *adev = smu->adev; 2200 + int i; 2201 + 2202 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2203 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2204 + struct i2c_adapter *control = &smu_i2c->adapter; 2205 + 2206 + i2c_del_adapter(control); 2207 + } 2208 + adev->pm.ras_eeprom_i2c_bus = NULL; 2209 + adev->pm.fru_eeprom_i2c_bus = NULL; 2179 2210 } 2180 2211 2181 2212 static void arcturus_get_unique_id(struct smu_context *smu)
+50 -18
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
··· 27 27 #include <linux/pci.h> 28 28 #include <linux/i2c.h> 29 29 #include "amdgpu.h" 30 + #include "amdgpu_dpm.h" 30 31 #include "amdgpu_smu.h" 31 32 #include "atomfirmware.h" 32 33 #include "amdgpu_atomfirmware.h" ··· 57 56 #undef pr_warn 58 57 #undef pr_info 59 58 #undef pr_debug 60 - 61 - #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 62 59 63 60 #define FEATURE_MASK(feature) (1ULL << feature) 64 61 #define SMC_DPM_FEATURE ( \ ··· 2745 2746 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 2746 2747 struct i2c_msg *msg, int num_msgs) 2747 2748 { 2748 - struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 2749 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2750 + struct amdgpu_device *adev = smu_i2c->adev; 2749 2751 struct smu_context *smu = adev->powerplay.pp_handle; 2750 2752 struct smu_table_context *smu_table = &smu->smu_table; 2751 2753 struct smu_table *table = &smu_table->driver_table; ··· 2758 2758 if (!req) 2759 2759 return -ENOMEM; 2760 2760 2761 - req->I2CcontrollerPort = 0; 2761 + req->I2CcontrollerPort = smu_i2c->port; 2762 2762 req->I2CSpeed = I2C_SPEED_FAST_400K; 2763 2763 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2764 2764 dir = msg[0].flags & I2C_M_RD; ··· 2836 2836 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2837 2837 }; 2838 2838 2839 - static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 2839 + static int navi10_i2c_control_init(struct smu_context *smu) 2840 2840 { 2841 - struct amdgpu_device *adev = to_amdgpu_device(control); 2842 - int res; 2841 + struct amdgpu_device *adev = smu->adev; 2842 + int res, i; 2843 2843 2844 - control->owner = THIS_MODULE; 2845 - control->class = I2C_CLASS_HWMON; 2846 - control->dev.parent = &adev->pdev->dev; 2847 - control->algo = &navi10_i2c_algo; 2848 - snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 2849 - control->quirks = &navi10_i2c_control_quirks; 2844 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2845 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2846 + struct i2c_adapter *control = &smu_i2c->adapter; 2850 2847 2851 - res = i2c_add_adapter(control); 2852 - if (res) 2853 - DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2848 + smu_i2c->adev = adev; 2849 + smu_i2c->port = i; 2850 + mutex_init(&smu_i2c->mutex); 2851 + control->owner = THIS_MODULE; 2852 + control->class = I2C_CLASS_HWMON; 2853 + control->dev.parent = &adev->pdev->dev; 2854 + control->algo = &navi10_i2c_algo; 2855 + snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2856 + control->quirks = &navi10_i2c_control_quirks; 2857 + i2c_set_adapdata(control, smu_i2c); 2854 2858 2859 + res = i2c_add_adapter(control); 2860 + if (res) { 2861 + DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2862 + goto Out_err; 2863 + } 2864 + } 2865 + 2866 + adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2867 + adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2868 + 2869 + return 0; 2870 + Out_err: 2871 + for ( ; i >= 0; i--) { 2872 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2873 + struct i2c_adapter *control = &smu_i2c->adapter; 2874 + 2875 + i2c_del_adapter(control); 2876 + } 2855 2877 return res; 2856 2878 } 2857 2879 2858 - static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 2880 + static void navi10_i2c_control_fini(struct smu_context *smu) 2859 2881 { 2860 - i2c_del_adapter(control); 2882 + struct amdgpu_device *adev = smu->adev; 2883 + int i; 2884 + 2885 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2886 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2887 + struct i2c_adapter *control = &smu_i2c->adapter; 2888 + 2889 + i2c_del_adapter(control); 2890 + } 2891 + adev->pm.ras_eeprom_i2c_bus = NULL; 2892 + adev->pm.fru_eeprom_i2c_bus = NULL; 2861 2893 } 2862 2894 2863 2895 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
+51 -18
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
··· 27 27 #include <linux/pci.h> 28 28 #include <linux/i2c.h> 29 29 #include "amdgpu.h" 30 + #include "amdgpu_dpm.h" 30 31 #include "amdgpu_smu.h" 31 32 #include "atomfirmware.h" 32 33 #include "amdgpu_atomfirmware.h" ··· 59 58 #undef pr_warn 60 59 #undef pr_info 61 60 #undef pr_debug 62 - 63 - #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 64 61 65 62 #define FEATURE_MASK(feature) (1ULL << feature) 66 63 #define SMC_DPM_FEATURE ( \ ··· 3440 3441 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 3441 3442 struct i2c_msg *msg, int num_msgs) 3442 3443 { 3443 - struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 3444 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3445 + struct amdgpu_device *adev = smu_i2c->adev; 3444 3446 struct smu_context *smu = adev->powerplay.pp_handle; 3445 3447 struct smu_table_context *smu_table = &smu->smu_table; 3446 3448 struct smu_table *table = &smu_table->driver_table; ··· 3453 3453 if (!req) 3454 3454 return -ENOMEM; 3455 3455 3456 - req->I2CcontrollerPort = 1; 3456 + req->I2CcontrollerPort = smu_i2c->port; 3457 3457 req->I2CSpeed = I2C_SPEED_FAST_400K; 3458 3458 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3459 3459 dir = msg[0].flags & I2C_M_RD; ··· 3531 3531 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3532 3532 }; 3533 3533 3534 - static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 3534 + static int sienna_cichlid_i2c_control_init(struct smu_context *smu) 3535 3535 { 3536 - struct amdgpu_device *adev = to_amdgpu_device(control); 3537 - int res; 3536 + struct amdgpu_device *adev = smu->adev; 3537 + int res, i; 3538 3538 3539 - control->owner = THIS_MODULE; 3540 - control->class = I2C_CLASS_HWMON; 3541 - control->dev.parent = &adev->pdev->dev; 3542 - control->algo = &sienna_cichlid_i2c_algo; 3543 - snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 3544 - control->quirks = &sienna_cichlid_i2c_control_quirks; 3539 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3540 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3541 + struct i2c_adapter *control = &smu_i2c->adapter; 3545 3542 3546 - res = i2c_add_adapter(control); 3547 - if (res) 3548 - DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3543 + smu_i2c->adev = adev; 3544 + smu_i2c->port = i; 3545 + mutex_init(&smu_i2c->mutex); 3546 + control->owner = THIS_MODULE; 3547 + control->class = I2C_CLASS_HWMON; 3548 + control->dev.parent = &adev->pdev->dev; 3549 + control->algo = &sienna_cichlid_i2c_algo; 3550 + snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3551 + control->quirks = &sienna_cichlid_i2c_control_quirks; 3552 + i2c_set_adapdata(control, smu_i2c); 3549 3553 3554 + res = i2c_add_adapter(control); 3555 + if (res) { 3556 + DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3557 + goto Out_err; 3558 + } 3559 + } 3560 + /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 3561 + /* XXX ideally this would be something in a vbios data table */ 3562 + adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3563 + adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3564 + 3565 + return 0; 3566 + Out_err: 3567 + for ( ; i >= 0; i--) { 3568 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3569 + struct i2c_adapter *control = &smu_i2c->adapter; 3570 + 3571 + i2c_del_adapter(control); 3572 + } 3550 3573 return res; 3551 3574 } 3552 3575 3553 - static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 3576 + static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) 3554 3577 { 3555 - i2c_del_adapter(control); 3578 + struct amdgpu_device *adev = smu->adev; 3579 + int i; 3580 + 3581 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3582 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3583 + struct i2c_adapter *control = &smu_i2c->adapter; 3584 + 3585 + i2c_del_adapter(control); 3586 + } 3587 + adev->pm.ras_eeprom_i2c_bus = NULL; 3588 + adev->pm.fru_eeprom_i2c_bus = NULL; 3556 3589 } 3557 3590 3558 3591 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
+34 -10
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
··· 25 25 26 26 #include <linux/firmware.h> 27 27 #include "amdgpu.h" 28 + #include "amdgpu_dpm.h" 28 29 #include "amdgpu_smu.h" 29 30 #include "atomfirmware.h" 30 31 #include "amdgpu_atomfirmware.h" ··· 56 55 #undef pr_warn 57 56 #undef pr_info 58 57 #undef pr_debug 59 - 60 - #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 58 62 59 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 63 60 [smu_feature] = {1, (aldebaran_feature)} ··· 1464 1465 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1465 1466 struct i2c_msg *msg, int num_msgs) 1466 1467 { 1467 - struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 1468 + struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1469 + struct amdgpu_device *adev = smu_i2c->adev; 1468 1470 struct smu_context *smu = adev->powerplay.pp_handle; 1469 1471 struct smu_table_context *smu_table = &smu->smu_table; 1470 1472 struct smu_table *table = &smu_table->driver_table; ··· 1477 1477 if (!req) 1478 1478 return -ENOMEM; 1479 1479 1480 - req->I2CcontrollerPort = 0; 1480 + req->I2CcontrollerPort = smu_i2c->port; 1481 1481 req->I2CSpeed = I2C_SPEED_FAST_400K; 1482 1482 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1483 1483 dir = msg[0].flags & I2C_M_RD; ··· 1555 1555 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1556 1556 }; 1557 1557 1558 - static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 1558 + static int aldebaran_i2c_control_init(struct smu_context *smu) 1559 1559 { 1560 - struct amdgpu_device *adev = to_amdgpu_device(control); 1560 + struct amdgpu_device *adev = smu->adev; 1561 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1562 + struct i2c_adapter *control = &smu_i2c->adapter; 1561 1563 int res; 1562 1564 1565 + smu_i2c->adev = adev; 1566 + smu_i2c->port = 0; 1567 + mutex_init(&smu_i2c->mutex); 1563 1568 control->owner = THIS_MODULE; 1564 1569 control->class = I2C_CLASS_SPD; 1565 1570 control->dev.parent = &adev->pdev->dev; 1566 1571 control->algo = &aldebaran_i2c_algo; 1567 - snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 1572 + snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1568 1573 control->quirks = &aldebaran_i2c_control_quirks; 1574 + i2c_set_adapdata(control, smu_i2c); 1569 1575 1570 1576 res = i2c_add_adapter(control); 1571 - if (res) 1577 + if (res) { 1572 1578 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1579 + goto Out_err; 1580 + } 1581 + 1582 + adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1583 + 1584 + return 0; 1585 + Out_err: 1586 + i2c_del_adapter(control); 1573 1587 1574 1588 return res; 1575 1589 } 1576 1590 1577 - static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 1591 + static void aldebaran_i2c_control_fini(struct smu_context *smu) 1578 1592 { 1579 - i2c_del_adapter(control); 1593 + struct amdgpu_device *adev = smu->adev; 1594 + int i; 1595 + 1596 + for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1597 + struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1598 + struct i2c_adapter *control = &smu_i2c->adapter; 1599 + 1600 + i2c_del_adapter(control); 1601 + } 1602 + adev->pm.ras_eeprom_i2c_bus = NULL; 1603 + adev->pm.fru_eeprom_i2c_bus = NULL; 1580 1604 } 1581 1605 1582 1606 static void aldebaran_get_unique_id(struct smu_context *smu)
+2 -2
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
··· 78 78 #define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu) 79 79 #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap) 80 80 #define smu_set_power_source(smu, power_src) smu_ppt_funcs(set_power_source, 0, smu, power_src) 81 - #define smu_i2c_init(smu, control) smu_ppt_funcs(i2c_init, 0, smu, control) 82 - #define smu_i2c_fini(smu, control) smu_ppt_funcs(i2c_fini, 0, smu, control) 81 + #define smu_i2c_init(smu) smu_ppt_funcs(i2c_init, 0, smu) 82 + #define smu_i2c_fini(smu) smu_ppt_funcs(i2c_fini, 0, smu) 83 83 #define smu_get_unique_id(smu) smu_ppt_funcs(get_unique_id, 0, smu) 84 84 #define smu_log_thermal_throttling(smu) smu_ppt_funcs(log_thermal_throttling_event, 0, smu) 85 85 #define smu_get_asic_power_limits(smu, current, default, max) smu_ppt_funcs(get_power_limit, 0, smu, current, default, max)