tjh.dev
+9
-9
arch/riscv/include/asm/csr.h
+9
-9
arch/riscv/include/asm/csr.h
···
116
116
# define SR_PIE SR_MPIE
117
117
# define SR_PP SR_MPP
118
118
119
-
# define IRQ_SOFT IRQ_M_SOFT
120
-
# define IRQ_TIMER IRQ_M_TIMER
121
-
# define IRQ_EXT IRQ_M_EXT
119
+
# define RV_IRQ_SOFT IRQ_M_SOFT
120
+
# define RV_IRQ_TIMER IRQ_M_TIMER
121
+
# define RV_IRQ_EXT IRQ_M_EXT
122
122
#else /* CONFIG_RISCV_M_MODE */
123
123
# define CSR_STATUS CSR_SSTATUS
124
124
# define CSR_IE CSR_SIE
···
133
133
# define SR_PIE SR_SPIE
134
134
# define SR_PP SR_SPP
135
135
136
-
# define IRQ_SOFT IRQ_S_SOFT
137
-
# define IRQ_TIMER IRQ_S_TIMER
138
-
# define IRQ_EXT IRQ_S_EXT
136
+
# define RV_IRQ_SOFT IRQ_S_SOFT
137
+
# define RV_IRQ_TIMER IRQ_S_TIMER
138
+
# define RV_IRQ_EXT IRQ_S_EXT
139
139
#endif /* CONFIG_RISCV_M_MODE */
140
140
141
141
/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
142
-
#define IE_SIE (_AC(0x1, UL) << IRQ_SOFT)
143
-
#define IE_TIE (_AC(0x1, UL) << IRQ_TIMER)
144
-
#define IE_EIE (_AC(0x1, UL) << IRQ_EXT)
142
+
#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
143
+
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
144
+
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
145
145
146
146
#ifndef __ASSEMBLY__
147
147
+3
-3
arch/riscv/kernel/irq.c
+3
-3
arch/riscv/kernel/irq.c
···
23
23
24
24
irq_enter();
25
25
switch (regs->cause & ~CAUSE_IRQ_FLAG) {
26
-
case IRQ_TIMER:
26
+
case RV_IRQ_TIMER:
27
27
riscv_timer_interrupt();
28
28
break;
29
29
#ifdef CONFIG_SMP
30
-
case IRQ_SOFT:
30
+
case RV_IRQ_SOFT:
31
31
/*
32
32
* We only use software interrupts to pass IPIs, so if a non-SMP
33
33
* system gets one, then we don't know what to do.
···
35
35
riscv_software_interrupt();
36
36
break;
37
37
#endif
38
-
case IRQ_EXT:
38
+
case RV_IRQ_EXT:
39
39
handle_arch_irq(regs);
40
40
break;
41
41
default: