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ARM: tegra: define DT bindings for and instantiate timer
The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
+64
+21
Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
+21
Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
···
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NVIDIA Tegra20 timer
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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Example:
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timer {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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};
+23
Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+23
Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
···
1
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NVIDIA Tegra30 timer
2
+
3
+
The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4
+
running counter, and 5 watchdog modules. The first two channels may also
5
+
trigger a legacy watchdog reset.
6
+
7
+
Required properties:
8
+
9
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- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
10
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- reg : Specifies base physical address and size of the registers.
11
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
12
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through 5, and one for the shared interrupt for the remaining channels.
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timer {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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};
+9
arch/arm/boot/dts/tegra20.dtsi
+9
arch/arm/boot/dts/tegra20.dtsi
···
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#interrupt-cells = <3>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1200>;
+11
arch/arm/boot/dts/tegra30.dtsi
+11
arch/arm/boot/dts/tegra30.dtsi
···
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#interrupt-cells = <3>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
115
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0 1 0x04
116
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0 41 0x04
117
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;