tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.17, please pull the following:
- Linus updates the 64-bit BCMBCA SoCs Device Tree with the common
peripherals that exit as well as correct IRQ assignments
- Andrea adds support for the RP1 companion chip on the Raspberry Pi 5
systems with clocks, gpios, pinctrl, all of that using an overlay to
describe those peripherals
- Rob drops the interrupt-parent property from the GICv2M node on
Northstar2 SoCs
* tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"
arm64: dts: broadcom: Add overlay for RP1 device
arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
arm64: dts: rp1: Add support for RaspberryPi's RP1 device
dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
dt-bindings: clock: Add RaspberryPi RP1 clock bindings
ARM64: dts: bcm63158: Add BCMBCA peripherals
ARM64: dts: bcm6858: Add BCMBCA peripherals
ARM64: dts: bcm6856: Add BCMBCA peripherals
ARM64: dts: bcm4908: Add BCMBCA peripherals
Link: https://lore.kernel.org/r/20250630190216.1518354-3-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+1148
-117
+58
Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml
+58
Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RaspberryPi RP1 clock generator
8
+
9
+
maintainers:
10
+
- A. della Porta <andrea.porta@suse.com>
11
+
12
+
description: |
13
+
The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO,
14
+
VIDEO), and each PLL output can be programmed through dividers to generate
15
+
the clocks to drive the sub-peripherals embedded inside the chipset.
16
+
17
+
Link to datasheet:
18
+
https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf
19
+
20
+
properties:
21
+
compatible:
22
+
const: raspberrypi,rp1-clocks
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
'#clock-cells':
28
+
const: 1
29
+
description:
30
+
The available clocks are defined in
31
+
include/dt-bindings/clock/raspberrypi,rp1-clocks.h.
32
+
33
+
clocks:
34
+
maxItems: 1
35
+
36
+
required:
37
+
- compatible
38
+
- reg
39
+
- '#clock-cells'
40
+
- clocks
41
+
42
+
additionalProperties: false
43
+
44
+
examples:
45
+
- |
46
+
#include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
47
+
48
+
rp1 {
49
+
#address-cells = <2>;
50
+
#size-cells = <2>;
51
+
52
+
clocks@c040018000 {
53
+
compatible = "raspberrypi,rp1-clocks";
54
+
reg = <0xc0 0x40018000 0x0 0x10038>;
55
+
#clock-cells = <1>;
56
+
clocks = <&clk_rp1_xosc>;
57
+
};
58
+
};
+137
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
+137
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/misc/pci1de4,1.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RaspberryPi RP1 MFD PCI device
8
+
9
+
maintainers:
10
+
- A. della Porta <andrea.porta@suse.com>
11
+
12
+
description:
13
+
The RaspberryPi RP1 is a PCI multi function device containing
14
+
peripherals ranging from Ethernet to USB controller, I2C, SPI
15
+
and others.
16
+
The peripherals are accessed by addressing the PCI BAR1 region.
17
+
18
+
allOf:
19
+
- $ref: /schemas/pci/pci-ep-bus.yaml
20
+
21
+
properties:
22
+
compatible:
23
+
additionalItems: true
24
+
maxItems: 3
25
+
items:
26
+
- const: pci1de4,1
27
+
28
+
'#interrupt-cells':
29
+
const: 2
30
+
description: |
31
+
Specifies respectively the interrupt number and flags as defined
32
+
in include/dt-bindings/interrupt-controller/irq.h.
33
+
Since all interrupts are active high, only IRQ_TYPE_LEVEL_HIGH
34
+
and IRQ_TYPE_EDGE_RISING can be specified as type flags.
35
+
The supported values for the interrupt number are:
36
+
- IO BANK0: 0
37
+
- IO BANK1: 1
38
+
- IO BANK2: 2
39
+
- AUDIO IN: 3
40
+
- AUDIO OUT: 4
41
+
- PWM0: 5
42
+
- ETH: 6
43
+
- I2C0: 7
44
+
- I2C1: 8
45
+
- I2C2: 9
46
+
- I2C3: 10
47
+
- I2C4: 11
48
+
- I2C5: 12
49
+
- I2C6: 13
50
+
- I2S0: 14
51
+
- I2S1: 15
52
+
- I2S2: 16
53
+
- SDIO0: 17
54
+
- SDIO1: 18
55
+
- SPI0: 19
56
+
- SPI1: 20
57
+
- SPI2: 21
58
+
- SPI3: 22
59
+
- SPI4: 23
60
+
- SPI5: 24
61
+
- UART0: 25
62
+
- TIMER0: 26
63
+
- TIMER1: 27
64
+
- TIMER2: 28
65
+
- TIMER3: 29
66
+
- USB HOST0: 30
67
+
- USB HOST0-0: 31
68
+
- USB HOST0-1: 32
69
+
- USB HOST0-2: 33
70
+
- USB HOST0-3: 34
71
+
- USB HOST1: 35
72
+
- USB HOST1-0: 36
73
+
- USB HOST1-1: 37
74
+
- USB HOST1-2: 38
75
+
- USB HOST1-3: 39
76
+
- DMA: 40
77
+
- PWM1: 41
78
+
- UART1: 42
79
+
- UART2: 43
80
+
- UART3: 44
81
+
- UART4: 45
82
+
- UART5: 46
83
+
- MIPI0: 47
84
+
- MIPI1: 48
85
+
- VIDEO OUT: 49
86
+
- PIO0: 50
87
+
- PIO1: 51
88
+
- ADC FIFO: 52
89
+
- PCIE OUT: 53
90
+
- SPI6: 54
91
+
- SPI7: 55
92
+
- SPI8: 56
93
+
- PROC MISC: 57
94
+
- SYSCFG: 58
95
+
- CLOCKS DEFAULT: 59
96
+
- VBUSCTRL: 60
97
+
98
+
interrupt-controller: true
99
+
100
+
unevaluatedProperties: false
101
+
102
+
required:
103
+
- compatible
104
+
- '#interrupt-cells'
105
+
- interrupt-controller
106
+
- pci-ep-bus@1
107
+
108
+
examples:
109
+
- |
110
+
pci {
111
+
#address-cells = <3>;
112
+
#size-cells = <2>;
113
+
114
+
rp1@0,0 {
115
+
compatible = "pci1de4,1";
116
+
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
117
+
#address-cells = <3>;
118
+
#size-cells = <2>;
119
+
interrupt-controller;
120
+
#interrupt-cells = <2>;
121
+
122
+
pci_ep_bus: pci-ep-bus@1 {
123
+
compatible = "simple-bus";
124
+
ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>;
125
+
dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>;
126
+
#address-cells = <2>;
127
+
#size-cells = <2>;
128
+
129
+
rp1_clocks: clocks@40018000 {
130
+
compatible = "raspberrypi,rp1-clocks";
131
+
reg = <0x00 0x40018000 0x0 0x10038>;
132
+
#clock-cells = <1>;
133
+
clocks = <&clk_rp1_xosc>;
134
+
};
135
+
};
136
+
};
137
+
};
+198
Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml
+198
Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/raspberrypi,rp1-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RaspberryPi RP1 GPIO/Pinconf/Pinmux Controller submodule
8
+
9
+
maintainers:
10
+
- A. della Porta <andrea.porta@suse.com>
11
+
12
+
description:
13
+
The RP1 chipset is a Multi Function Device containing, among other
14
+
sub-peripherals, a gpio/pinconf/mux controller whose 54 pins are grouped
15
+
into 3 banks.
16
+
It works also as an interrupt controller for those gpios.
17
+
18
+
properties:
19
+
compatible:
20
+
const: raspberrypi,rp1-gpio
21
+
22
+
reg:
23
+
maxItems: 3
24
+
description: One reg specifier for each one of the 3 pin banks.
25
+
26
+
'#gpio-cells':
27
+
description: The first cell is the pin number and the second cell is used
28
+
to specify the flags (see include/dt-bindings/gpio/gpio.h).
29
+
const: 2
30
+
31
+
gpio-controller: true
32
+
33
+
gpio-ranges:
34
+
maxItems: 1
35
+
36
+
gpio-line-names:
37
+
maxItems: 54
38
+
39
+
interrupts:
40
+
maxItems: 3
41
+
description: One interrupt specifier for each one of the 3 pin banks.
42
+
43
+
'#interrupt-cells':
44
+
description:
45
+
Specifies the Bank number [0, 1, 2] and Flags as defined in
46
+
include/dt-bindings/interrupt-controller/irq.h.
47
+
const: 2
48
+
49
+
interrupt-controller: true
50
+
51
+
patternProperties:
52
+
'-state$':
53
+
oneOf:
54
+
- $ref: '#/$defs/raspberrypi-rp1-state'
55
+
- patternProperties:
56
+
'-pins$':
57
+
$ref: '#/$defs/raspberrypi-rp1-state'
58
+
additionalProperties: false
59
+
60
+
$defs:
61
+
raspberrypi-rp1-state:
62
+
allOf:
63
+
- $ref: pincfg-node.yaml#
64
+
- $ref: pinmux-node.yaml#
65
+
66
+
description:
67
+
Pin controller client devices use pin configuration subnodes (children
68
+
and grandchildren) for desired pin configuration.
69
+
Client device subnodes use below standard properties.
70
+
71
+
properties:
72
+
pins:
73
+
description:
74
+
List of gpio pins affected by the properties specified in this
75
+
subnode.
76
+
items:
77
+
pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$'
78
+
79
+
function:
80
+
enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none,
81
+
aaud, dcd0, dpi, dsi0_te_ext, dsi1_te_ext, dsr0, dtr0, gpclk0,
82
+
gpclk1, gpclk2, gpclk3, gpclk4, gpclk5, i2c0, i2c1, i2c2, i2c3,
83
+
i2c4, i2c5, i2c6, i2s0, i2s1, i2s2, ir, mic, pcie_clkreq_n,
84
+
pio, proc_rio, pwm0, pwm1, ri0, sd0, sd1, spi0, spi1, spi2,
85
+
spi3, spi4, spi5, spi6, spi7, spi8, uart0, uart1, uart2, uart3,
86
+
uart4, uart5, vbus0, vbus1, vbus2, vbus3 ]
87
+
88
+
description:
89
+
Specify the alternative function to be configured for the specified
90
+
pins.
91
+
92
+
bias-disable: true
93
+
bias-pull-down: true
94
+
bias-pull-up: true
95
+
input-enable: true
96
+
input-schmitt-enable: true
97
+
output-enable: true
98
+
output-high: true
99
+
output-low: true
100
+
slew-rate:
101
+
description: 0 is slow slew rate, 1 is fast slew rate
102
+
enum: [ 0, 1 ]
103
+
drive-strength:
104
+
enum: [ 2, 4, 8, 12 ]
105
+
106
+
additionalProperties: false
107
+
108
+
allOf:
109
+
- $ref: pinctrl.yaml#
110
+
111
+
required:
112
+
- reg
113
+
- compatible
114
+
- '#gpio-cells'
115
+
- gpio-controller
116
+
- interrupts
117
+
- '#interrupt-cells'
118
+
- interrupt-controller
119
+
120
+
unevaluatedProperties: false
121
+
122
+
examples:
123
+
- |
124
+
#include <dt-bindings/interrupt-controller/irq.h>
125
+
126
+
rp1 {
127
+
#address-cells = <2>;
128
+
#size-cells = <2>;
129
+
130
+
rp1_gpio: pinctrl@c0400d0000 {
131
+
reg = <0xc0 0x400d0000 0x0 0xc000>,
132
+
<0xc0 0x400e0000 0x0 0xc000>,
133
+
<0xc0 0x400f0000 0x0 0xc000>;
134
+
compatible = "raspberrypi,rp1-gpio";
135
+
gpio-controller;
136
+
#gpio-cells = <2>;
137
+
interrupt-controller;
138
+
#interrupt-cells = <2>;
139
+
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
140
+
<1 IRQ_TYPE_LEVEL_HIGH>,
141
+
<2 IRQ_TYPE_LEVEL_HIGH>;
142
+
gpio-line-names =
143
+
"ID_SDA", // GPIO0
144
+
"ID_SCL", // GPIO1
145
+
"GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6",
146
+
"GPIO7", "GPIO8", "GPIO9", "GPIO10", "GPIO11",
147
+
"GPIO12", "GPIO13", "GPIO14", "GPIO15", "GPIO16",
148
+
"GPIO17", "GPIO18", "GPIO19", "GPIO20", "GPIO21",
149
+
"GPIO22", "GPIO23", "GPIO24", "GPIO25", "GPIO26",
150
+
"GPIO27",
151
+
"PCIE_RP1_WAKE", // GPIO28
152
+
"FAN_TACH", // GPIO29
153
+
"HOST_SDA", // GPIO30
154
+
"HOST_SCL", // GPIO31
155
+
"ETH_RST_N", // GPIO32
156
+
"", // GPIO33
157
+
"CD0_IO0_MICCLK", // GPIO34
158
+
"CD0_IO0_MICDAT0", // GPIO35
159
+
"RP1_PCIE_CLKREQ_N", // GPIO36
160
+
"", // GPIO37
161
+
"CD0_SDA", // GPIO38
162
+
"CD0_SCL", // GPIO39
163
+
"CD1_SDA", // GPIO40
164
+
"CD1_SCL", // GPIO41
165
+
"USB_VBUS_EN", // GPIO42
166
+
"USB_OC_N", // GPIO43
167
+
"RP1_STAT_LED", // GPIO44
168
+
"FAN_PWM", // GPIO45
169
+
"CD1_IO0_MICCLK", // GPIO46
170
+
"2712_WAKE", // GPIO47
171
+
"CD1_IO1_MICDAT1", // GPIO48
172
+
"EN_MAX_USB_CUR", // GPIO49
173
+
"", // GPIO50
174
+
"", // GPIO51
175
+
"", // GPIO52
176
+
""; // GPIO53
177
+
178
+
rp1-i2s0-default-state {
179
+
function = "i2s0";
180
+
pins = "gpio18", "gpio19", "gpio20", "gpio21";
181
+
bias-disable;
182
+
};
183
+
184
+
rp1-uart0-default-state {
185
+
txd-pins {
186
+
function = "uart0";
187
+
pins = "gpio14";
188
+
bias-disable;
189
+
};
190
+
191
+
rxd-pins {
192
+
function = "uart0";
193
+
pins = "gpio15";
194
+
bias-pull-up;
195
+
};
196
+
};
197
+
};
198
+
};
+3
-1
arch/arm64/boot/dts/broadcom/Makefile
+3
-1
arch/arm64/boot/dts/broadcom/Makefile
···
7
7
bcm2711-rpi-4-b.dtb \
8
8
bcm2711-rpi-cm4-io.dtb \
9
9
bcm2712-rpi-5-b.dtb \
10
+
bcm2712-rpi-5-b-ovl-rp1.dtb \
10
11
bcm2712-d-rpi-5-b.dtb \
11
12
bcm2837-rpi-2-b.dtb \
12
13
bcm2837-rpi-3-a-plus.dtb \
13
14
bcm2837-rpi-3-b.dtb \
14
15
bcm2837-rpi-3-b-plus.dtb \
15
16
bcm2837-rpi-cm3-io3.dtb \
16
-
bcm2837-rpi-zero-2-w.dtb
17
+
bcm2837-rpi-zero-2-w.dtb \
18
+
rp1.dtbo
17
19
18
20
subdir-y += bcmbca
19
21
subdir-y += northstar2
+121
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
+121
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/dts-v1/;
3
+
4
+
#include <dt-bindings/gpio/gpio.h>
5
+
#include "bcm2712.dtsi"
6
+
7
+
/ {
8
+
compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
9
+
model = "Raspberry Pi 5";
10
+
11
+
aliases {
12
+
serial10 = &uart10;
13
+
};
14
+
15
+
chosen: chosen {
16
+
stdout-path = "serial10:115200n8";
17
+
};
18
+
19
+
clk_rp1_xosc: clock-50000000 {
20
+
compatible = "fixed-clock";
21
+
#clock-cells = <0>;
22
+
clock-output-names = "rp1-xosc";
23
+
clock-frequency = <50000000>;
24
+
};
25
+
26
+
/* Will be filled by the bootloader */
27
+
memory@0 {
28
+
device_type = "memory";
29
+
reg = <0 0 0 0x28000000>;
30
+
};
31
+
32
+
sd_io_1v8_reg: sd-io-1v8-reg {
33
+
compatible = "regulator-gpio";
34
+
regulator-name = "vdd-sd-io";
35
+
regulator-min-microvolt = <1800000>;
36
+
regulator-max-microvolt = <3300000>;
37
+
regulator-boot-on;
38
+
regulator-always-on;
39
+
regulator-settling-time-us = <5000>;
40
+
gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
41
+
states = <1800000 1>,
42
+
<3300000 0>;
43
+
};
44
+
45
+
sd_vcc_reg: sd-vcc-reg {
46
+
compatible = "regulator-fixed";
47
+
regulator-name = "vcc-sd";
48
+
regulator-min-microvolt = <3300000>;
49
+
regulator-max-microvolt = <3300000>;
50
+
regulator-boot-on;
51
+
enable-active-high;
52
+
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
53
+
};
54
+
};
55
+
56
+
/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
57
+
* labeled "UART", i.e. the interface with the system console.
58
+
*/
59
+
&uart10 {
60
+
status = "okay";
61
+
};
62
+
63
+
/* SDIO1 is used to drive the SD card */
64
+
&sdio1 {
65
+
vqmmc-supply = <&sd_io_1v8_reg>;
66
+
vmmc-supply = <&sd_vcc_reg>;
67
+
bus-width = <4>;
68
+
sd-uhs-sdr50;
69
+
sd-uhs-ddr50;
70
+
sd-uhs-sdr104;
71
+
};
72
+
73
+
&soc {
74
+
firmware: firmware {
75
+
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
76
+
#address-cells = <1>;
77
+
#size-cells = <1>;
78
+
79
+
mboxes = <&mailbox>;
80
+
dma-ranges;
81
+
82
+
firmware_clocks: clocks {
83
+
compatible = "raspberrypi,firmware-clocks";
84
+
#clock-cells = <1>;
85
+
};
86
+
87
+
reset: reset {
88
+
compatible = "raspberrypi,firmware-reset";
89
+
#reset-cells = <1>;
90
+
};
91
+
};
92
+
93
+
power: power {
94
+
compatible = "raspberrypi,bcm2835-power";
95
+
firmware = <&firmware>;
96
+
#power-domain-cells = <1>;
97
+
};
98
+
};
99
+
100
+
&hvs {
101
+
clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
102
+
clock-names = "core", "disp";
103
+
};
104
+
105
+
&hdmi0 {
106
+
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
107
+
clock-names = "hdmi", "bvb", "audio", "cec";
108
+
};
109
+
110
+
&hdmi1 {
111
+
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
112
+
clock-names = "hdmi", "bvb", "audio", "cec";
113
+
};
114
+
115
+
&pcie1 {
116
+
status = "okay";
117
+
};
118
+
119
+
&pcie2 {
120
+
status = "okay";
121
+
};
+12
-101
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+12
-101
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
···
1
1
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/*
3
+
* bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make
4
+
* the RP1 driver to load the RP1 dtb overlay at runtime, while
5
+
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
6
+
* already contains RP1 node, so no overlay is loaded nor needed).
7
+
* This file is not intended to be modified, nodes should be added
8
+
* to the included bcm2712-rpi-5-b-ovl-rp1.dts.
9
+
*/
10
+
2
11
/dts-v1/;
3
12
4
-
#include <dt-bindings/gpio/gpio.h>
5
-
#include "bcm2712.dtsi"
13
+
#include "bcm2712-rpi-5-b-ovl-rp1.dts"
6
14
7
-
/ {
8
-
compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
9
-
model = "Raspberry Pi 5";
10
-
11
-
aliases {
12
-
serial10 = &uart10;
13
-
};
14
-
15
-
chosen: chosen {
16
-
stdout-path = "serial10:115200n8";
17
-
};
18
-
19
-
/* Will be filled by the bootloader */
20
-
memory@0 {
21
-
device_type = "memory";
22
-
reg = <0 0 0 0x28000000>;
23
-
};
24
-
25
-
sd_io_1v8_reg: sd-io-1v8-reg {
26
-
compatible = "regulator-gpio";
27
-
regulator-name = "vdd-sd-io";
28
-
regulator-min-microvolt = <1800000>;
29
-
regulator-max-microvolt = <3300000>;
30
-
regulator-boot-on;
31
-
regulator-always-on;
32
-
regulator-settling-time-us = <5000>;
33
-
gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
34
-
states = <1800000 1>,
35
-
<3300000 0>;
36
-
};
37
-
38
-
sd_vcc_reg: sd-vcc-reg {
39
-
compatible = "regulator-fixed";
40
-
regulator-name = "vcc-sd";
41
-
regulator-min-microvolt = <3300000>;
42
-
regulator-max-microvolt = <3300000>;
43
-
regulator-boot-on;
44
-
enable-active-high;
45
-
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
46
-
};
47
-
};
48
-
49
-
/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
50
-
* labeled "UART", i.e. the interface with the system console.
51
-
*/
52
-
&uart10 {
53
-
status = "okay";
54
-
};
55
-
56
-
/* SDIO1 is used to drive the SD card */
57
-
&sdio1 {
58
-
vqmmc-supply = <&sd_io_1v8_reg>;
59
-
vmmc-supply = <&sd_vcc_reg>;
60
-
bus-width = <4>;
61
-
sd-uhs-sdr50;
62
-
sd-uhs-ddr50;
63
-
sd-uhs-sdr104;
64
-
};
65
-
66
-
&soc {
67
-
firmware: firmware {
68
-
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
69
-
#address-cells = <1>;
70
-
#size-cells = <1>;
71
-
72
-
mboxes = <&mailbox>;
73
-
dma-ranges;
74
-
75
-
firmware_clocks: clocks {
76
-
compatible = "raspberrypi,firmware-clocks";
77
-
#clock-cells = <1>;
78
-
};
79
-
80
-
reset: reset {
81
-
compatible = "raspberrypi,firmware-reset";
82
-
#reset-cells = <1>;
83
-
};
84
-
};
85
-
86
-
power: power {
87
-
compatible = "raspberrypi,bcm2835-power";
88
-
firmware = <&firmware>;
89
-
#power-domain-cells = <1>;
90
-
};
91
-
};
92
-
93
-
&hvs {
94
-
clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
95
-
clock-names = "core", "disp";
96
-
};
97
-
98
-
&hdmi0 {
99
-
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
100
-
clock-names = "hdmi", "bvb", "audio", "cec";
101
-
};
102
-
103
-
&hdmi1 {
104
-
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
105
-
clock-names = "hdmi", "bvb", "audio", "cec";
15
+
&pcie2 {
16
+
#include "rp1-nexus.dtsi"
106
17
};
107
18
108
19
&pcie1 {
+115
-5
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+115
-5
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
···
323
323
};
324
324
};
325
325
326
+
/* PERF Peripherals */
326
327
bus@ff800000 {
327
328
compatible = "simple-bus";
328
329
#address-cells = <1>;
329
330
#size-cells = <1>;
330
-
ranges = <0x00 0x00 0xff800000 0x3000>;
331
+
ranges = <0x00 0x00 0xff800000 0x400000>;
331
332
332
333
twd: timer-mfd@400 {
333
334
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
···
349
348
};
350
349
};
351
350
352
-
gpio0: gpio-controller@500 {
351
+
/* GPIOs 0 .. 31 */
352
+
gpio0: gpio@500 {
353
353
compatible = "brcm,bcm6345-gpio";
354
+
reg = <0x500 0x04>, <0x528 0x04>;
354
355
reg-names = "dirout", "dat";
355
-
reg = <0x500 0x28>, <0x528 0x28>;
356
-
357
-
#gpio-cells = <2>;
358
356
gpio-controller;
357
+
#gpio-cells = <2>;
358
+
};
359
+
360
+
/* GPIOs 32 .. 63 */
361
+
gpio1: gpio@504 {
362
+
compatible = "brcm,bcm6345-gpio";
363
+
reg = <0x504 0x04>, <0x52c 0x04>;
364
+
reg-names = "dirout", "dat";
365
+
gpio-controller;
366
+
#gpio-cells = <2>;
367
+
status = "disabled";
368
+
};
369
+
370
+
/* GPIOs 64 .. 95 */
371
+
gpio2: gpio@508 {
372
+
compatible = "brcm,bcm6345-gpio";
373
+
reg = <0x508 0x04>, <0x530 0x04>;
374
+
reg-names = "dirout", "dat";
375
+
gpio-controller;
376
+
#gpio-cells = <2>;
377
+
status = "disabled";
378
+
};
379
+
380
+
/* GPIOs 96 .. 127 */
381
+
gpio3: gpio@50c {
382
+
compatible = "brcm,bcm6345-gpio";
383
+
reg = <0x50c 0x04>, <0x534 0x04>;
384
+
reg-names = "dirout", "dat";
385
+
gpio-controller;
386
+
#gpio-cells = <2>;
387
+
status = "disabled";
388
+
};
389
+
390
+
/* GPIOs 128 .. 159 */
391
+
gpio4: gpio@510 {
392
+
compatible = "brcm,bcm6345-gpio";
393
+
reg = <0x510 0x04>, <0x538 0x04>;
394
+
reg-names = "dirout", "dat";
395
+
gpio-controller;
396
+
#gpio-cells = <2>;
397
+
status = "disabled";
398
+
};
399
+
400
+
/* GPIOs 160 .. 191 */
401
+
gpio5: gpio@514 {
402
+
compatible = "brcm,bcm6345-gpio";
403
+
reg = <0x514 0x04>, <0x53c 0x04>;
404
+
reg-names = "dirout", "dat";
405
+
gpio-controller;
406
+
#gpio-cells = <2>;
407
+
status = "disabled";
408
+
};
409
+
410
+
/* GPIOs 192 .. 223 */
411
+
gpio6: gpio@518 {
412
+
compatible = "brcm,bcm6345-gpio";
413
+
reg = <0x518 0x04>, <0x540 0x04>;
414
+
reg-names = "dirout", "dat";
415
+
gpio-controller;
416
+
#gpio-cells = <2>;
417
+
status = "disabled";
418
+
};
419
+
420
+
/* GPIOs 224 .. 255 */
421
+
gpio7: gpio@51c {
422
+
compatible = "brcm,bcm6345-gpio";
423
+
reg = <0x51c 0x04>, <0x544 0x04>;
424
+
reg-names = "dirout", "dat";
425
+
gpio-controller;
426
+
#gpio-cells = <2>;
427
+
status = "disabled";
428
+
};
429
+
430
+
/* GPIOs 256 .. 287 */
431
+
gpio8: gpio@520 {
432
+
compatible = "brcm,bcm6345-gpio";
433
+
reg = <0x520 0x04>, <0x548 0x04>;
434
+
reg-names = "dirout", "dat";
435
+
gpio-controller;
436
+
#gpio-cells = <2>;
437
+
status = "disabled";
438
+
};
439
+
440
+
/* GPIOs 288 .. 319 */
441
+
gpio9: gpio@524 {
442
+
compatible = "brcm,bcm6345-gpio";
443
+
reg = <0x524 0x04>, <0x54c 0x04>;
444
+
reg-names = "dirout", "dat";
445
+
gpio-controller;
446
+
#gpio-cells = <2>;
447
+
status = "disabled";
359
448
};
360
449
361
450
pinctrl@560 {
···
675
584
#size-cells = <0>;
676
585
};
677
586
587
+
rng@b80 {
588
+
compatible = "brcm,iproc-rng200";
589
+
reg = <0xb80 0x28>;
590
+
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
591
+
};
592
+
678
593
hsspi: spi@1000 {
679
594
#address-cells = <1>;
680
595
#size-cells = <0>;
···
732
635
reg = <0x44 0x04>;
733
636
#reset-cells = <1>;
734
637
};
638
+
};
639
+
640
+
pl081_dma: dma-controller@59000 {
641
+
compatible = "arm,pl081", "arm,primecell";
642
+
// The magic B105F00D info is missing
643
+
arm,primecell-periphid = <0x00041081>;
644
+
reg = <0x59000 0x1000>;
645
+
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
646
+
memcpy-burst-size = <256>;
647
+
memcpy-bus-width = <32>;
648
+
clocks = <&periph_clk>;
649
+
clock-names = "apb_pclk";
650
+
#dma-cells = <2>;
735
651
};
736
652
};
737
653
+129
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+129
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
···
1
1
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
2
/*
3
3
* Copyright 2022 Broadcom Ltd.
4
+
* This DTSI is for the B0 and later revision of the SoC
4
5
*/
5
6
6
7
#include <dt-bindings/interrupt-controller/irq.h>
···
126
125
#size-cells = <1>;
127
126
ranges = <0x0 0x0 0xff800000 0x800000>;
128
127
128
+
/* GPIOs 0 .. 31 */
129
+
gpio0: gpio@500 {
130
+
compatible = "brcm,bcm6345-gpio";
131
+
reg = <0x500 0x04>, <0x520 0x04>;
132
+
reg-names = "dirout", "dat";
133
+
gpio-controller;
134
+
#gpio-cells = <2>;
135
+
status = "disabled";
136
+
};
137
+
138
+
/* GPIOs 32 .. 63 */
139
+
gpio1: gpio@504 {
140
+
compatible = "brcm,bcm6345-gpio";
141
+
reg = <0x504 0x04>, <0x524 0x04>;
142
+
reg-names = "dirout", "dat";
143
+
gpio-controller;
144
+
#gpio-cells = <2>;
145
+
status = "disabled";
146
+
};
147
+
148
+
/* GPIOs 64 .. 95 */
149
+
gpio2: gpio@508 {
150
+
compatible = "brcm,bcm6345-gpio";
151
+
reg = <0x508 0x04>, <0x528 0x04>;
152
+
reg-names = "dirout", "dat";
153
+
gpio-controller;
154
+
#gpio-cells = <2>;
155
+
status = "disabled";
156
+
};
157
+
158
+
/* GPIOs 96 .. 127 */
159
+
gpio3: gpio@50c {
160
+
compatible = "brcm,bcm6345-gpio";
161
+
reg = <0x50c 0x04>, <0x52c 0x04>;
162
+
reg-names = "dirout", "dat";
163
+
gpio-controller;
164
+
#gpio-cells = <2>;
165
+
status = "disabled";
166
+
};
167
+
168
+
/* GPIOs 128 .. 159 */
169
+
gpio4: gpio@510 {
170
+
compatible = "brcm,bcm6345-gpio";
171
+
reg = <0x510 0x04>, <0x530 0x04>;
172
+
reg-names = "dirout", "dat";
173
+
gpio-controller;
174
+
#gpio-cells = <2>;
175
+
status = "disabled";
176
+
};
177
+
178
+
/* GPIOs 160 .. 191 */
179
+
gpio5: gpio@514 {
180
+
compatible = "brcm,bcm6345-gpio";
181
+
reg = <0x514 0x04>, <0x534 0x04>;
182
+
reg-names = "dirout", "dat";
183
+
gpio-controller;
184
+
#gpio-cells = <2>;
185
+
status = "disabled";
186
+
};
187
+
188
+
/* GPIOs 192 .. 223 */
189
+
gpio6: gpio@518 {
190
+
compatible = "brcm,bcm6345-gpio";
191
+
reg = <0x518 0x04>, <0x538 0x04>;
192
+
reg-names = "dirout", "dat";
193
+
gpio-controller;
194
+
#gpio-cells = <2>;
195
+
status = "disabled";
196
+
};
197
+
198
+
/* GPIOs 224 .. 255 */
199
+
gpio7: gpio@51c {
200
+
compatible = "brcm,bcm6345-gpio";
201
+
reg = <0x51c 0x04>, <0x53c 0x04>;
202
+
reg-names = "dirout", "dat";
203
+
gpio-controller;
204
+
#gpio-cells = <2>;
205
+
status = "disabled";
206
+
};
207
+
208
+
209
+
leds: led-controller@800 {
210
+
#address-cells = <1>;
211
+
#size-cells = <0>;
212
+
compatible = "brcm,bcm63138-leds";
213
+
reg = <0x800 0xdc>;
214
+
status = "disabled";
215
+
};
216
+
217
+
rng@b80 {
218
+
compatible = "brcm,iproc-rng200";
219
+
reg = <0xb80 0x28>;
220
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
221
+
};
222
+
129
223
hsspi: spi@1000 {
130
224
#address-cells = <1>;
131
225
#size-cells = <0>;
···
247
151
};
248
152
};
249
153
154
+
/* B0 AHB Peripherals */
155
+
pl081_dma: dma-controller@11000 {
156
+
compatible = "arm,pl081", "arm,primecell";
157
+
// The magic B105F00D info is missing
158
+
arm,primecell-periphid = <0x00041081>;
159
+
reg = <0x11000 0x1000>;
160
+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
161
+
memcpy-burst-size = <256>;
162
+
memcpy-bus-width = <32>;
163
+
clocks = <&periph_clk>;
164
+
clock-names = "apb_pclk";
165
+
#dma-cells = <2>;
166
+
};
167
+
168
+
/* B0 ARM UART Peripheral block */
250
169
uart0: serial@12000 {
251
170
compatible = "arm,pl011", "arm,primecell";
252
171
reg = <0x12000 0x1000>;
253
172
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
173
+
clocks = <&uart_clk>, <&uart_clk>;
174
+
clock-names = "uartclk", "apb_pclk";
175
+
status = "disabled";
176
+
};
177
+
178
+
uart1: serial@13000 {
179
+
compatible = "arm,pl011", "arm,primecell";
180
+
reg = <0x13000 0x1000>;
181
+
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182
+
clocks = <&uart_clk>, <&uart_clk>;
183
+
clock-names = "uartclk", "apb_pclk";
184
+
status = "disabled";
185
+
};
186
+
187
+
uart2: serial@14000 {
188
+
compatible = "arm,pl011", "arm,primecell";
189
+
reg = <0x14000 0x1000>;
190
+
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
254
191
clocks = <&uart_clk>, <&uart_clk>;
255
192
clock-names = "uartclk", "apb_pclk";
256
193
status = "disabled";
+129
-1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+129
-1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
···
93
93
};
94
94
};
95
95
96
+
/* PERF Peripherals */
96
97
bus@ff800000 {
97
98
compatible = "simple-bus";
98
99
#address-cells = <1>;
99
100
#size-cells = <1>;
100
-
ranges = <0x0 0x0 0xff800000 0x800000>;
101
+
ranges = <0x0 0x0 0xff800000 0x400000>;
102
+
103
+
watchdog@480 {
104
+
compatible = "brcm,bcm6345-wdt";
105
+
reg = <0x480 0x10>;
106
+
};
107
+
108
+
watchdog@4c0 {
109
+
compatible = "brcm,bcm6345-wdt";
110
+
reg = <0x4c0 0x10>;
111
+
status = "disabled";
112
+
};
113
+
114
+
/* GPIOs 0 .. 31 */
115
+
gpio0: gpio@500 {
116
+
compatible = "brcm,bcm6345-gpio";
117
+
reg = <0x500 0x04>, <0x520 0x04>;
118
+
reg-names = "dirout", "dat";
119
+
gpio-controller;
120
+
#gpio-cells = <2>;
121
+
status = "disabled";
122
+
};
123
+
124
+
/* GPIOs 32 .. 63 */
125
+
gpio1: gpio@504 {
126
+
compatible = "brcm,bcm6345-gpio";
127
+
reg = <0x504 0x04>, <0x524 0x04>;
128
+
reg-names = "dirout", "dat";
129
+
gpio-controller;
130
+
#gpio-cells = <2>;
131
+
status = "disabled";
132
+
};
133
+
134
+
/* GPIOs 64 .. 95 */
135
+
gpio2: gpio@508 {
136
+
compatible = "brcm,bcm6345-gpio";
137
+
reg = <0x508 0x04>, <0x528 0x04>;
138
+
reg-names = "dirout", "dat";
139
+
gpio-controller;
140
+
#gpio-cells = <2>;
141
+
status = "disabled";
142
+
};
143
+
144
+
/* GPIOs 96 .. 127 */
145
+
gpio3: gpio@50c {
146
+
compatible = "brcm,bcm6345-gpio";
147
+
reg = <0x50c 0x04>, <0x52c 0x04>;
148
+
reg-names = "dirout", "dat";
149
+
gpio-controller;
150
+
#gpio-cells = <2>;
151
+
status = "disabled";
152
+
};
153
+
154
+
/* GPIOs 128 .. 159 */
155
+
gpio4: gpio@510 {
156
+
compatible = "brcm,bcm6345-gpio";
157
+
reg = <0x510 0x04>, <0x530 0x04>;
158
+
reg-names = "dirout", "dat";
159
+
gpio-controller;
160
+
#gpio-cells = <2>;
161
+
status = "disabled";
162
+
};
163
+
164
+
/* GPIOs 160 .. 191 */
165
+
gpio5: gpio@514 {
166
+
compatible = "brcm,bcm6345-gpio";
167
+
reg = <0x514 0x04>, <0x534 0x04>;
168
+
reg-names = "dirout", "dat";
169
+
gpio-controller;
170
+
#gpio-cells = <2>;
171
+
status = "disabled";
172
+
};
173
+
174
+
/* GPIOs 192 .. 223 */
175
+
gpio6: gpio@518 {
176
+
compatible = "brcm,bcm6345-gpio";
177
+
reg = <0x518 0x04>, <0x538 0x04>;
178
+
reg-names = "dirout", "dat";
179
+
gpio-controller;
180
+
#gpio-cells = <2>;
181
+
status = "disabled";
182
+
};
183
+
184
+
/* GPIOs 224 .. 255 */
185
+
gpio7: gpio@51c {
186
+
compatible = "brcm,bcm6345-gpio";
187
+
reg = <0x51c 0x04>, <0x53c 0x04>;
188
+
reg-names = "dirout", "dat";
189
+
gpio-controller;
190
+
#gpio-cells = <2>;
191
+
status = "disabled";
192
+
};
101
193
102
194
uart0: serial@640 {
103
195
compatible = "brcm,bcm6345-uart";
···
198
106
clocks = <&periph_clk>;
199
107
clock-names = "refclk";
200
108
status = "disabled";
109
+
};
110
+
111
+
uart1: serial@660 {
112
+
compatible = "brcm,bcm6345-uart";
113
+
reg = <0x660 0x18>;
114
+
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
115
+
clocks = <&periph_clk>;
116
+
clock-names = "refclk";
117
+
status = "disabled";
118
+
};
119
+
120
+
leds: led-controller@800 {
121
+
#address-cells = <1>;
122
+
#size-cells = <0>;
123
+
compatible = "brcm,bcm63138-leds";
124
+
reg = <0x800 0xdc>;
125
+
status = "disabled";
126
+
};
127
+
128
+
rng@b80 {
129
+
compatible = "brcm,iproc-rng200";
130
+
reg = <0xb80 0x28>;
131
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
201
132
};
202
133
203
134
hsspi: spi@1000 {
···
247
132
compatible = "brcm,nandcs";
248
133
reg = <0>;
249
134
};
135
+
};
136
+
137
+
pl081_dma: dma-controller@59000 {
138
+
compatible = "arm,pl081", "arm,primecell";
139
+
// The magic B105F00D info is missing
140
+
arm,primecell-periphid = <0x00041081>;
141
+
reg = <0x59000 0x1000>;
142
+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
143
+
memcpy-burst-size = <256>;
144
+
memcpy-bus-width = <32>;
145
+
clocks = <&periph_clk>;
146
+
clock-names = "apb_pclk";
147
+
#dma-cells = <2>;
250
148
};
251
149
};
252
150
};
+118
-1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+118
-1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
···
111
111
};
112
112
};
113
113
114
+
/* PERF Peripherals */
114
115
bus@ff800000 {
115
116
compatible = "simple-bus";
116
117
#address-cells = <1>;
117
118
#size-cells = <1>;
118
-
ranges = <0x0 0x0 0xff800000 0x62000>;
119
+
ranges = <0x0 0x0 0xff800000 0x400000>;
119
120
120
121
twd: timer-mfd@400 {
121
122
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
···
137
136
};
138
137
};
139
138
139
+
/* GPIOs 0 .. 31 */
140
+
gpio0: gpio@500 {
141
+
compatible = "brcm,bcm6345-gpio";
142
+
reg = <0x500 0x04>, <0x520 0x04>;
143
+
reg-names = "dirout", "dat";
144
+
gpio-controller;
145
+
#gpio-cells = <2>;
146
+
status = "disabled";
147
+
};
148
+
149
+
/* GPIOs 32 .. 63 */
150
+
gpio1: gpio@504 {
151
+
compatible = "brcm,bcm6345-gpio";
152
+
reg = <0x504 0x04>, <0x524 0x04>;
153
+
reg-names = "dirout", "dat";
154
+
gpio-controller;
155
+
#gpio-cells = <2>;
156
+
status = "disabled";
157
+
};
158
+
159
+
/* GPIOs 64 .. 95 */
160
+
gpio2: gpio@508 {
161
+
compatible = "brcm,bcm6345-gpio";
162
+
reg = <0x508 0x04>, <0x528 0x04>;
163
+
reg-names = "dirout", "dat";
164
+
gpio-controller;
165
+
#gpio-cells = <2>;
166
+
status = "disabled";
167
+
};
168
+
169
+
/* GPIOs 96 .. 127 */
170
+
gpio3: gpio@50c {
171
+
compatible = "brcm,bcm6345-gpio";
172
+
reg = <0x50c 0x04>, <0x52c 0x04>;
173
+
reg-names = "dirout", "dat";
174
+
gpio-controller;
175
+
#gpio-cells = <2>;
176
+
status = "disabled";
177
+
};
178
+
179
+
/* GPIOs 128 .. 159 */
180
+
gpio4: gpio@510 {
181
+
compatible = "brcm,bcm6345-gpio";
182
+
reg = <0x510 0x04>, <0x530 0x04>;
183
+
reg-names = "dirout", "dat";
184
+
gpio-controller;
185
+
#gpio-cells = <2>;
186
+
status = "disabled";
187
+
};
188
+
189
+
/* GPIOs 160 .. 191 */
190
+
gpio5: gpio@514 {
191
+
compatible = "brcm,bcm6345-gpio";
192
+
reg = <0x514 0x04>, <0x534 0x04>;
193
+
reg-names = "dirout", "dat";
194
+
gpio-controller;
195
+
#gpio-cells = <2>;
196
+
status = "disabled";
197
+
};
198
+
199
+
/* GPIOs 192 .. 223 */
200
+
gpio6: gpio@518 {
201
+
compatible = "brcm,bcm6345-gpio";
202
+
reg = <0x518 0x04>, <0x538 0x04>;
203
+
reg-names = "dirout", "dat";
204
+
gpio-controller;
205
+
#gpio-cells = <2>;
206
+
status = "disabled";
207
+
};
208
+
209
+
/* GPIOs 224 .. 255 */
210
+
gpio7: gpio@51c {
211
+
compatible = "brcm,bcm6345-gpio";
212
+
reg = <0x51c 0x04>, <0x53c 0x04>;
213
+
reg-names = "dirout", "dat";
214
+
gpio-controller;
215
+
#gpio-cells = <2>;
216
+
status = "disabled";
217
+
};
218
+
140
219
uart0: serial@640 {
141
220
compatible = "brcm,bcm6345-uart";
142
221
reg = <0x640 0x18>;
···
224
143
clocks = <&periph_clk>;
225
144
clock-names = "refclk";
226
145
status = "disabled";
146
+
};
147
+
148
+
uart1: serial@660 {
149
+
compatible = "brcm,bcm6345-uart";
150
+
reg = <0x660 0x18>;
151
+
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
152
+
clocks = <&periph_clk>;
153
+
clock-names = "refclk";
154
+
status = "disabled";
155
+
};
156
+
157
+
leds: led-controller@800 {
158
+
#address-cells = <1>;
159
+
#size-cells = <0>;
160
+
compatible = "brcm,bcm63138-leds";
161
+
reg = <0x800 0xdc>;
162
+
status = "disabled";
163
+
};
164
+
165
+
rng@b80 {
166
+
compatible = "brcm,iproc-rng200";
167
+
reg = <0xb80 0x28>;
168
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
227
169
};
228
170
229
171
hsspi: spi@1000 {
···
273
169
compatible = "brcm,nandcs";
274
170
reg = <0>;
275
171
};
172
+
};
173
+
174
+
pl081_dma: dma-controller@59000 {
175
+
compatible = "arm,pl081", "arm,primecell";
176
+
// The magic B105F00D info is missing
177
+
arm,primecell-periphid = <0x00041081>;
178
+
reg = <0x59000 0x1000>;
179
+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
180
+
memcpy-burst-size = <256>;
181
+
memcpy-bus-width = <32>;
182
+
clocks = <&periph_clk>;
183
+
clock-names = "apb_pclk";
184
+
#dma-cells = <2>;
276
185
};
277
186
};
278
187
};
-8
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-8
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
···
367
367
368
368
v2m0: v2m@0 {
369
369
compatible = "arm,gic-v2m-frame";
370
-
interrupt-parent = <&gic>;
371
370
msi-controller;
372
371
reg = <0x00000 0x1000>;
373
372
arm,msi-base-spi = <72>;
···
375
376
376
377
v2m1: v2m@10000 {
377
378
compatible = "arm,gic-v2m-frame";
378
-
interrupt-parent = <&gic>;
379
379
msi-controller;
380
380
reg = <0x10000 0x1000>;
381
381
arm,msi-base-spi = <88>;
···
383
385
384
386
v2m2: v2m@20000 {
385
387
compatible = "arm,gic-v2m-frame";
386
-
interrupt-parent = <&gic>;
387
388
msi-controller;
388
389
reg = <0x20000 0x1000>;
389
390
arm,msi-base-spi = <104>;
···
391
394
392
395
v2m3: v2m@30000 {
393
396
compatible = "arm,gic-v2m-frame";
394
-
interrupt-parent = <&gic>;
395
397
msi-controller;
396
398
reg = <0x30000 0x1000>;
397
399
arm,msi-base-spi = <120>;
···
399
403
400
404
v2m4: v2m@40000 {
401
405
compatible = "arm,gic-v2m-frame";
402
-
interrupt-parent = <&gic>;
403
406
msi-controller;
404
407
reg = <0x40000 0x1000>;
405
408
arm,msi-base-spi = <136>;
···
407
412
408
413
v2m5: v2m@50000 {
409
414
compatible = "arm,gic-v2m-frame";
410
-
interrupt-parent = <&gic>;
411
415
msi-controller;
412
416
reg = <0x50000 0x1000>;
413
417
arm,msi-base-spi = <152>;
···
415
421
416
422
v2m6: v2m@60000 {
417
423
compatible = "arm,gic-v2m-frame";
418
-
interrupt-parent = <&gic>;
419
424
msi-controller;
420
425
reg = <0x60000 0x1000>;
421
426
arm,msi-base-spi = <168>;
···
423
430
424
431
v2m7: v2m@70000 {
425
432
compatible = "arm,gic-v2m-frame";
426
-
interrupt-parent = <&gic>;
427
433
msi-controller;
428
434
reg = <0x70000 0x1000>;
429
435
arm,msi-base-spi = <184>;
+42
arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+42
arch/arm64/boot/dts/broadcom/rp1-common.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
3
+
#include <dt-bindings/gpio/gpio.h>
4
+
#include <dt-bindings/interrupt-controller/irq.h>
5
+
#include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
6
+
7
+
pci_ep_bus: pci-ep-bus@1 {
8
+
compatible = "simple-bus";
9
+
ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>;
10
+
dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>;
11
+
#address-cells = <2>;
12
+
#size-cells = <2>;
13
+
14
+
rp1_clocks: clocks@40018000 {
15
+
compatible = "raspberrypi,rp1-clocks";
16
+
reg = <0x00 0x40018000 0x0 0x10038>;
17
+
#clock-cells = <1>;
18
+
clocks = <&clk_rp1_xosc>;
19
+
assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>,
20
+
<&rp1_clocks RP1_PLL_SYS>,
21
+
<&rp1_clocks RP1_PLL_SYS_SEC>,
22
+
<&rp1_clocks RP1_CLK_SYS>;
23
+
assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE
24
+
<200000000>, // RP1_PLL_SYS
25
+
<125000000>, // RP1_PLL_SYS_SEC
26
+
<200000000>; // RP1_CLK_SYS
27
+
};
28
+
29
+
rp1_gpio: pinctrl@400d0000 {
30
+
compatible = "raspberrypi,rp1-gpio";
31
+
reg = <0x00 0x400d0000 0x0 0xc000>,
32
+
<0x00 0x400e0000 0x0 0xc000>,
33
+
<0x00 0x400f0000 0x0 0xc000>;
34
+
gpio-controller;
35
+
#gpio-cells = <2>;
36
+
interrupt-controller;
37
+
#interrupt-cells = <2>;
38
+
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
39
+
<1 IRQ_TYPE_LEVEL_HIGH>,
40
+
<2 IRQ_TYPE_LEVEL_HIGH>;
41
+
};
42
+
};
+14
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
+14
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
3
+
rp1_nexus {
4
+
compatible = "pci1de4,1";
5
+
#address-cells = <3>;
6
+
#size-cells = <2>;
7
+
ranges = <0x01 0x00 0x00000000
8
+
0x02000000 0x00 0x00000000
9
+
0x0 0x400000>;
10
+
interrupt-controller;
11
+
#interrupt-cells = <2>;
12
+
13
+
#include "rp1-common.dtsi"
14
+
};
+11
arch/arm64/boot/dts/broadcom/rp1.dtso
+11
arch/arm64/boot/dts/broadcom/rp1.dtso
+61
include/dt-bindings/clock/raspberrypi,rp1-clocks.h
+61
include/dt-bindings/clock/raspberrypi,rp1-clocks.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2021 Raspberry Pi Ltd.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
7
+
#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
8
+
9
+
#define RP1_PLL_SYS_CORE 0
10
+
#define RP1_PLL_AUDIO_CORE 1
11
+
#define RP1_PLL_VIDEO_CORE 2
12
+
13
+
#define RP1_PLL_SYS 3
14
+
#define RP1_PLL_AUDIO 4
15
+
#define RP1_PLL_VIDEO 5
16
+
17
+
#define RP1_PLL_SYS_PRI_PH 6
18
+
#define RP1_PLL_SYS_SEC_PH 7
19
+
#define RP1_PLL_AUDIO_PRI_PH 8
20
+
21
+
#define RP1_PLL_SYS_SEC 9
22
+
#define RP1_PLL_AUDIO_SEC 10
23
+
#define RP1_PLL_VIDEO_SEC 11
24
+
25
+
#define RP1_CLK_SYS 12
26
+
#define RP1_CLK_SLOW_SYS 13
27
+
#define RP1_CLK_DMA 14
28
+
#define RP1_CLK_UART 15
29
+
#define RP1_CLK_ETH 16
30
+
#define RP1_CLK_PWM0 17
31
+
#define RP1_CLK_PWM1 18
32
+
#define RP1_CLK_AUDIO_IN 19
33
+
#define RP1_CLK_AUDIO_OUT 20
34
+
#define RP1_CLK_I2S 21
35
+
#define RP1_CLK_MIPI0_CFG 22
36
+
#define RP1_CLK_MIPI1_CFG 23
37
+
#define RP1_CLK_PCIE_AUX 24
38
+
#define RP1_CLK_USBH0_MICROFRAME 25
39
+
#define RP1_CLK_USBH1_MICROFRAME 26
40
+
#define RP1_CLK_USBH0_SUSPEND 27
41
+
#define RP1_CLK_USBH1_SUSPEND 28
42
+
#define RP1_CLK_ETH_TSU 29
43
+
#define RP1_CLK_ADC 30
44
+
#define RP1_CLK_SDIO_TIMER 31
45
+
#define RP1_CLK_SDIO_ALT_SRC 32
46
+
#define RP1_CLK_GP0 33
47
+
#define RP1_CLK_GP1 34
48
+
#define RP1_CLK_GP2 35
49
+
#define RP1_CLK_GP3 36
50
+
#define RP1_CLK_GP4 37
51
+
#define RP1_CLK_GP5 38
52
+
#define RP1_CLK_VEC 39
53
+
#define RP1_CLK_DPI 40
54
+
#define RP1_CLK_MIPI0_DPI 41
55
+
#define RP1_CLK_MIPI1_DPI 42
56
+
57
+
/* Extra PLL output channels - RP1B0 only */
58
+
#define RP1_PLL_VIDEO_PRI_PH 43
59
+
#define RP1_PLL_AUDIO_TERN 44
60
+
61
+
#endif