tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: tegra: Fix PLLP rate table
This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
authored by
Gabe Black
and committed by
Peter De Schrijver
2ec35fd5
2edf3e03
+5
-5
+5
-5
drivers/clk/tegra/clk-tegra124.c
+5
-5
drivers/clk/tegra/clk-tegra124.c
···
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};
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static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
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-
{12000000, 216000000, 432, 12, 1, 8},
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{13000000, 216000000, 432, 13, 1, 8},
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{16800000, 216000000, 360, 14, 1, 8},
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{19200000, 216000000, 360, 16, 1, 8},
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{26000000, 216000000, 432, 26, 1, 8},
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+
{12000000, 408000000, 408, 12, 0, 8},
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{13000000, 408000000, 408, 13, 0, 8},
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+
{16800000, 408000000, 340, 14, 0, 8},
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{19200000, 408000000, 340, 16, 0, 8},
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{26000000, 408000000, 408, 26, 0, 8},
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{0, 0, 0, 0, 0, 0},
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};
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