tjh.dev / kernel
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[ARM] 4503/1: nommu: Add noMMU support for ARMv7

This patch adds the necessary ifdef's to the proc-v7.S code and
defines the v7wbi_tlb_fns macro in pgtable-nommu.h

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by Catalin Marinas and committed by Russell King 2eb8c82b 7092fc38

+16 -12
unified split
+1 -1
arch/arm/mm/Kconfig
··· 377 377 select CPU_CACHE_V7 378 378 select CPU_CACHE_VIPT 379 379 select CPU_CP15_MMU 380 - select CPU_HAS_ASID 380 + select CPU_HAS_ASID if MMU 381 381 select CPU_COPY_V6 if MMU 382 382 select CPU_TLB_V7 if MMU 383 383
+14 -11
arch/arm/mm/proc-v7.S
··· 77 77 * - we are not using split page tables 78 78 */ 79 79 ENTRY(cpu_v7_switch_mm) 80 + #ifdef CONFIG_MMU 80 81 mov r2, #0 81 82 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 82 83 orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB ··· 87 86 isb 88 87 mcr p15, 0, r1, c13, c0, 1 @ set context ID 89 88 isb 89 + #endif 90 90 mov pc, lr 91 91 92 92 /* ··· 111 109 * 1111 0 1 1 r/w r/w 112 110 */ 113 111 ENTRY(cpu_v7_set_pte_ext) 112 + #ifdef CONFIG_MMU 114 113 str r1, [r0], #-2048 @ linux version 115 114 116 115 bic r3, r1, #0x000003f0 ··· 139 136 140 137 str r3, [r0] 141 138 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 139 + #endif 142 140 mov pc, lr 143 141 144 142 cpu_v7_name: ··· 173 169 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 174 170 #endif 175 171 dsb 172 + #ifdef CONFIG_MMU 176 173 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 177 174 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 178 175 orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB ··· 181 176 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 182 177 mov r10, #0x1f @ domains 0, 1 = manager 183 178 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 184 - mrc p15, 0, r0, c1, c0, 0 @ read control register 185 - ldr r10, cr1_clear @ get mask for bits to clear 186 - bic r0, r0, r10 @ clear bits them 187 - ldr r10, cr1_set @ get mask for bits to set 188 - orr r0, r0, r10 @ set them 179 + #endif 180 + adr r5, v7_crval 181 + ldmia r5, {r5, r6} 182 + mrc p15, 0, r0, c1, c0, 0 @ read control register 183 + bic r0, r0, r5 @ clear bits them 184 + orr r0, r0, r6 @ set them 189 185 mov pc, lr @ return to head.S:__ret 190 186 191 187 /* ··· 195 189 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 196 190 * 0 110 0011 1.00 .111 1101 < we want 197 191 */ 198 - .type cr1_clear, #object 199 - .type cr1_set, #object 200 - cr1_clear: 201 - .word 0x0120c302 202 - cr1_set: 203 - .word 0x00c0387d 192 + .type v7_crval, #object 193 + v7_crval: 194 + crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c 204 195 205 196 __v7_setup_stack: 206 197 .space 4 * 11 @ 11 registers
+1
include/asm-arm/pgtable-nommu.h
··· 103 103 #define v4wb_tlb_fns (0) 104 104 #define v4wbi_tlb_fns (0) 105 105 #define v6wbi_tlb_fns (0) 106 + #define v7wbi_tlb_fns (0) 106 107 107 108 #define v3_user_fns (0) 108 109 #define v4_user_fns (0)