tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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media: h264: Use v4l2_h264_reference for reflist

In preparation for adding field decoding support, convert the byte arrays
for reflist into array of struct v4l2_h264_reference. That struct will
allow us to mark which field of the reference picture is being referenced.

[hverkuil: top_field_order_cnt -> pic_order_count]

Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

authored by

Nicolas Dufresne and committed by
Mauro Carvalho Chehab 2e2c3d6c 4d52db40

+167 -132
+17 -4
drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.c
··· 12 12 #define GET_MTK_VDEC_PARAM(param) \ 13 13 { dst_param->param = src_param->param; } 14 14 15 - /* 16 - * The firmware expects unused reflist entries to have the value 0x20. 17 - */ 18 - void mtk_vdec_h264_fixup_ref_list(u8 *ref_list, size_t num_valid) 15 + void mtk_vdec_h264_get_ref_list(u8 *ref_list, 16 + const struct v4l2_h264_reference *v4l2_ref_list, 17 + int num_valid) 19 18 { 19 + u32 i; 20 + 21 + /* 22 + * TODO The firmware does not support field decoding. Future 23 + * implementation must use v4l2_ref_list[i].fields to obtain 24 + * the reference field parity. 25 + */ 26 + 27 + for (i = 0; i < num_valid; i++) 28 + ref_list[i] = v4l2_ref_list[i].index; 29 + 30 + /* 31 + * The firmware expects unused reflist entries to have the value 0x20. 32 + */ 20 33 memset(&ref_list[num_valid], 0x20, 32 - num_valid); 21 34 } 22 35
+7 -4
drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.h
··· 164 164 }; 165 165 166 166 /** 167 - * mtk_vdec_h264_fixup_ref_list - fixup unused reference to 0x20. 167 + * mtk_vdec_h264_get_ref_list - translate V4L2 reference list 168 168 * 169 - * @ref_list: reference picture list 170 - * @num_valid: used reference number 169 + * @ref_list: Mediatek reference picture list 170 + * @v4l2_ref_list: V4L2 reference picture list 171 + * @num_valid: used reference number 171 172 */ 172 - void mtk_vdec_h264_fixup_ref_list(u8 *ref_list, size_t num_valid); 173 + void mtk_vdec_h264_get_ref_list(u8 *ref_list, 174 + const struct v4l2_h264_reference *v4l2_ref_list, 175 + int num_valid); 173 176 174 177 /** 175 178 * mtk_vdec_h264_get_ctrl_ptr - get each CID contrl address.
+10 -5
drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c
··· 102 102 const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; 103 103 struct mtk_h264_dec_slice_param *slice_param = &inst->h264_slice_param; 104 104 struct v4l2_h264_reflist_builder reflist_builder; 105 + struct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN]; 106 + struct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN]; 107 + struct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN]; 105 108 u8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0; 106 109 u8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0; 107 110 u8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1; ··· 140 137 /* Build the reference lists */ 141 138 v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, 142 139 inst->dpb); 143 - v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); 144 - v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); 140 + v4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist); 141 + v4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, 142 + v4l2_b1_reflist); 143 + 145 144 /* Adapt the built lists to the firmware's expectations */ 146 - mtk_vdec_h264_fixup_ref_list(p0_reflist, reflist_builder.num_valid); 147 - mtk_vdec_h264_fixup_ref_list(b0_reflist, reflist_builder.num_valid); 148 - mtk_vdec_h264_fixup_ref_list(b1_reflist, reflist_builder.num_valid); 145 + mtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid); 146 + mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); 147 + mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); 149 148 150 149 memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, 151 150 sizeof(inst->vsi_ctx.h264_slice_params));
+17 -10
drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c
··· 222 222 const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; 223 223 struct vdec_h264_slice_lat_dec_param *slice_param = &inst->h264_slice_param; 224 224 struct v4l2_h264_reflist_builder reflist_builder; 225 + struct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN]; 226 + struct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN]; 227 + struct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN]; 225 228 u8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0; 226 229 u8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0; 227 230 u8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1; ··· 259 256 260 257 /* Build the reference lists */ 261 258 v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, inst->dpb); 262 - v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); 259 + v4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist); 260 + v4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, v4l2_b1_reflist); 263 261 264 - v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); 265 262 /* Adapt the built lists to the firmware's expectations */ 266 - mtk_vdec_h264_fixup_ref_list(p0_reflist, reflist_builder.num_valid); 267 - mtk_vdec_h264_fixup_ref_list(b0_reflist, reflist_builder.num_valid); 268 - mtk_vdec_h264_fixup_ref_list(b1_reflist, reflist_builder.num_valid); 263 + mtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid); 264 + mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); 265 + mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); 266 + 269 267 memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, 270 268 sizeof(inst->vsi_ctx.h264_slice_params)); 271 269 ··· 280 276 struct v4l2_ctrl_h264_decode_params *dec_params = &share_info->dec_params; 281 277 struct v4l2_ctrl_h264_sps *sps = &share_info->sps; 282 278 struct v4l2_h264_reflist_builder reflist_builder; 279 + struct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN]; 280 + struct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN]; 281 + struct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN]; 283 282 u8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0; 284 283 u8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0; 285 284 u8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1; ··· 298 291 /* Build the reference lists */ 299 292 v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, 300 293 inst->dpb); 301 - v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); 302 - v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); 294 + v4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist); 295 + v4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, v4l2_b1_reflist); 303 296 304 297 /* Adapt the built lists to the firmware's expectations */ 305 - mtk_vdec_h264_fixup_ref_list(p0_reflist, reflist_builder.num_valid); 306 - mtk_vdec_h264_fixup_ref_list(b0_reflist, reflist_builder.num_valid); 307 - mtk_vdec_h264_fixup_ref_list(b1_reflist, reflist_builder.num_valid); 298 + mtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid); 299 + mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); 300 + mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); 308 301 } 309 302 310 303 static int vdec_h264_slice_alloc_mv_buf(struct vdec_h264_slice_inst *inst,
+12 -7
drivers/media/platform/nvidia/tegra-vde/h264.c
··· 45 45 }; 46 46 47 47 struct h264_reflists { 48 - u8 p[V4L2_H264_NUM_DPB_ENTRIES]; 49 - u8 b0[V4L2_H264_NUM_DPB_ENTRIES]; 50 - u8 b1[V4L2_H264_NUM_DPB_ENTRIES]; 48 + struct v4l2_h264_reference p[V4L2_H264_NUM_DPB_ENTRIES]; 49 + struct v4l2_h264_reference b0[V4L2_H264_NUM_DPB_ENTRIES]; 50 + struct v4l2_h264_reference b1[V4L2_H264_NUM_DPB_ENTRIES]; 51 51 }; 52 52 53 53 static int tegra_vde_wait_mbe(struct tegra_vde *vde) ··· 765 765 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(&dst->vb2_buf); 766 766 struct tegra_ctx_h264 *h = &ctx->h264; 767 767 struct v4l2_h264_reflist_builder b; 768 + struct v4l2_h264_reference *dpb_id; 768 769 struct h264_reflists reflists; 769 770 struct vb2_buffer *ref; 770 771 unsigned int i; 771 - u8 *dpb_id; 772 772 int err; 773 773 774 774 /* ··· 811 811 } 812 812 813 813 for (i = 0; i < b.num_valid; i++) { 814 - ref = get_ref_buf(ctx, dst, dpb_id[i]); 814 + int dpb_idx = dpb_id[i].index; 815 815 816 - err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_id[i], 816 + ref = get_ref_buf(ctx, dst, dpb_idx); 817 + 818 + err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_idx, 817 819 h264->dpb_frames_nb++); 818 820 if (err) 819 821 return err; 820 822 821 - if (b.refs[dpb_id[i]].pic_order_count < b.cur_pic_order_count) 823 + if (b.refs[dpb_idx].pic_order_count < b.cur_pic_order_count) 822 824 h264->dpb_ref_frames_with_earlier_poc_nb++; 823 825 } 824 826 ··· 880 878 881 879 /* CABAC unsupported by hardware, requires software preprocessing */ 882 880 if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) 881 + return -EOPNOTSUPP; 882 + 883 + if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) 883 884 return -EOPNOTSUPP; 884 885 885 886 if (h->sps->profile_idc == 66)
+17 -16
drivers/media/v4l2-core/v4l2-h264.c
··· 75 75 pic_order_count = dpb[i].top_field_order_cnt; 76 76 77 77 b->refs[i].pic_order_count = pic_order_count; 78 - b->unordered_reflist[b->num_valid] = i; 78 + b->unordered_reflist[b->num_valid].index = i; 79 79 b->num_valid++; 80 80 } 81 81 82 82 for (i = b->num_valid; i < ARRAY_SIZE(b->unordered_reflist); i++) 83 - b->unordered_reflist[i] = i; 83 + b->unordered_reflist[i].index = i; 84 84 } 85 85 EXPORT_SYMBOL_GPL(v4l2_h264_init_reflist_builder); 86 86 ··· 90 90 const struct v4l2_h264_reflist_builder *builder = data; 91 91 u8 idxa, idxb; 92 92 93 - idxa = *((u8 *)ptra); 94 - idxb = *((u8 *)ptrb); 93 + idxa = ((struct v4l2_h264_reference *)ptra)->index; 94 + idxb = ((struct v4l2_h264_reference *)ptrb)->index; 95 95 96 96 if (WARN_ON(idxa >= V4L2_H264_NUM_DPB_ENTRIES || 97 97 idxb >= V4L2_H264_NUM_DPB_ENTRIES)) ··· 125 125 s32 poca, pocb; 126 126 u8 idxa, idxb; 127 127 128 - idxa = *((u8 *)ptra); 129 - idxb = *((u8 *)ptrb); 128 + idxa = ((struct v4l2_h264_reference *)ptra)->index; 129 + idxb = ((struct v4l2_h264_reference *)ptrb)->index; 130 130 131 131 if (WARN_ON(idxa >= V4L2_H264_NUM_DPB_ENTRIES || 132 132 idxb >= V4L2_H264_NUM_DPB_ENTRIES)) ··· 170 170 s32 poca, pocb; 171 171 u8 idxa, idxb; 172 172 173 - idxa = *((u8 *)ptra); 174 - idxb = *((u8 *)ptrb); 173 + idxa = ((struct v4l2_h264_reference *)ptra)->index; 174 + idxb = ((struct v4l2_h264_reference *)ptrb)->index; 175 175 176 176 if (WARN_ON(idxa >= V4L2_H264_NUM_DPB_ENTRIES || 177 177 idxb >= V4L2_H264_NUM_DPB_ENTRIES)) ··· 212 212 * v4l2_h264_build_p_ref_list() - Build the P reference list 213 213 * 214 214 * @builder: reference list builder context 215 - * @reflist: 16-bytes array used to store the P reference list. Each entry 216 - * is an index in the DPB 215 + * @reflist: 16 sized array used to store the P reference list. Each entry 216 + * is a v4l2_h264_reference structure 217 217 * 218 218 * This functions builds the P reference lists. This procedure is describe in 219 219 * section '8.2.4 Decoding process for reference picture lists construction' ··· 222 222 */ 223 223 void 224 224 v4l2_h264_build_p_ref_list(const struct v4l2_h264_reflist_builder *builder, 225 - u8 *reflist) 225 + struct v4l2_h264_reference *reflist) 226 226 { 227 227 memcpy(reflist, builder->unordered_reflist, 228 228 sizeof(builder->unordered_reflist[0]) * builder->num_valid); ··· 235 235 * v4l2_h264_build_b_ref_lists() - Build the B0/B1 reference lists 236 236 * 237 237 * @builder: reference list builder context 238 - * @b0_reflist: 16-bytes array used to store the B0 reference list. Each entry 239 - * is an index in the DPB 240 - * @b1_reflist: 16-bytes array used to store the B1 reference list. Each entry 241 - * is an index in the DPB 238 + * @b0_reflist: 16 sized array used to store the B0 reference list. Each entry 239 + * is a v4l2_h264_reference structure 240 + * @b1_reflist: 16 sized array used to store the B1 reference list. Each entry 241 + * is a v4l2_h264_reference structure 242 242 * 243 243 * This functions builds the B0/B1 reference lists. This procedure is described 244 244 * in section '8.2.4 Decoding process for reference picture lists construction' ··· 247 247 */ 248 248 void 249 249 v4l2_h264_build_b_ref_lists(const struct v4l2_h264_reflist_builder *builder, 250 - u8 *b0_reflist, u8 *b1_reflist) 250 + struct v4l2_h264_reference *b0_reflist, 251 + struct v4l2_h264_reference *b1_reflist) 251 252 { 252 253 memcpy(b0_reflist, builder->unordered_reflist, 253 254 sizeof(builder->unordered_reflist[0]) * builder->num_valid);
+19 -19
drivers/staging/media/hantro/hantro_g1_h264_dec.c
··· 126 126 127 127 static void set_ref(struct hantro_ctx *ctx) 128 128 { 129 - const u8 *b0_reflist, *b1_reflist, *p_reflist; 129 + const struct v4l2_h264_reference *b0_reflist, *b1_reflist, *p_reflist; 130 130 struct hantro_dev *vpu = ctx->dev; 131 131 int reg_num; 132 132 u32 reg; ··· 157 157 */ 158 158 reg_num = 0; 159 159 for (i = 0; i < 15; i += 3) { 160 - reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i]) | 161 - G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1]) | 162 - G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2]) | 163 - G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i]) | 164 - G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1]) | 165 - G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2]); 160 + reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i].index) | 161 + G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1].index) | 162 + G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2].index) | 163 + G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i].index) | 164 + G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1].index) | 165 + G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2].index); 166 166 vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); 167 167 } 168 168 ··· 171 171 * of forward and backward reference picture lists and first 4 entries 172 172 * of P forward picture list. 173 173 */ 174 - reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15]) | 175 - G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15]) | 176 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0]) | 177 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1]) | 178 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2]) | 179 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3]); 174 + reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15].index) | 175 + G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15].index) | 176 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0].index) | 177 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1].index) | 178 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2].index) | 179 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3].index); 180 180 vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC); 181 181 182 182 /* ··· 185 185 */ 186 186 reg_num = 0; 187 187 for (i = 4; i < HANTRO_H264_DPB_SIZE; i += 6) { 188 - reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i]) | 189 - G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1]) | 190 - G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2]) | 191 - G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3]) | 192 - G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4]) | 193 - G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5]); 188 + reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i].index) | 189 + G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1].index) | 190 + G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2].index) | 191 + G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3].index) | 192 + G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4].index) | 193 + G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5].index); 194 194 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); 195 195 } 196 196
+3 -3
drivers/staging/media/hantro/hantro_hw.h
··· 69 69 * @b1: B1 reflist 70 70 */ 71 71 struct hantro_h264_dec_reflists { 72 - u8 p[HANTRO_H264_DPB_SIZE]; 73 - u8 b0[HANTRO_H264_DPB_SIZE]; 74 - u8 b1[HANTRO_H264_DPB_SIZE]; 72 + struct v4l2_h264_reference p[HANTRO_H264_DPB_SIZE]; 73 + struct v4l2_h264_reference b0[HANTRO_H264_DPB_SIZE]; 74 + struct v4l2_h264_reference b1[HANTRO_H264_DPB_SIZE]; 75 75 }; 76 76 77 77 /**
+49 -49
drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c
··· 298 298 299 299 static void set_ref(struct hantro_ctx *ctx) 300 300 { 301 - const u8 *b0_reflist, *b1_reflist, *p_reflist; 301 + const struct v4l2_h264_reference *b0_reflist, *b1_reflist, *p_reflist; 302 302 struct hantro_dev *vpu = ctx->dev; 303 303 u32 reg; 304 304 int i; ··· 307 307 b1_reflist = ctx->h264_dec.reflists.b1; 308 308 p_reflist = ctx->h264_dec.reflists.p; 309 309 310 - reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) | 311 - VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) | 312 - VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) | 313 - VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) | 314 - VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) | 315 - VDPU_REG_PINIT_RLIST_F4(p_reflist[4]); 310 + reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9].index) | 311 + VDPU_REG_PINIT_RLIST_F8(p_reflist[8].index) | 312 + VDPU_REG_PINIT_RLIST_F7(p_reflist[7].index) | 313 + VDPU_REG_PINIT_RLIST_F6(p_reflist[6].index) | 314 + VDPU_REG_PINIT_RLIST_F5(p_reflist[5].index) | 315 + VDPU_REG_PINIT_RLIST_F4(p_reflist[4].index); 316 316 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); 317 317 318 - reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) | 319 - VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) | 320 - VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) | 321 - VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) | 322 - VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) | 323 - VDPU_REG_PINIT_RLIST_F10(p_reflist[10]); 318 + reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15].index) | 319 + VDPU_REG_PINIT_RLIST_F14(p_reflist[14].index) | 320 + VDPU_REG_PINIT_RLIST_F13(p_reflist[13].index) | 321 + VDPU_REG_PINIT_RLIST_F12(p_reflist[12].index) | 322 + VDPU_REG_PINIT_RLIST_F11(p_reflist[11].index) | 323 + VDPU_REG_PINIT_RLIST_F10(p_reflist[10].index); 324 324 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75)); 325 325 326 326 reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | ··· 355 355 VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); 356 356 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83)); 357 357 358 - reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) | 359 - VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) | 360 - VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) | 361 - VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) | 362 - VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) | 363 - VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]); 358 + reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5].index) | 359 + VDPU_REG_BINIT_RLIST_F4(b0_reflist[4].index) | 360 + VDPU_REG_BINIT_RLIST_F3(b0_reflist[3].index) | 361 + VDPU_REG_BINIT_RLIST_F2(b0_reflist[2].index) | 362 + VDPU_REG_BINIT_RLIST_F1(b0_reflist[1].index) | 363 + VDPU_REG_BINIT_RLIST_F0(b0_reflist[0].index); 364 364 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100)); 365 365 366 - reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) | 367 - VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) | 368 - VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) | 369 - VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) | 370 - VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) | 371 - VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]); 366 + reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11].index) | 367 + VDPU_REG_BINIT_RLIST_F10(b0_reflist[10].index) | 368 + VDPU_REG_BINIT_RLIST_F9(b0_reflist[9].index) | 369 + VDPU_REG_BINIT_RLIST_F8(b0_reflist[8].index) | 370 + VDPU_REG_BINIT_RLIST_F7(b0_reflist[7].index) | 371 + VDPU_REG_BINIT_RLIST_F6(b0_reflist[6].index); 372 372 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101)); 373 373 374 - reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) | 375 - VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) | 376 - VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) | 377 - VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]); 374 + reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15].index) | 375 + VDPU_REG_BINIT_RLIST_F14(b0_reflist[14].index) | 376 + VDPU_REG_BINIT_RLIST_F13(b0_reflist[13].index) | 377 + VDPU_REG_BINIT_RLIST_F12(b0_reflist[12].index); 378 378 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102)); 379 379 380 - reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) | 381 - VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) | 382 - VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) | 383 - VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) | 384 - VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) | 385 - VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]); 380 + reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5].index) | 381 + VDPU_REG_BINIT_RLIST_B4(b1_reflist[4].index) | 382 + VDPU_REG_BINIT_RLIST_B3(b1_reflist[3].index) | 383 + VDPU_REG_BINIT_RLIST_B2(b1_reflist[2].index) | 384 + VDPU_REG_BINIT_RLIST_B1(b1_reflist[1].index) | 385 + VDPU_REG_BINIT_RLIST_B0(b1_reflist[0].index); 386 386 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103)); 387 387 388 - reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) | 389 - VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) | 390 - VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) | 391 - VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) | 392 - VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) | 393 - VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]); 388 + reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11].index) | 389 + VDPU_REG_BINIT_RLIST_B10(b1_reflist[10].index) | 390 + VDPU_REG_BINIT_RLIST_B9(b1_reflist[9].index) | 391 + VDPU_REG_BINIT_RLIST_B8(b1_reflist[8].index) | 392 + VDPU_REG_BINIT_RLIST_B7(b1_reflist[7].index) | 393 + VDPU_REG_BINIT_RLIST_B6(b1_reflist[6].index); 394 394 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104)); 395 395 396 - reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) | 397 - VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) | 398 - VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) | 399 - VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]); 396 + reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15].index) | 397 + VDPU_REG_BINIT_RLIST_B14(b1_reflist[14].index) | 398 + VDPU_REG_BINIT_RLIST_B13(b1_reflist[13].index) | 399 + VDPU_REG_BINIT_RLIST_B12(b1_reflist[12].index); 400 400 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105)); 401 401 402 - reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) | 403 - VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) | 404 - VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) | 405 - VDPU_REG_PINIT_RLIST_F0(p_reflist[0]); 402 + reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3].index) | 403 + VDPU_REG_PINIT_RLIST_F2(p_reflist[2].index) | 404 + VDPU_REG_PINIT_RLIST_F1(p_reflist[1].index) | 405 + VDPU_REG_PINIT_RLIST_F0(p_reflist[0].index); 406 406 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106)); 407 407 408 408 reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm);
+6 -6
drivers/staging/media/rkvdec/rkvdec-h264.c
··· 100 100 #define RKVDEC_H264_DPB_SIZE 16 101 101 102 102 struct rkvdec_h264_reflists { 103 - u8 p[RKVDEC_H264_DPB_SIZE]; 104 - u8 b0[RKVDEC_H264_DPB_SIZE]; 105 - u8 b1[RKVDEC_H264_DPB_SIZE]; 103 + struct v4l2_h264_reference p[RKVDEC_H264_DPB_SIZE]; 104 + struct v4l2_h264_reference b0[RKVDEC_H264_DPB_SIZE]; 105 + struct v4l2_h264_reference b1[RKVDEC_H264_DPB_SIZE]; 106 106 u8 num_valid; 107 107 }; 108 108 ··· 767 767 768 768 switch (j) { 769 769 case 0: 770 - idx = h264_ctx->reflists.p[i]; 770 + idx = h264_ctx->reflists.p[i].index; 771 771 break; 772 772 case 1: 773 - idx = h264_ctx->reflists.b0[i]; 773 + idx = h264_ctx->reflists.b0[i].index; 774 774 break; 775 775 case 2: 776 - idx = h264_ctx->reflists.b1[i]; 776 + idx = h264_ctx->reflists.b1[i].index; 777 777 break; 778 778 } 779 779
+10 -9
include/media/v4l2-h264.h
··· 37 37 u16 longterm : 1; 38 38 } refs[V4L2_H264_NUM_DPB_ENTRIES]; 39 39 s32 cur_pic_order_count; 40 - u8 unordered_reflist[V4L2_H264_NUM_DPB_ENTRIES]; 40 + struct v4l2_h264_reference unordered_reflist[V4L2_H264_NUM_DPB_ENTRIES]; 41 41 u8 num_valid; 42 42 }; 43 43 ··· 51 51 * v4l2_h264_build_b_ref_lists() - Build the B0/B1 reference lists 52 52 * 53 53 * @builder: reference list builder context 54 - * @b0_reflist: 16-bytes array used to store the B0 reference list. Each entry 55 - * is an index in the DPB 56 - * @b1_reflist: 16-bytes array used to store the B1 reference list. Each entry 57 - * is an index in the DPB 54 + * @b0_reflist: 16 sized array used to store the B0 reference list. Each entry 55 + * is a v4l2_h264_reference structure 56 + * @b1_reflist: 16 sized array used to store the B1 reference list. Each entry 57 + * is a v4l2_h264_reference structure 58 58 * 59 59 * This functions builds the B0/B1 reference lists. This procedure is described 60 60 * in section '8.2.4 Decoding process for reference picture lists construction' ··· 63 63 */ 64 64 void 65 65 v4l2_h264_build_b_ref_lists(const struct v4l2_h264_reflist_builder *builder, 66 - u8 *b0_reflist, u8 *b1_reflist); 66 + struct v4l2_h264_reference *b0_reflist, 67 + struct v4l2_h264_reference *b1_reflist); 67 68 68 69 /** 69 70 * v4l2_h264_build_p_ref_list() - Build the P reference list 70 71 * 71 72 * @builder: reference list builder context 72 - * @reflist: 16-bytes array used to store the P reference list. Each entry 73 - * is an index in the DPB 73 + * @reflist: 16 sized array used to store the P reference list. Each entry 74 + * is a v4l2_h264_reference structure 74 75 * 75 76 * This functions builds the P reference lists. This procedure is describe in 76 77 * section '8.2.4 Decoding process for reference picture lists construction' ··· 80 79 */ 81 80 void 82 81 v4l2_h264_build_p_ref_list(const struct v4l2_h264_reflist_builder *builder, 83 - u8 *reflist); 82 + struct v4l2_h264_reference *reflist); 84 83 85 84 #endif /* _MEDIA_V4L2_H264_H */