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linux
[IA64] SGI Altix : fix pcibr_dmamap_ate32() bug
On a SGI Altix TIOCP based PCI bus we need to include the ATE_PIO attribute
bit if we're mapping a 32bit MSI address.
Signed-off-by: Mike Habeck <habeck@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
authored by
Mike Habeck
and committed by
Tony Luck
2e0d232b
8a3a78d1
+9
-4
+6
-2
arch/ia64/sn/pci/pcibr/pcibr_dma.c
+6
-2
arch/ia64/sn/pci/pcibr/pcibr_dma.c
···
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}
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/*
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* If we're mapping for MSI, set the MSI bit in the ATE
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* If we're mapping for MSI, set the MSI bit in the ATE. If it's a
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* TIOCP based pci bus, we also need to set the PIO bit in the ATE.
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*/
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if (dma_flags & SN_DMA_MSI)
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if (dma_flags & SN_DMA_MSI) {
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ate |= PCI32_ATE_MSI;
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if (IS_TIOCP_SOFT(pcibus_info))
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ate |= PCI32_ATE_PIO;
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}
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ate_write(pcibus_info, ate_index, ate_count, ate);
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+3
-2
include/asm-ia64/sn/pcibr_provider.h
+3
-2
include/asm-ia64/sn/pcibr_provider.h
···
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#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
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asic == PCIIO_ASIC_TYPE_TIOCP)
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#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
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#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
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/*
···
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* Bridge PMU Address Transaltion Entry Attibutes
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*/
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#define PCI32_ATE_V (0x1 << 0)
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-
#define PCI32_ATE_CO (0x1 << 1)
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-
#define PCI32_ATE_PREC (0x1 << 2)
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#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
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#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
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#define PCI32_ATE_MSI (0x1 << 2)
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#define PCI32_ATE_PREF (0x1 << 3)
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#define PCI32_ATE_BAR (0x1 << 4)