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[media] ths8200: Format adjustment

Closer inspection on exact transmitted format showed that
we needed to add 1 on vertical sync.

Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Martin Bugge <marbugge@cisco.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

authored by

Martin Bugge and committed by
Mauro Carvalho Chehab 2dfb1c93 00b9f51e

+10 -10
+10 -10
drivers/media/i2c/ths8200.c
··· 318 318 (htotal(bt) >> 8) & 0x1f); 319 319 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); 320 320 321 - /* v sync width transmitted */ 322 - ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); 321 + /* v sync width transmitted (must add 1 to get correct output) */ 322 + ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff); 323 323 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, 324 - ((bt->vsync) >> 2) & 0xc0); 324 + ((bt->vsync + 1) >> 2) & 0xc0); 325 325 326 - /* The pixel value v sync is asserted on */ 326 + /* The pixel value v sync is asserted on (must add 1 to get correct output) */ 327 327 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, 328 - (vtotal(bt)>>8) & 0x7); 329 - ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); 328 + ((vtotal(bt) + 1) >> 8) & 0x7); 329 + ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1); 330 330 331 331 /* For progressive video vlength2 must be set to all 0 and vdly2 must 332 332 * be set to all 1. ··· 336 336 ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); 337 337 338 338 /* Internal delay factors to synchronize the sync pulses and the data */ 339 - /* Experimental values delays (hor 4, ver 1) */ 340 - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); 341 - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); 339 + /* Experimental values delays (hor 0, ver 0) */ 340 + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0); 341 + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0); 342 342 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); 343 - ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); 343 + ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0); 344 344 345 345 /* Polarity of received and transmitted sync signals */ 346 346 if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {