Merge tag 'pinctrl-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

+68 -45

Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml

··· 34 34 the amount of cells must be specified as 2. See the below mentioned gpio 35 35 binding representation for description of particular cells. 36 36 37 + gpio-ranges: 38 + maxItems: 1 39 + 37 40 interrupt-controller: true 38 41 39 42 interrupts: ··· 78 75 function: 79 76 description: 80 77 A string containing the name of the function to mux to the group. 81 - enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, sd, 82 - spi, tdm, uart, watchdog, wifi] 78 + enum: [antsel, emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, 79 + sd, spi, tdm, uart, watchdog, wifi] 83 80 84 81 groups: 85 82 description: ··· 96 93 - if: 97 94 properties: 98 95 function: 96 + const: antsel 97 + then: 98 + properties: 99 + groups: 100 + items: 101 + enum: [antsel0, antsel1, antsel2, antsel3, antsel4, antsel5, 102 + antsel6, antsel7, antsel8, antsel9, antsel10, 103 + antsel11, antsel12, antsel13, antsel14, antsel15, 104 + antsel16, antsel17, antsel18, antsel19, antsel20, 105 + antsel21, antsel22, antsel23, antsel24, antsel25, 106 + antsel26, antsel27, antsel28, antsel29] 107 + - if: 108 + properties: 109 + function: 99 110 const: emmc 100 111 then: 101 112 properties: 102 113 groups: 103 - enum: [emmc, emmc_rst] 114 + items: 115 + enum: [emmc, emmc_rst] 104 116 - if: 105 117 properties: 106 118 function: ··· 123 105 then: 124 106 properties: 125 107 groups: 126 - enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw, 127 - rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio] 108 + items: 109 + enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw, 110 + rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio] 128 111 - if: 129 112 properties: 130 113 function: ··· 142 123 then: 143 124 properties: 144 125 groups: 145 - enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data, 146 - i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws, 147 - i2s1_out_data, i2s2_out_data, i2s3_out_data, 148 - i2s4_out_data] 126 + items: 127 + enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data, 128 + i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws, 129 + i2s1_out_data, i2s2_out_data, i2s3_out_data, 130 + i2s4_out_data] 149 131 - if: 150 132 properties: 151 133 function: ··· 179 159 then: 180 160 properties: 181 161 groups: 182 - enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken, 183 - pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq, 184 - pcie0_pad_perst, pcie1_pad_perst, pcie_pereset, 185 - pcie_wake, pcie_clkreq] 162 + items: 163 + enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken, 164 + pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq, 165 + pcie0_pad_perst, pcie1_pad_perst, pcie_pereset, 166 + pcie_wake, pcie_clkreq] 186 167 - if: 187 168 properties: 188 169 function: ··· 199 178 then: 200 179 properties: 201 180 groups: 202 - enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1, 203 - pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0, 204 - pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1, 205 - pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3, 206 - pwm_ch7_0, pwm_0, pwm_1] 181 + items: 182 + enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1, 183 + pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0, 184 + pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1, 185 + pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3, 186 + pwm_ch7_0, pwm_0, pwm_1] 207 187 - if: 208 188 properties: 209 189 function: ··· 282 260 pins: 283 261 description: 284 262 An array of strings. Each string contains the name of a pin. 285 - enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0, 286 - RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, 287 - I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT, 288 - I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1, 289 - G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2, 290 - G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6, 291 - NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0, 292 - MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1, 293 - MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2, 294 - MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3, 295 - MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL, 296 - PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS, 297 - GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N, 298 - PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2, 299 - AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4, 300 - PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA, 301 - WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4, 302 - WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG, 303 - EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS, 304 - EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N, 305 - WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD, 306 - UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD, 307 - UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N, 308 - PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, 309 - GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK, 310 - TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3, 311 - WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6] 263 + items: 264 + enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0, 265 + RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, 266 + I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT, 267 + I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1, 268 + G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2, 269 + G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6, 270 + NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0, 271 + MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1, 272 + MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2, 273 + MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3, 274 + MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL, 275 + PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS, 276 + GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N, 277 + PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2, 278 + AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4, 279 + PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA, 280 + WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4, 281 + WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG, 282 + EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS, 283 + EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N, 284 + WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD, 285 + UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD, 286 + UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N, 287 + PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, 288 + GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK, 289 + TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3, 290 + WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6] 312 291 313 292 bias-disable: true 314 293

+38

Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml

··· 24 24 - qcom,pm6150-gpio 25 25 - qcom,pm6150l-gpio 26 26 - qcom,pm6350-gpio 27 + - qcom,pm6450-gpio 27 28 - qcom,pm7250b-gpio 28 29 - qcom,pm7325-gpio 29 30 - qcom,pm7550ba-gpio ··· 57 56 - qcom,pma8084-gpio 58 57 - qcom,pmc8180-gpio 59 58 - qcom,pmc8180c-gpio 59 + - qcom,pmd8028-gpio 60 60 - qcom,pmi632-gpio 61 61 - qcom,pmi8950-gpio 62 62 - qcom,pmi8994-gpio 63 63 - qcom,pmi8998-gpio 64 + - qcom,pmih0108-gpio 64 65 - qcom,pmk8350-gpio 65 66 - qcom,pmk8550-gpio 66 67 - qcom,pmm8155au-gpio ··· 75 72 - qcom,pmx55-gpio 76 73 - qcom,pmx65-gpio 77 74 - qcom,pmx75-gpio 75 + - qcom,pmxr2230-gpio 78 76 79 77 - enum: 80 78 - qcom,spmi-gpio ··· 145 141 - qcom,pm8005-gpio 146 142 - qcom,pm8450-gpio 147 143 - qcom,pm8916-gpio 144 + - qcom,pmd8028-gpio 148 145 - qcom,pmk8350-gpio 149 146 - qcom,pmr735a-gpio 150 147 - qcom,pmr735b-gpio ··· 203 198 contains: 204 199 enum: 205 200 - qcom,pm6350-gpio 201 + - qcom,pm6450-gpio 206 202 - qcom,pm8350c-gpio 207 203 then: 208 204 properties: ··· 267 261 - qcom,pmc8180c-gpio 268 262 - qcom,pmp8074-gpio 269 263 - qcom,pms405-gpio 264 + - qcom,pmxr2230-gpio 270 265 then: 271 266 properties: 272 267 gpio-line-names: ··· 306 299 gpio-reserved-ranges: 307 300 minItems: 1 308 301 maxItems: 7 302 + 303 + - if: 304 + properties: 305 + compatible: 306 + contains: 307 + enum: 308 + - qcom,pmih0108-gpio 309 + then: 310 + properties: 311 + gpio-line-names: 312 + minItems: 18 313 + maxItems: 18 314 + gpio-reserved-ranges: 315 + minItems: 1 316 + maxItems: 9 309 317 310 318 - if: 311 319 properties: ··· 424 402 $ref: "#/$defs/qcom-pmic-gpio-state" 425 403 additionalProperties: false 426 404 405 + "-hog(-[0-9]+)?$": 406 + required: 407 + - gpio-hog 408 + 427 409 $defs: 428 410 qcom-pmic-gpio-state: 429 411 type: object ··· 443 417 - gpio1-gpio10 for pm6150 444 418 - gpio1-gpio12 for pm6150l 445 419 - gpio1-gpio9 for pm6350 420 + - gpio1-gpio9 for pm6450 446 421 - gpio1-gpio12 for pm7250b 447 422 - gpio1-gpio10 for pm7325 448 423 - gpio1-gpio8 for pm7550ba ··· 474 447 - gpio1-gpio22 for pm8994 475 448 - gpio1-gpio26 for pm8998 476 449 - gpio1-gpio22 for pma8084 450 + - gpio1-gpio4 for pmd8028 477 451 - gpio1-gpio8 for pmi632 478 452 - gpio1-gpio2 for pmi8950 479 453 - gpio1-gpio10 for pmi8994 454 + - gpio1-gpio18 for pmih0108 480 455 - gpio1-gpio4 for pmk8350 481 456 - gpio1-gpio6 for pmk8550 482 457 - gpio1-gpio10 for pmm8155au ··· 493 464 and gpio11) 494 465 - gpio1-gpio16 for pmx65 495 466 - gpio1-gpio16 for pmx75 467 + - gpio1-gpio12 for pmxr2230 496 468 497 469 items: 498 470 pattern: "^gpio([0-9]+)$" ··· 575 545 576 546 examples: 577 547 - | 548 + #include <dt-bindings/gpio/gpio.h> 578 549 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 579 550 580 551 pm8921_gpio: gpio@150 { ··· 598 567 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 599 568 power-source = <PM8921_GPIO_S4>; 600 569 }; 570 + }; 571 + 572 + otg-hog { 573 + gpio-hog; 574 + gpios = <35 GPIO_ACTIVE_HIGH>; 575 + output-high; 576 + line-name = "otg-gpio"; 601 577 }; 602 578 }; 603 579 ...

+1

Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml

··· 35 35 - qcom,pm8038-mpp 36 36 - qcom,pm8058-mpp 37 37 - qcom,pm8821-mpp 38 + - qcom,pm8901-mpp 38 39 - qcom,pm8917-mpp 39 40 - qcom,pm8921-mpp 40 41 - const: qcom,ssbi-mpp

+18 -34

Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml

··· 72 72 description: 73 73 Specify the alternative function to be configured for the specified 74 74 pins. 75 - enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2, 76 - atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02, 77 - atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c, 78 - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, 79 - cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng, 80 - cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, 81 - dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c, 82 - jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, 83 - mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, 84 - mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, 85 - mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk, 86 - phase_flag0, phase_flag1, phase_flag10, phase_flag11, 87 - phase_flag12, phase_flag13, phase_flag14, phase_flag15, 88 - phase_flag16, phase_flag17, phase_flag18, phase_flag19, 89 - phase_flag2, phase_flag20, phase_flag21, phase_flag22, 90 - phase_flag23, phase_flag24, phase_flag25, phase_flag26, 91 - phase_flag27, phase_flag28, phase_flag29, phase_flag3, 92 - phase_flag30, phase_flag31, phase_flag4, phase_flag5, 93 - phase_flag6, phase_flag7, phase_flag8, phase_flag9, 94 - pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, 95 - prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1, 96 - qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, 97 - qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, 98 - qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, 99 - qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, 100 - qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, 101 - qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, 102 - qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3, 103 - qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0, 104 - tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1, 105 - tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, 106 - uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, 107 - uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1, 108 - vsense_trigger ] 75 + enum: [ gpio, atest_char, atest_usb0, audio_ref_clk, cam_mclk, 76 + cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx, 77 + coex_uart1_tx, cri_trng, dbg_out_clk, ddr_bist, 78 + ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk, gcc_gp2_clk, 79 + gcc_gp3_clk, host2wlan_sol, ibi_i3c_qup0, ibi_i3c_qup1, 80 + jitter_bist_ref, mdp_vsync0_out, mdp_vsync1_out, 81 + mdp_vsync2_out, mdp_vsync3_out, mdp_vsync, nav, 82 + pcie0_clk_req, phase_flag, pll_bist_sync, pll_clk_aux, 83 + prng_rosc, qdss_cti_trig0, qdss_cti_trig1, qdss_gpio, 84 + qlink0_enable, qlink0_request, qlink0_wmss_reset, 85 + qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, 86 + qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2, qup1_se3, 87 + qup1_se4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2, 88 + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, 89 + tgu_ch3_trigout, tmess_prng, tsense_pwm1_out, 90 + tsense_pwm2_out, uim0, uim1, usb0_hs_ac, usb0_phy_ps, 91 + vfr_0_mira, vfr_0_mirb, vfr_1, vsense_trigger_mirnat, 92 + wlan1_adc_dtest0, wlan1_adc_dtest1 ] 109 93 110 94 required: 111 95 - pins

+21

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml

··· 73 73 minItems: 1 74 74 maxItems: 2 75 75 76 + clocks: 77 + maxItems: 1 78 + 79 + clock-names: 80 + items: 81 + - const: pclk 82 + 76 83 wakeup-interrupt-controller: 77 84 $ref: samsung,pinctrl-wakeup-interrupt.yaml 78 85 ··· 127 120 128 121 allOf: 129 122 - $ref: pinctrl.yaml# 123 + - if: 124 + properties: 125 + compatible: 126 + contains: 127 + const: google,gs101-pinctrl 128 + then: 129 + required: 130 + - clocks 131 + - clock-names 132 + else: 133 + properties: 134 + clocks: false 135 + clock-names: false 136 + 130 137 - if: 131 138 properties: 132 139 compatible:

-1

MAINTAINERS

··· 17702 17702 T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git 17703 17703 F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml 17704 17704 F: drivers/pinctrl/samsung/ 17705 - F: include/dt-bindings/pinctrl/samsung.h 17706 17705 17707 17706 PIN CONTROLLER - SINGLE 17708 17707 M: Tony Lindgren <tony@atomide.com>

+76 -7

drivers/pinctrl/bcm/pinctrl-bcm2835.c

··· 244 244 [IRQ_TYPE_LEVEL_LOW] = "level-low", 245 245 }; 246 246 247 + static bool persist_gpio_outputs; 248 + module_param(persist_gpio_outputs, bool, 0644); 249 + MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed"); 250 + 247 251 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 248 252 { 249 253 return readl(pc->base + reg); ··· 930 926 unsigned offset) 931 927 { 932 928 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 929 + enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 930 + 931 + if (fsel == BCM2835_FSEL_GPIO_IN) 932 + return 0; 933 + 934 + if (persist_gpio_outputs && fsel == BCM2835_FSEL_GPIO_OUT) 935 + return 0; 933 936 934 937 /* disable by setting to GPIO_IN */ 935 938 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); ··· 981 970 struct pinctrl_gpio_range *range, 982 971 unsigned offset) 983 972 { 984 - struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 985 - 986 - /* disable by setting to GPIO_IN */ 987 - bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 973 + bcm2835_pmx_free(pctldev, offset); 988 974 } 989 975 990 976 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, ··· 1011 1003 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 1012 1004 unsigned pin, unsigned long *config) 1013 1005 { 1014 - /* No way to read back config in HW */ 1015 - return -ENOTSUPP; 1006 + enum pin_config_param param = pinconf_to_config_param(*config); 1007 + struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1008 + enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, pin); 1009 + u32 val; 1010 + 1011 + /* No way to read back bias config in HW */ 1012 + 1013 + switch (param) { 1014 + case PIN_CONFIG_OUTPUT: 1015 + if (fsel != BCM2835_FSEL_GPIO_OUT) 1016 + return -EINVAL; 1017 + 1018 + val = bcm2835_gpio_get_bit(pc, GPLEV0, pin); 1019 + *config = pinconf_to_config_packed(param, val); 1020 + break; 1021 + 1022 + default: 1023 + return -ENOTSUPP; 1024 + } 1025 + 1026 + return 0; 1016 1027 } 1017 1028 1018 1029 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, ··· 1106 1079 .pin_config_set = bcm2835_pinconf_set, 1107 1080 }; 1108 1081 1082 + static int bcm2711_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 1083 + unsigned long *config) 1084 + { 1085 + struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1086 + enum pin_config_param param = pinconf_to_config_param(*config); 1087 + u32 offset, shift, val; 1088 + 1089 + offset = PUD_2711_REG_OFFSET(pin); 1090 + shift = PUD_2711_REG_SHIFT(pin); 1091 + val = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (offset * 4)); 1092 + 1093 + switch (param) { 1094 + case PIN_CONFIG_BIAS_DISABLE: 1095 + if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_NONE) 1096 + return -EINVAL; 1097 + 1098 + break; 1099 + 1100 + case PIN_CONFIG_BIAS_PULL_UP: 1101 + if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_UP) 1102 + return -EINVAL; 1103 + 1104 + *config = pinconf_to_config_packed(param, 50000); 1105 + break; 1106 + 1107 + case PIN_CONFIG_BIAS_PULL_DOWN: 1108 + if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_DOWN) 1109 + return -EINVAL; 1110 + 1111 + *config = pinconf_to_config_packed(param, 50000); 1112 + break; 1113 + 1114 + default: 1115 + return bcm2835_pinconf_get(pctldev, pin, config); 1116 + } 1117 + 1118 + return 0; 1119 + } 1120 + 1109 1121 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, 1110 1122 unsigned int pin, unsigned int arg) 1111 1123 { ··· 1212 1146 1213 1147 static const struct pinconf_ops bcm2711_pinconf_ops = { 1214 1148 .is_generic = true, 1215 - .pin_config_get = bcm2835_pinconf_get, 1149 + .pin_config_get = bcm2711_pinconf_get, 1216 1150 .pin_config_set = bcm2711_pinconf_set, 1217 1151 }; 1218 1152 ··· 1426 1360 dev_err(dev, "could not add GPIO chip\n"); 1427 1361 goto out_remove; 1428 1362 } 1363 + 1364 + dev_info(dev, "GPIO_OUT persistence: %s\n", 1365 + persist_gpio_outputs ? "yes" : "no"); 1429 1366 1430 1367 return 0; 1431 1368

+1

drivers/pinctrl/freescale/pinctrl-imx8ulp.c

··· 252 252 { .compatible = "fsl,imx8ulp-iomuxc1", }, 253 253 { /* sentinel */ } 254 254 }; 255 + MODULE_DEVICE_TABLE(of, imx8ulp_pinctrl_of_match); 255 256 256 257 static int imx8ulp_pinctrl_probe(struct platform_device *pdev) 257 258 {

+1

drivers/pinctrl/mediatek/pinctrl-mt6765.c

··· 1086 1086 { .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data }, 1087 1087 { } 1088 1088 }; 1089 + MODULE_DEVICE_TABLE(of, mt6765_pinctrl_of_match); 1089 1090 1090 1091 static struct platform_driver mt6765_pinctrl_driver = { 1091 1092 .driver = {

+1

drivers/pinctrl/mediatek/pinctrl-mt6779.c

··· 762 762 { .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data }, 763 763 { } 764 764 }; 765 + MODULE_DEVICE_TABLE(of, mt6779_pinctrl_of_match); 765 766 766 767 static struct platform_driver mt6779_pinctrl_driver = { 767 768 .driver = {

-3

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

··· 834 834 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 835 835 int *funcsize, const char *name) 836 836 { 837 - int i = 0; 838 - 839 837 if (*funcsize <= 0) 840 838 return -EOVERFLOW; 841 839 ··· 845 847 return -EEXIST; 846 848 } 847 849 funcs++; 848 - i++; 849 850 } 850 851 851 852 /* append new unique function */

+1 -1

drivers/pinctrl/pinconf-generic.c

··· 88 88 seq_puts(s, items[i].display); 89 89 /* Print unit if available */ 90 90 if (items[i].has_arg) { 91 - seq_printf(s, " (%u", 91 + seq_printf(s, " (0x%x", 92 92 pinconf_to_config_argument(config)); 93 93 if (items[i].format) 94 94 seq_printf(s, " %s)", items[i].format);

+46 -85

drivers/pinctrl/pinctrl-aw9523.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * Awinic AW9523B i2c pin controller driver 4 - * Copyright (c) 2020, AngeloGioacchino Del Regno 5 - * <angelogioacchino.delregno@somainline.org> 4 + * Copyright (c) 2020, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> 6 5 */ 7 6 8 7 #include <linux/bitfield.h> 8 + #include <linux/errno.h> 9 9 #include <linux/gpio/consumer.h> 10 10 #include <linux/gpio/driver.h> 11 11 #include <linux/i2c.h> 12 12 #include <linux/init.h> 13 13 #include <linux/interrupt.h> 14 14 #include <linux/irq.h> 15 - #include <linux/mutex.h> 16 15 #include <linux/module.h> 17 - #include <linux/pinctrl/pinconf.h> 18 - #include <linux/pinctrl/pinctrl.h> 19 - #include <linux/pinctrl/pinmux.h> 20 - #include <linux/pinctrl/pinconf-generic.h> 16 + #include <linux/mutex.h> 21 17 #include <linux/property.h> 22 18 #include <linux/regmap.h> 23 19 #include <linux/regulator/consumer.h> 24 20 #include <linux/slab.h> 21 + 22 + #include <linux/pinctrl/pinconf-generic.h> 23 + #include <linux/pinctrl/pinconf.h> 24 + #include <linux/pinctrl/pinctrl.h> 25 + #include <linux/pinctrl/pinmux.h> 25 26 26 27 #define AW9523_MAX_FUNCS 2 27 28 #define AW9523_NUM_PORTS 2 ··· 57 56 /* 58 57 * struct aw9523_irq - Interrupt controller structure 59 58 * @lock: mutex locking for the irq bus 60 - * @irqchip: structure holding irqchip params 61 59 * @cached_gpio: stores the previous gpio status for bit comparison 62 60 */ 63 61 struct aw9523_irq { 64 62 struct mutex lock; 65 - struct irq_chip *irqchip; 66 63 u16 cached_gpio; 67 - }; 68 - 69 - /* 70 - * struct aw9523_pinmux - Pin mux params 71 - * @name: Name of the mux 72 - * @grps: Groups of the mux 73 - * @num_grps: Number of groups (sizeof array grps) 74 - */ 75 - struct aw9523_pinmux { 76 - const char *name; 77 - const char * const *grps; 78 - const u8 num_grps; 79 64 }; 80 65 81 66 /* ··· 138 151 }; 139 152 140 153 static const char * const gpio_pwm_groups[] = { 141 - "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 142 - "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 143 - "gpio12", "gpio13", "gpio14", "gpio15" 154 + "gpio0", "gpio1", "gpio2", "gpio3", /* 0-3 */ 155 + "gpio4", "gpio5", "gpio6", "gpio7", /* 4-7 */ 156 + "gpio8", "gpio9", "gpio10", "gpio11", /* 8-11 */ 157 + "gpio12", "gpio13", "gpio14", "gpio15", /* 11-15 */ 144 158 }; 145 159 146 160 /* Warning: Do NOT reorder this array */ 147 - static const struct aw9523_pinmux aw9523_pmx[] = { 148 - { 149 - .name = "pwm", 150 - .grps = gpio_pwm_groups, 151 - .num_grps = ARRAY_SIZE(gpio_pwm_groups), 152 - }, 153 - { 154 - .name = "gpio", 155 - .grps = gpio_pwm_groups, 156 - .num_grps = ARRAY_SIZE(gpio_pwm_groups), 157 - }, 161 + static const struct pinfunction aw9523_pmx[] = { 162 + PINCTRL_PINFUNCTION("pwm", gpio_pwm_groups, ARRAY_SIZE(gpio_pwm_groups)), 163 + PINCTRL_PINFUNCTION("gpio", gpio_pwm_groups, ARRAY_SIZE(gpio_pwm_groups)), 158 164 }; 159 165 160 166 static int aw9523_pmx_get_funcs_count(struct pinctrl_dev *pctl) ··· 163 183 164 184 static int aw9523_pmx_get_groups(struct pinctrl_dev *pctl, unsigned int sel, 165 185 const char * const **groups, 166 - unsigned int * const num_groups) 186 + unsigned int * const ngroups) 167 187 { 168 - *groups = aw9523_pmx[sel].grps; 169 - *num_groups = aw9523_pmx[sel].num_grps; 188 + *groups = aw9523_pmx[sel].groups; 189 + *ngroups = aw9523_pmx[sel].ngroups; 170 190 return 0; 171 191 } 172 192 ··· 219 239 reg = AW9523_REG_OUT_STATE(pin); 220 240 break; 221 241 default: 222 - return -EOPNOTSUPP; 242 + return -ENOTSUPP; 223 243 } 224 244 *r = reg; 225 245 ··· 270 290 val = FIELD_GET(AW9523_GCR_GPOMD_MASK, val); 271 291 break; 272 292 default: 273 - return -EOPNOTSUPP; 293 + return -ENOTSUPP; 274 294 } 275 295 if (val < 1) 276 296 return -EINVAL; ··· 324 344 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 325 345 /* Open-Drain is supported only on port 0 */ 326 346 if (pin >= AW9523_PINS_PER_PORT) { 327 - rc = -EOPNOTSUPP; 347 + rc = -ENOTSUPP; 328 348 goto end; 329 349 } 330 350 mask = AW9523_GCR_GPOMD_MASK; ··· 341 361 val = AW9523_GCR_GPOMD_MASK; 342 362 break; 343 363 default: 344 - rc = -EOPNOTSUPP; 364 + rc = -ENOTSUPP; 345 365 goto end; 346 366 } 347 367 ··· 388 408 * 389 409 * Return: Zero for success or negative number for error 390 410 */ 391 - static int aw9523_get_port_state(struct regmap *regmap, u8 pin, 392 - u8 regbit, unsigned int *state) 411 + static int aw9523_get_port_state(struct regmap *regmap, u8 pin, u8 regbit, 412 + unsigned int *state) 393 413 { 394 414 u8 reg; 395 415 int dir; ··· 427 447 static void aw9523_irq_mask(struct irq_data *d) 428 448 { 429 449 struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 430 - unsigned int n = d->hwirq % AW9523_PINS_PER_PORT; 450 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 451 + unsigned int n = hwirq % AW9523_PINS_PER_PORT; 431 452 432 - regmap_update_bits(awi->regmap, 433 - AW9523_REG_INTR_DIS(d->hwirq), 453 + regmap_update_bits(awi->regmap, AW9523_REG_INTR_DIS(hwirq), 434 454 BIT(n), BIT(n)); 435 - gpiochip_disable_irq(&awi->gpio, irqd_to_hwirq(d)); 455 + gpiochip_disable_irq(&awi->gpio, hwirq); 436 456 } 437 457 438 458 /* ··· 445 465 static void aw9523_irq_unmask(struct irq_data *d) 446 466 { 447 467 struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 448 - unsigned int n = d->hwirq % AW9523_PINS_PER_PORT; 468 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 469 + unsigned int n = hwirq % AW9523_PINS_PER_PORT; 449 470 450 - gpiochip_enable_irq(&awi->gpio, irqd_to_hwirq(d)); 451 - regmap_update_bits(awi->regmap, 452 - AW9523_REG_INTR_DIS(d->hwirq), 471 + gpiochip_enable_irq(&awi->gpio, hwirq); 472 + regmap_update_bits(awi->regmap, AW9523_REG_INTR_DIS(hwirq), 453 473 BIT(n), 0); 454 474 } 455 475 ··· 602 622 mutex_lock(&awi->i2c_lock); 603 623 604 624 /* Port 0 (gpio 0-7) */ 605 - m = *mask & U8_MAX; 625 + m = *mask; 606 626 if (m) { 607 627 ret = _aw9523_gpio_get_multiple(awi, 0, &state, m); 608 628 if (ret) ··· 611 631 *bits = state; 612 632 613 633 /* Port 1 (gpio 8-15) */ 614 - m = (*mask >> 8) & U8_MAX; 634 + m = *mask >> 8; 615 635 if (m) { 616 636 ret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT, 617 637 &state, m); ··· 632 652 struct aw9523 *awi = gpiochip_get_data(chip); 633 653 u8 mask_lo, mask_hi, bits_lo, bits_hi; 634 654 unsigned int reg; 635 - int ret = 0; 655 + int ret; 636 656 637 - mask_lo = *mask & U8_MAX; 638 - mask_hi = (*mask >> 8) & U8_MAX; 657 + mask_lo = *mask; 658 + mask_hi = *mask >> 8; 659 + bits_lo = *bits; 660 + bits_hi = *bits >> 8; 661 + 639 662 mutex_lock(&awi->i2c_lock); 640 663 if (mask_hi) { 641 664 reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT); 642 - bits_hi = (*bits >> 8) & U8_MAX; 643 - 644 665 ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi); 645 - if (ret) { 666 + if (ret) 646 667 dev_warn(awi->dev, "Cannot write port1 out level\n"); 647 - goto out; 648 - } 649 668 } 650 669 if (mask_lo) { 651 670 reg = AW9523_REG_OUT_STATE(0); 652 - bits_lo = *bits & U8_MAX; 653 671 ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo); 654 672 if (ret) 655 673 dev_warn(awi->dev, "Cannot write port0 out level\n"); 656 674 } 657 - out: 658 675 mutex_unlock(&awi->i2c_lock); 659 676 } 660 677 ··· 804 827 { 805 828 struct device *dev = awi->dev; 806 829 struct gpio_irq_chip *girq; 807 - struct irq_chip *irqchip; 808 830 int ret; 809 831 810 832 if (!device_property_read_bool(dev, "interrupt-controller")) 811 833 return 0; 812 834 813 - irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); 814 - if (!irqchip) 815 - return -ENOMEM; 816 - 817 835 awi->irq = devm_kzalloc(dev, sizeof(*awi->irq), GFP_KERNEL); 818 836 if (!awi->irq) 819 837 return -ENOMEM; 820 838 821 - awi->irq->irqchip = irqchip; 822 839 mutex_init(&awi->irq->lock); 823 840 824 841 ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func, 825 842 IRQF_ONESHOT, dev_name(dev), awi); 826 - if (ret) { 827 - dev_err(dev, "Failed to request irq %d\n", irq); 828 - return ret; 829 - } 843 + if (ret) 844 + return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq); 830 845 831 846 girq = &awi->gpio.irq; 832 847 gpio_irq_chip_set_chip(girq, &aw9523_irq_chip); ··· 984 1015 } 985 1016 986 1017 mutex_init(&awi->i2c_lock); 987 - lockdep_set_subclass(&awi->i2c_lock, 988 - i2c_adapter_depth(client->adapter)); 1018 + lockdep_set_subclass(&awi->i2c_lock, i2c_adapter_depth(client->adapter)); 989 1019 990 1020 pdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL); 991 1021 if (!pdesc) ··· 1014 1046 1015 1047 awi->pctl = devm_pinctrl_register(dev, pdesc, awi); 1016 1048 if (IS_ERR(awi->pctl)) { 1017 - ret = PTR_ERR(awi->pctl); 1018 - dev_err(dev, "Cannot register pinctrl: %d", ret); 1049 + ret = dev_err_probe(dev, PTR_ERR(awi->pctl), "Cannot register pinctrl"); 1019 1050 goto err_disable_vregs; 1020 1051 } 1021 1052 ··· 1034 1067 static void aw9523_remove(struct i2c_client *client) 1035 1068 { 1036 1069 struct aw9523 *awi = i2c_get_clientdata(client); 1037 - int ret; 1038 - 1039 - if (!awi) 1040 - return; 1041 1070 1042 1071 /* 1043 1072 * If the chip VIO is connected to a regulator that we can turn ··· 1045 1082 regulator_disable(awi->vio_vreg); 1046 1083 } else { 1047 1084 mutex_lock(&awi->i2c_lock); 1048 - ret = aw9523_hw_init(awi); 1085 + aw9523_hw_init(awi); 1049 1086 mutex_unlock(&awi->i2c_lock); 1050 - if (ret) 1051 - return; 1052 1087 } 1053 1088 1054 1089 mutex_destroy(&awi->i2c_lock);

+1

drivers/pinctrl/pinctrl-loongson2.c

··· 286 286 }, 287 287 { } 288 288 }; 289 + MODULE_DEVICE_TABLE(of, loongson2_pinctrl_dt_match); 289 290 290 291 static struct platform_driver loongson2_pinctrl_driver = { 291 292 .probe = loongson2_pinctrl_probe,

-2

drivers/pinctrl/pinctrl-max77620.c

··· 88 88 89 89 struct max77620_pin_info { 90 90 enum max77620_pin_ppdrv drv_type; 91 - int pull_config; 92 91 }; 93 92 94 93 struct max77620_fps_config { ··· 103 104 struct device *dev; 104 105 struct pinctrl_dev *pctl; 105 106 struct regmap *rmap; 106 - int pins_current_opt[MAX77620_GPIO_NR]; 107 107 const struct max77620_pin_function *functions; 108 108 unsigned int num_functions; 109 109 const struct max77620_pingroup *pin_groups;

+21 -29

drivers/pinctrl/pinctrl-single.c

··· 81 81 * @name: pinctrl function name 82 82 * @vals: register and vals array 83 83 * @nvals: number of entries in vals array 84 - * @pgnames: array of pingroup names the function uses 85 - * @npgnames: number of pingroup names the function uses 86 84 * @conf: array of pin configurations 87 85 * @nconfs: number of pin configurations available 88 86 * @node: list node ··· 89 91 const char *name; 90 92 struct pcs_func_vals *vals; 91 93 unsigned nvals; 92 - const char **pgnames; 93 - int npgnames; 94 94 struct pcs_conf_vals *conf; 95 95 int nconfs; 96 96 struct list_head node; ··· 550 554 unsigned offset = 0, shift = 0, i, data, ret; 551 555 u32 arg; 552 556 int j; 557 + enum pin_config_param param; 553 558 554 559 ret = pcs_get_function(pctldev, pin, &func); 555 560 if (ret) 556 561 return ret; 557 562 558 563 for (j = 0; j < num_configs; j++) { 564 + param = pinconf_to_config_param(configs[j]); 565 + 566 + /* BIAS_DISABLE has no entry in the func->conf table */ 567 + if (param == PIN_CONFIG_BIAS_DISABLE) { 568 + /* This just disables all bias entries */ 569 + pcs_pinconf_clear_bias(pctldev, pin); 570 + continue; 571 + } 572 + 559 573 for (i = 0; i < func->nconfs; i++) { 560 - if (pinconf_to_config_param(configs[j]) 561 - != func->conf[i].param) 574 + if (param != func->conf[i].param) 562 575 continue; 563 576 564 577 offset = pin * (pcs->width / BITS_PER_BYTE); 565 578 data = pcs->read(pcs->base + offset); 566 579 arg = pinconf_to_config_argument(configs[j]); 567 - switch (func->conf[i].param) { 580 + switch (param) { 568 581 /* 2 parameters */ 569 582 case PIN_CONFIG_INPUT_SCHMITT: 570 583 case PIN_CONFIG_DRIVE_STRENGTH: ··· 585 580 data |= (arg << shift) & func->conf[i].mask; 586 581 break; 587 582 /* 4 parameters */ 588 - case PIN_CONFIG_BIAS_DISABLE: 589 - pcs_pinconf_clear_bias(pctldev, pin); 590 - break; 591 583 case PIN_CONFIG_BIAS_PULL_DOWN: 592 584 case PIN_CONFIG_BIAS_PULL_UP: 593 585 if (arg) ··· 1627 1625 return 0; 1628 1626 } 1629 1627 1630 - #ifdef CONFIG_PM 1631 1628 static int pcs_save_context(struct pcs_device *pcs) 1632 1629 { 1633 1630 int i, mux_bytes; ··· 1691 1690 } 1692 1691 } 1693 1692 1694 - static int pinctrl_single_suspend(struct platform_device *pdev, 1695 - pm_message_t state) 1693 + static int pinctrl_single_suspend_noirq(struct device *dev) 1696 1694 { 1697 - struct pcs_device *pcs; 1698 - 1699 - pcs = platform_get_drvdata(pdev); 1700 - if (!pcs) 1701 - return -EINVAL; 1695 + struct pcs_device *pcs = dev_get_drvdata(dev); 1702 1696 1703 1697 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { 1704 1698 int ret; ··· 1706 1710 return pinctrl_force_sleep(pcs->pctl); 1707 1711 } 1708 1712 1709 - static int pinctrl_single_resume(struct platform_device *pdev) 1713 + static int pinctrl_single_resume_noirq(struct device *dev) 1710 1714 { 1711 - struct pcs_device *pcs; 1712 - 1713 - pcs = platform_get_drvdata(pdev); 1714 - if (!pcs) 1715 - return -EINVAL; 1715 + struct pcs_device *pcs = dev_get_drvdata(dev); 1716 1716 1717 1717 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) 1718 1718 pcs_restore_context(pcs); 1719 1719 1720 1720 return pinctrl_force_default(pcs->pctl); 1721 1721 } 1722 - #endif 1722 + 1723 + static DEFINE_NOIRQ_DEV_PM_OPS(pinctrl_single_pm_ops, 1724 + pinctrl_single_suspend_noirq, 1725 + pinctrl_single_resume_noirq); 1723 1726 1724 1727 /** 1725 1728 * pcs_quirk_missing_pinctrl_cells - handle legacy binding ··· 1981 1986 .driver = { 1982 1987 .name = DRIVER_NAME, 1983 1988 .of_match_table = pcs_of_match, 1989 + .pm = pm_sleep_ptr(&pinctrl_single_pm_ops), 1984 1990 }, 1985 - #ifdef CONFIG_PM 1986 - .suspend = pinctrl_single_suspend, 1987 - .resume = pinctrl_single_resume, 1988 - #endif 1989 1991 }; 1990 1992 1991 1993 module_platform_driver(pcs_driver);

+9 -17

drivers/pinctrl/pinmux.c

··· 578 578 579 579 return 0; 580 580 } 581 + DEFINE_SHOW_ATTRIBUTE(pinmux_functions); 581 582 582 583 static int pinmux_pins_show(struct seq_file *s, void *what) 583 584 { ··· 651 650 652 651 return 0; 653 652 } 653 + DEFINE_SHOW_ATTRIBUTE(pinmux_pins); 654 654 655 655 void pinmux_show_map(struct seq_file *s, const struct pinctrl_map *map) 656 656 { ··· 674 672 setting->data.mux.func); 675 673 } 676 674 677 - DEFINE_SHOW_ATTRIBUTE(pinmux_functions); 678 - DEFINE_SHOW_ATTRIBUTE(pinmux_pins); 675 + static int pinmux_select_show(struct seq_file *s, void *unused) 676 + { 677 + return -EPERM; 678 + } 679 679 680 - static ssize_t pinmux_select(struct file *file, const char __user *user_buf, 680 + static ssize_t pinmux_select_write(struct file *file, const char __user *user_buf, 681 681 size_t len, loff_t *ppos) 682 682 { 683 683 struct seq_file *sfile = file->private_data; ··· 753 749 754 750 return ret; 755 751 } 756 - 757 - static int pinmux_select_open(struct inode *inode, struct file *file) 758 - { 759 - return single_open(file, NULL, inode->i_private); 760 - } 761 - 762 - static const struct file_operations pinmux_select_ops = { 763 - .owner = THIS_MODULE, 764 - .open = pinmux_select_open, 765 - .write = pinmux_select, 766 - .llseek = no_llseek, 767 - .release = single_release, 768 - }; 752 + DEFINE_SHOW_STORE_ATTRIBUTE(pinmux_select); 769 753 770 754 void pinmux_init_device_debugfs(struct dentry *devroot, 771 755 struct pinctrl_dev *pctldev) ··· 763 771 debugfs_create_file("pinmux-pins", 0444, 764 772 devroot, pctldev, &pinmux_pins_fops); 765 773 debugfs_create_file("pinmux-select", 0200, 766 - devroot, pctldev, &pinmux_select_ops); 774 + devroot, pctldev, &pinmux_select_fops); 767 775 } 768 776 769 777 #endif /* CONFIG_DEBUG_FS */

+25 -30

drivers/pinctrl/pxa/pinctrl-pxa2xx.c

··· 32 32 unsigned tgroup) 33 33 { 34 34 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 35 - struct pxa_pinctrl_group *group = pctl->groups + tgroup; 35 + struct pingroup *group = pctl->groups + tgroup; 36 36 37 37 return group->name; 38 38 } ··· 43 43 unsigned *num_pins) 44 44 { 45 45 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 46 - struct pxa_pinctrl_group *group = pctl->groups + tgroup; 46 + struct pingroup *group = pctl->groups + tgroup; 47 47 48 - *pins = (unsigned *)&group->pin; 49 - *num_pins = 1; 48 + *pins = group->pins; 49 + *num_pins = group->npins; 50 50 51 51 return 0; 52 52 } ··· 109 109 unsigned function) 110 110 { 111 111 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 112 - struct pxa_pinctrl_function *pf = pctl->functions + function; 112 + struct pinfunction *pf = pctl->functions + function; 113 113 114 114 return pf->name; 115 115 } ··· 127 127 unsigned * const num_groups) 128 128 { 129 129 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 130 - struct pxa_pinctrl_function *pf = pctl->functions + function; 130 + struct pinfunction *pf = pctl->functions + function; 131 131 132 132 *groups = pf->groups; 133 133 *num_groups = pf->ngroups; ··· 139 139 unsigned tgroup) 140 140 { 141 141 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 142 - struct pxa_pinctrl_group *group = pctl->groups + tgroup; 142 + struct pingroup *g = pctl->groups + tgroup; 143 + unsigned int pin = g->pins[0]; 143 144 struct pxa_desc_function *df; 144 - int pin, shift; 145 145 unsigned long flags; 146 146 void __iomem *gafr, *gpdr; 147 + int shift; 147 148 u32 val; 148 149 149 - 150 - df = pxa_desc_by_func_group(pctl, group->name, 151 - (pctl->functions + function)->name); 150 + df = pxa_desc_by_func_group(pctl, g->name, (pctl->functions + function)->name); 152 151 if (!df) 153 152 return -EINVAL; 154 153 155 - pin = group->pin; 156 154 gafr = pctl->base_gafr[pin / 16]; 157 155 gpdr = pctl->base_gpdr[pin / 32]; 158 156 shift = (pin % 16) << 1; ··· 184 186 unsigned long *config) 185 187 { 186 188 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 187 - struct pxa_pinctrl_group *g = pctl->groups + group; 189 + struct pingroup *g = pctl->groups + group; 190 + unsigned int pin = g->pins[0]; 188 191 unsigned long flags; 189 - unsigned pin = g->pin; 190 192 void __iomem *pgsr = pctl->base_pgsr[pin / 32]; 191 193 u32 val; 192 194 ··· 206 208 unsigned num_configs) 207 209 { 208 210 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 209 - struct pxa_pinctrl_group *g = pctl->groups + group; 211 + struct pingroup *g = pctl->groups + group; 212 + unsigned int pin = g->pins[0]; 210 213 unsigned long flags; 211 - unsigned pin = g->pin; 212 214 void __iomem *pgsr = pctl->base_pgsr[pin / 32]; 213 215 int i, is_set = 0; 214 216 u32 val; ··· 247 249 .pmxops = &pxa2xx_pinmux_ops, 248 250 }; 249 251 250 - static const struct pxa_pinctrl_function * 251 - pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname, 252 - const struct pxa_pinctrl_function *functions) 252 + static const struct pinfunction *pxa2xx_find_function(struct pxa_pinctrl *pctl, 253 + const char *fname, 254 + const struct pinfunction *functions) 253 255 { 254 - const struct pxa_pinctrl_function *func; 256 + const struct pinfunction *func; 255 257 256 258 for (func = functions; func->name; func++) 257 259 if (!strcmp(fname, func->name)) ··· 262 264 263 265 static int pxa2xx_build_functions(struct pxa_pinctrl *pctl) 264 266 { 267 + struct pinfunction *functions; 265 268 int i; 266 - struct pxa_pinctrl_function *functions; 267 269 struct pxa_desc_function *df; 268 270 269 271 /* ··· 294 296 static int pxa2xx_build_groups(struct pxa_pinctrl *pctl) 295 297 { 296 298 int i, j, ngroups; 297 - struct pxa_pinctrl_function *func; 298 299 struct pxa_desc_function *df; 299 - char **gtmp; 300 + struct pinfunction *func; 301 + const char **gtmp; 300 302 301 303 gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp), 302 304 GFP_KERNEL); ··· 314 316 pctl->ppins[j].pin.name; 315 317 func = pctl->functions + i; 316 318 func->ngroups = ngroups; 317 - func->groups = 318 - devm_kmalloc_array(pctl->dev, ngroups, 319 - sizeof(char *), GFP_KERNEL); 319 + func->groups = devm_kmemdup(pctl->dev, gtmp, ngroups * sizeof(*gtmp), GFP_KERNEL); 320 320 if (!func->groups) 321 321 return -ENOMEM; 322 - 323 - memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp)); 324 322 } 325 323 326 324 devm_kfree(pctl->dev, gtmp); ··· 326 332 static int pxa2xx_build_state(struct pxa_pinctrl *pctl, 327 333 const struct pxa_desc_pin *ppins, int npins) 328 334 { 329 - struct pxa_pinctrl_group *group; 330 335 struct pinctrl_pin_desc *pins; 336 + struct pingroup *group; 331 337 int ret, i; 332 338 333 339 pctl->npins = npins; ··· 351 357 for (i = 0; i < npins; i++) { 352 358 group = pctl->groups + i; 353 359 group->name = ppins[i].pin.name; 354 - group->pin = ppins[i].pin.number; 360 + group->pins = &ppins[i].pin.number; 361 + group->npins = 1; 355 362 } 356 363 357 364 ret = pxa2xx_build_functions(pctl);

+2 -13

drivers/pinctrl/pxa/pinctrl-pxa2xx.h

··· 52 52 struct pxa_desc_function *functions; 53 53 }; 54 54 55 - struct pxa_pinctrl_group { 56 - const char *name; 57 - unsigned pin; 58 - }; 59 - 60 - struct pxa_pinctrl_function { 61 - const char *name; 62 - const char **groups; 63 - unsigned ngroups; 64 - }; 65 - 66 55 struct pxa_pinctrl { 67 56 spinlock_t lock; 68 57 void __iomem **base_gafr; ··· 63 74 unsigned npins; 64 75 const struct pxa_desc_pin *ppins; 65 76 unsigned ngroups; 66 - struct pxa_pinctrl_group *groups; 77 + struct pingroup *groups; 67 78 unsigned nfuncs; 68 - struct pxa_pinctrl_function *functions; 79 + struct pinfunction *functions; 69 80 char *name; 70 81 }; 71 82

+11 -10

drivers/pinctrl/qcom/pinctrl-sm7150.c

··· 65 65 .intr_detection_width = 2, \ 66 66 } 67 67 68 - #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 68 + #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ 69 69 { \ 70 70 .grp = PINCTRL_PINGROUP(#pg_name, \ 71 71 pg_name##_pins, \ ··· 75 75 .intr_cfg_reg = 0, \ 76 76 .intr_status_reg = 0, \ 77 77 .intr_target_reg = 0, \ 78 - .tile = SOUTH, \ 78 + .tile = _tile, \ 79 79 .mux_bit = -1, \ 80 80 .pull_bit = pull, \ 81 81 .drv_bit = drv, \ ··· 101 101 .intr_cfg_reg = 0, \ 102 102 .intr_status_reg = 0, \ 103 103 .intr_target_reg = 0, \ 104 - .tile = SOUTH, \ 104 + .tile = WEST, \ 105 105 .mux_bit = -1, \ 106 106 .pull_bit = 3, \ 107 107 .drv_bit = 0, \ ··· 1199 1199 [117] = PINGROUP(117, NORTH, _, _, _, _, _, _, _, _, _), 1200 1200 [118] = PINGROUP(118, NORTH, _, _, _, _, _, _, _, _, _), 1201 1201 [119] = UFS_RESET(ufs_reset, 0x9f000), 1202 - [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), 1203 - [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), 1204 - [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), 1205 - [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), 1206 - [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x98000, 14, 6), 1207 - [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x98000, 11, 3), 1208 - [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x98000, 9, 0), 1202 + [120] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x9a000, 15, 0), 1203 + [121] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x9a000, 13, 6), 1204 + [122] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x9a000, 11, 3), 1205 + [123] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x9a000, 9, 0), 1206 + [124] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x98000, 14, 6), 1207 + [125] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x98000, 11, 3), 1208 + [126] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x98000, 9, 0), 1209 1209 }; 1210 1210 1211 1211 static const struct msm_gpio_wakeirq_map sm7150_pdc_map[] = { ··· 1246 1246 { .compatible = "qcom,sm7150-tlmm", }, 1247 1247 { }, 1248 1248 }; 1249 + MODULE_DEVICE_TABLE(of, sm7150_tlmm_of_match); 1249 1250 1250 1251 static struct platform_driver sm7150_tlmm_driver = { 1251 1252 .driver = {

+4

drivers/pinctrl/qcom/pinctrl-spmi-gpio.c

··· 1202 1202 { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, 1203 1203 { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, 1204 1204 { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 }, 1205 + { .compatible = "qcom,pm6450-gpio", .data = (void *) 9 }, 1205 1206 { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 }, 1206 1207 { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, 1207 1208 { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, ··· 1235 1234 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, 1236 1235 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, 1237 1236 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, 1237 + { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 }, 1238 1238 { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 }, 1239 1239 { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, 1240 1240 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, 1241 1241 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, 1242 + { .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 }, 1242 1243 { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, 1243 1244 { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, 1244 1245 { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, ··· 1256 1253 { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, 1257 1254 { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 }, 1258 1255 { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 }, 1256 + { .compatible = "qcom,pmxr2230-gpio", .data = (void *) 12 }, 1259 1257 { }, 1260 1258 }; 1261 1259

+1

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

··· 1414 1414 { .compatible = "realtek,rtd1315e-pinctrl", }, 1415 1415 {}, 1416 1416 }; 1417 + MODULE_DEVICE_TABLE(of, rtd1315e_pinctrl_of_match); 1417 1418 1418 1419 static struct platform_driver rtd1315e_pinctrl_driver = { 1419 1420 .driver = {

+1

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

··· 1584 1584 { .compatible = "realtek,rtd1319d-pinctrl", }, 1585 1585 {}, 1586 1586 }; 1587 + MODULE_DEVICE_TABLE(of, rtd1319d_pinctrl_of_match); 1587 1588 1588 1589 static struct platform_driver rtd1319d_pinctrl_driver = { 1589 1590 .driver = {

+124 -12

drivers/pinctrl/renesas/pfc-r8a779h0.c

··· 75 75 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) 76 76 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) 77 77 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) 78 - #define GPSR0_6 F_(IRQ0, IP0SR0_27_24) 79 - #define GPSR0_5 F_(IRQ1, IP0SR0_23_20) 80 - #define GPSR0_4 F_(IRQ2, IP0SR0_19_16) 81 - #define GPSR0_3 F_(IRQ3, IP0SR0_15_12) 78 + #define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24) 79 + #define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20) 80 + #define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16) 81 + #define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12) 82 82 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8) 83 83 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4) 84 84 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0) ··· 265 265 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 266 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 267 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 - #define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 - #define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 - #define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 - #define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 + #define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 + #define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 + #define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 + #define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 272 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 273 274 274 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ ··· 672 672 673 673 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), 674 674 675 - PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3), 675 + PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A), 676 676 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), 677 677 678 - PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2), 678 + PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A), 679 679 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), 680 680 681 - PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1), 681 + PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A), 682 682 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), 683 683 684 - PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0), 684 + PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A), 685 685 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), 686 686 687 687 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), ··· 1660 1660 SDA3_MARK, SCL3_MARK, 1661 1661 }; 1662 1662 1663 + /* - INTC-EX ---------------------------------------------------------------- */ 1664 + static const unsigned int intc_ex_irq0_a_pins[] = { 1665 + /* IRQ0_A */ 1666 + RCAR_GP_PIN(0, 6), 1667 + }; 1668 + static const unsigned int intc_ex_irq0_a_mux[] = { 1669 + IRQ0_A_MARK, 1670 + }; 1671 + static const unsigned int intc_ex_irq0_b_pins[] = { 1672 + /* IRQ0_B */ 1673 + RCAR_GP_PIN(1, 20), 1674 + }; 1675 + static const unsigned int intc_ex_irq0_b_mux[] = { 1676 + IRQ0_B_MARK, 1677 + }; 1678 + 1679 + static const unsigned int intc_ex_irq1_a_pins[] = { 1680 + /* IRQ1_A */ 1681 + RCAR_GP_PIN(0, 5), 1682 + }; 1683 + static const unsigned int intc_ex_irq1_a_mux[] = { 1684 + IRQ1_A_MARK, 1685 + }; 1686 + static const unsigned int intc_ex_irq1_b_pins[] = { 1687 + /* IRQ1_B */ 1688 + RCAR_GP_PIN(1, 21), 1689 + }; 1690 + static const unsigned int intc_ex_irq1_b_mux[] = { 1691 + IRQ1_B_MARK, 1692 + }; 1693 + 1694 + static const unsigned int intc_ex_irq2_a_pins[] = { 1695 + /* IRQ2_A */ 1696 + RCAR_GP_PIN(0, 4), 1697 + }; 1698 + static const unsigned int intc_ex_irq2_a_mux[] = { 1699 + IRQ2_A_MARK, 1700 + }; 1701 + static const unsigned int intc_ex_irq2_b_pins[] = { 1702 + /* IRQ2_B */ 1703 + RCAR_GP_PIN(0, 13), 1704 + }; 1705 + static const unsigned int intc_ex_irq2_b_mux[] = { 1706 + IRQ2_B_MARK, 1707 + }; 1708 + 1709 + static const unsigned int intc_ex_irq3_a_pins[] = { 1710 + /* IRQ3_A */ 1711 + RCAR_GP_PIN(0, 3), 1712 + }; 1713 + static const unsigned int intc_ex_irq3_a_mux[] = { 1714 + IRQ3_A_MARK, 1715 + }; 1716 + static const unsigned int intc_ex_irq3_b_pins[] = { 1717 + /* IRQ3_B */ 1718 + RCAR_GP_PIN(1, 23), 1719 + }; 1720 + static const unsigned int intc_ex_irq3_b_mux[] = { 1721 + IRQ3_B_MARK, 1722 + }; 1723 + 1724 + static const unsigned int intc_ex_irq4_a_pins[] = { 1725 + /* IRQ4_A */ 1726 + RCAR_GP_PIN(1, 17), 1727 + }; 1728 + static const unsigned int intc_ex_irq4_a_mux[] = { 1729 + IRQ4_A_MARK, 1730 + }; 1731 + static const unsigned int intc_ex_irq4_b_pins[] = { 1732 + /* IRQ4_B */ 1733 + RCAR_GP_PIN(2, 3), 1734 + }; 1735 + static const unsigned int intc_ex_irq4_b_mux[] = { 1736 + IRQ4_B_MARK, 1737 + }; 1738 + 1739 + static const unsigned int intc_ex_irq5_pins[] = { 1740 + /* IRQ5 */ 1741 + RCAR_GP_PIN(2, 2), 1742 + }; 1743 + static const unsigned int intc_ex_irq5_mux[] = { 1744 + IRQ5_MARK, 1745 + }; 1746 + 1663 1747 /* - MMC -------------------------------------------------------------------- */ 1664 1748 static const unsigned int mmc_data_pins[] = { 1665 1749 /* MMC_SD_D[0:3], MMC_D[4:7] */ ··· 2500 2416 SH_PFC_PIN_GROUP(i2c2), 2501 2417 SH_PFC_PIN_GROUP(i2c3), 2502 2418 2419 + SH_PFC_PIN_GROUP(intc_ex_irq0_a), 2420 + SH_PFC_PIN_GROUP(intc_ex_irq0_b), 2421 + SH_PFC_PIN_GROUP(intc_ex_irq1_a), 2422 + SH_PFC_PIN_GROUP(intc_ex_irq1_b), 2423 + SH_PFC_PIN_GROUP(intc_ex_irq2_a), 2424 + SH_PFC_PIN_GROUP(intc_ex_irq2_b), 2425 + SH_PFC_PIN_GROUP(intc_ex_irq3_a), 2426 + SH_PFC_PIN_GROUP(intc_ex_irq3_b), 2427 + SH_PFC_PIN_GROUP(intc_ex_irq4_a), 2428 + SH_PFC_PIN_GROUP(intc_ex_irq4_b), 2429 + SH_PFC_PIN_GROUP(intc_ex_irq5), 2430 + 2503 2431 BUS_DATA_PIN_GROUP(mmc_data, 1), 2504 2432 BUS_DATA_PIN_GROUP(mmc_data, 4), 2505 2433 BUS_DATA_PIN_GROUP(mmc_data, 8), ··· 2725 2629 "i2c3", 2726 2630 }; 2727 2631 2632 + static const char * const intc_ex_groups[] = { 2633 + "intc_ex_irq0_a", 2634 + "intc_ex_irq0_b", 2635 + "intc_ex_irq1_a", 2636 + "intc_ex_irq1_b", 2637 + "intc_ex_irq2_a", 2638 + "intc_ex_irq2_b", 2639 + "intc_ex_irq3_a", 2640 + "intc_ex_irq3_b", 2641 + "intc_ex_irq4_a", 2642 + "intc_ex_irq4_b", 2643 + "intc_ex_irq5", 2644 + }; 2645 + 2728 2646 static const char * const mmc_groups[] = { 2729 2647 "mmc_data1", 2730 2648 "mmc_data4", ··· 2922 2812 SH_PFC_FUNCTION(i2c1), 2923 2813 SH_PFC_FUNCTION(i2c2), 2924 2814 SH_PFC_FUNCTION(i2c3), 2815 + 2816 + SH_PFC_FUNCTION(intc_ex), 2925 2817 2926 2818 SH_PFC_FUNCTION(mmc), 2927 2819

+3 -1

drivers/pinctrl/renesas/pinctrl-rzg2l.c

··· 892 892 val = PVDD_1800; 893 893 break; 894 894 case 2500: 895 + if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 896 + return -EINVAL; 895 897 val = PVDD_2500; 896 898 break; 897 899 case 3300: ··· 2516 2514 } 2517 2515 } 2518 2516 2519 - static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 2517 + static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 2520 2518 { 2521 2519 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2522 2520 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;

+112

drivers/pinctrl/samsung/pinctrl-exynos.c

··· 13 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 14 // external gpio and wakeup interrupt support. 15 15 16 + #include <linux/clk.h> 16 17 #include <linux/device.h> 17 18 #include <linux/interrupt.h> 18 19 #include <linux/irqdomain.h> ··· 62 61 else 63 62 reg_mask = our_chip->eint_mask + bank->eint_offset; 64 63 64 + if (clk_enable(bank->drvdata->pclk)) { 65 + dev_err(bank->gpio_chip.parent, 66 + "unable to enable clock for masking IRQ\n"); 67 + return; 68 + } 69 + 65 70 raw_spin_lock_irqsave(&bank->slock, flags); 66 71 67 72 mask = readl(bank->eint_base + reg_mask); ··· 75 68 writel(mask, bank->eint_base + reg_mask); 76 69 77 70 raw_spin_unlock_irqrestore(&bank->slock, flags); 71 + 72 + clk_disable(bank->drvdata->pclk); 78 73 } 79 74 80 75 static void exynos_irq_ack(struct irq_data *irqd) ··· 91 82 else 92 83 reg_pend = our_chip->eint_pend + bank->eint_offset; 93 84 85 + if (clk_enable(bank->drvdata->pclk)) { 86 + dev_err(bank->gpio_chip.parent, 87 + "unable to enable clock to ack IRQ\n"); 88 + return; 89 + } 90 + 94 91 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 92 + 93 + clk_disable(bank->drvdata->pclk); 95 94 } 96 95 97 96 static void exynos_irq_unmask(struct irq_data *irqd) ··· 127 110 else 128 111 reg_mask = our_chip->eint_mask + bank->eint_offset; 129 112 113 + if (clk_enable(bank->drvdata->pclk)) { 114 + dev_err(bank->gpio_chip.parent, 115 + "unable to enable clock for unmasking IRQ\n"); 116 + return; 117 + } 118 + 130 119 raw_spin_lock_irqsave(&bank->slock, flags); 131 120 132 121 mask = readl(bank->eint_base + reg_mask); ··· 140 117 writel(mask, bank->eint_base + reg_mask); 141 118 142 119 raw_spin_unlock_irqrestore(&bank->slock, flags); 120 + 121 + clk_disable(bank->drvdata->pclk); 143 122 } 144 123 145 124 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) ··· 152 127 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 153 128 unsigned int con, trig_type; 154 129 unsigned long reg_con; 130 + int ret; 155 131 156 132 switch (type) { 157 133 case IRQ_TYPE_EDGE_RISING: ··· 185 159 else 186 160 reg_con = our_chip->eint_con + bank->eint_offset; 187 161 162 + ret = clk_enable(bank->drvdata->pclk); 163 + if (ret) { 164 + dev_err(bank->gpio_chip.parent, 165 + "unable to enable clock for configuring IRQ type\n"); 166 + return ret; 167 + } 168 + 188 169 con = readl(bank->eint_base + reg_con); 189 170 con &= ~(EXYNOS_EINT_CON_MASK << shift); 190 171 con |= trig_type << shift; 191 172 writel(con, bank->eint_base + reg_con); 173 + 174 + clk_disable(bank->drvdata->pclk); 192 175 193 176 return 0; 194 177 } ··· 235 200 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 236 201 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 237 202 203 + ret = clk_enable(bank->drvdata->pclk); 204 + if (ret) { 205 + dev_err(bank->gpio_chip.parent, 206 + "unable to enable clock for configuring pin %s-%lu\n", 207 + bank->name, irqd->hwirq); 208 + return ret; 209 + } 210 + 238 211 raw_spin_lock_irqsave(&bank->slock, flags); 239 212 240 213 con = readl(bank->pctl_base + reg_con); ··· 251 208 writel(con, bank->pctl_base + reg_con); 252 209 253 210 raw_spin_unlock_irqrestore(&bank->slock, flags); 211 + 212 + clk_disable(bank->drvdata->pclk); 254 213 255 214 return 0; 256 215 } ··· 268 223 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 269 224 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 270 225 226 + if (clk_enable(bank->drvdata->pclk)) { 227 + dev_err(bank->gpio_chip.parent, 228 + "unable to enable clock for deconfiguring pin %s-%lu\n", 229 + bank->name, irqd->hwirq); 230 + return; 231 + } 232 + 271 233 raw_spin_lock_irqsave(&bank->slock, flags); 272 234 273 235 con = readl(bank->pctl_base + reg_con); ··· 283 231 writel(con, bank->pctl_base + reg_con); 284 232 285 233 raw_spin_unlock_irqrestore(&bank->slock, flags); 234 + 235 + clk_disable(bank->drvdata->pclk); 286 236 287 237 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 288 238 } ··· 335 281 unsigned int svc, group, pin; 336 282 int ret; 337 283 284 + if (clk_enable(bank->drvdata->pclk)) { 285 + dev_err(bank->gpio_chip.parent, 286 + "unable to enable clock for handling IRQ\n"); 287 + return IRQ_NONE; 288 + } 289 + 338 290 if (bank->eint_con_offset) 339 291 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); 340 292 else 341 293 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 294 + 295 + clk_disable(bank->drvdata->pclk); 296 + 342 297 group = EXYNOS_SVC_GROUP(svc); 343 298 pin = svc & EXYNOS_SVC_NUM_MASK; 344 299 ··· 626 563 627 564 chained_irq_enter(chip, desc); 628 565 566 + /* 567 + * just enable the clock once here, to avoid an enable/disable dance for 568 + * each bank. 569 + */ 570 + if (eintd->nr_banks) { 571 + struct samsung_pin_bank *b = eintd->banks[0]; 572 + 573 + if (clk_enable(b->drvdata->pclk)) { 574 + dev_err(b->gpio_chip.parent, 575 + "unable to enable clock for pending IRQs\n"); 576 + return; 577 + } 578 + } 579 + 629 580 for (i = 0; i < eintd->nr_banks; ++i) { 630 581 struct samsung_pin_bank *b = eintd->banks[i]; 631 582 pend = readl(b->eint_base + b->irq_chip->eint_pend ··· 648 571 + b->eint_offset); 649 572 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 650 573 } 574 + 575 + if (eintd->nr_banks) 576 + clk_disable(eintd->banks[0]->drvdata->pclk); 651 577 652 578 chained_irq_exit(chip, desc); 653 579 } ··· 775 695 struct exynos_eint_gpio_save *save = bank->soc_priv; 776 696 const void __iomem *regs = bank->eint_base; 777 697 698 + if (clk_enable(bank->drvdata->pclk)) { 699 + dev_err(bank->gpio_chip.parent, 700 + "unable to enable clock for saving state\n"); 701 + return; 702 + } 703 + 778 704 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 779 705 + bank->eint_offset); 780 706 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET ··· 789 703 + 2 * bank->eint_offset + 4); 790 704 save->eint_mask = readl(regs + bank->irq_chip->eint_mask 791 705 + bank->eint_offset); 706 + 707 + clk_disable(bank->drvdata->pclk); 792 708 793 709 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 794 710 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); ··· 804 716 struct exynos_eint_gpio_save *save = bank->soc_priv; 805 717 const void __iomem *regs = bank->eint_base; 806 718 719 + if (clk_enable(bank->drvdata->pclk)) { 720 + dev_err(bank->gpio_chip.parent, 721 + "unable to enable clock for saving state\n"); 722 + return; 723 + } 724 + 807 725 save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); 808 726 save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); 727 + 728 + clk_disable(bank->drvdata->pclk); 809 729 810 730 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 811 731 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); ··· 849 753 struct exynos_eint_gpio_save *save = bank->soc_priv; 850 754 void __iomem *regs = bank->eint_base; 851 755 756 + if (clk_enable(bank->drvdata->pclk)) { 757 + dev_err(bank->gpio_chip.parent, 758 + "unable to enable clock for restoring state\n"); 759 + return; 760 + } 761 + 852 762 pr_debug("%s: con %#010x => %#010x\n", bank->name, 853 763 readl(regs + EXYNOS_GPIO_ECON_OFFSET 854 764 + bank->eint_offset), save->eint_con); ··· 876 774 + 2 * bank->eint_offset + 4); 877 775 writel(save->eint_mask, regs + bank->irq_chip->eint_mask 878 776 + bank->eint_offset); 777 + 778 + clk_disable(bank->drvdata->pclk); 879 779 } 880 780 881 781 static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata, ··· 886 782 struct exynos_eint_gpio_save *save = bank->soc_priv; 887 783 void __iomem *regs = bank->eint_base; 888 784 785 + if (clk_enable(bank->drvdata->pclk)) { 786 + dev_err(bank->gpio_chip.parent, 787 + "unable to enable clock for restoring state\n"); 788 + return; 789 + } 790 + 889 791 pr_debug("%s: con %#010x => %#010x\n", bank->name, 890 792 readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); 891 793 pr_debug("%s: mask %#010x => %#010x\n", bank->name, ··· 899 789 900 790 writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); 901 791 writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); 792 + 793 + clk_disable(bank->drvdata->pclk); 902 794 } 903 795 904 796 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)

+91 -4

drivers/pinctrl/samsung/pinctrl-samsung.c

··· 15 15 // but provides extensions to which platform specific implementation of the gpio 16 16 // and wakeup interrupts can be hooked to. 17 17 18 + #include <linux/clk.h> 18 19 #include <linux/err.h> 19 20 #include <linux/gpio/driver.h> 20 21 #include <linux/init.h> ··· 372 371 } 373 372 374 373 /* enable or disable a pinmux function */ 375 - static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, 376 - unsigned group) 374 + static int samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, 375 + unsigned group) 377 376 { 378 377 struct samsung_pinctrl_drv_data *drvdata; 379 378 const struct samsung_pin_bank_type *type; ··· 383 382 unsigned long flags; 384 383 const struct samsung_pmx_func *func; 385 384 const struct samsung_pin_group *grp; 385 + int ret; 386 386 387 387 drvdata = pinctrl_dev_get_drvdata(pctldev); 388 388 func = &drvdata->pmx_functions[selector]; ··· 399 397 reg += 4; 400 398 } 401 399 400 + ret = clk_enable(drvdata->pclk); 401 + if (ret) { 402 + dev_err(pctldev->dev, "failed to enable clock for setup\n"); 403 + return ret; 404 + } 405 + 402 406 raw_spin_lock_irqsave(&bank->slock, flags); 403 407 404 408 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); ··· 413 405 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); 414 406 415 407 raw_spin_unlock_irqrestore(&bank->slock, flags); 408 + 409 + clk_disable(drvdata->pclk); 410 + 411 + return 0; 416 412 } 417 413 418 414 /* enable a specified pinmux by writing to registers */ ··· 424 412 unsigned selector, 425 413 unsigned group) 426 414 { 427 - samsung_pinmux_setup(pctldev, selector, group); 428 - return 0; 415 + return samsung_pinmux_setup(pctldev, selector, group); 429 416 } 430 417 431 418 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ ··· 447 436 u32 data, width, pin_offset, mask, shift; 448 437 u32 cfg_value, cfg_reg; 449 438 unsigned long flags; 439 + int ret; 450 440 451 441 drvdata = pinctrl_dev_get_drvdata(pctldev); 452 442 pin_to_reg_bank(drvdata, pin, &reg_base, &pin_offset, &bank); ··· 458 446 459 447 width = type->fld_width[cfg_type]; 460 448 cfg_reg = type->reg_offset[cfg_type]; 449 + 450 + ret = clk_enable(drvdata->pclk); 451 + if (ret) { 452 + dev_err(drvdata->dev, "failed to enable clock\n"); 453 + return ret; 454 + } 461 455 462 456 raw_spin_lock_irqsave(&bank->slock, flags); 463 457 ··· 483 465 } 484 466 485 467 raw_spin_unlock_irqrestore(&bank->slock, flags); 468 + 469 + clk_disable(drvdata->pclk); 486 470 487 471 return 0; 488 472 } ··· 575 555 static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 576 556 { 577 557 struct samsung_pin_bank *bank = gpiochip_get_data(gc); 558 + struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; 578 559 unsigned long flags; 560 + 561 + if (clk_enable(drvdata->pclk)) { 562 + dev_err(drvdata->dev, "failed to enable clock\n"); 563 + return; 564 + } 579 565 580 566 raw_spin_lock_irqsave(&bank->slock, flags); 581 567 samsung_gpio_set_value(gc, offset, value); 582 568 raw_spin_unlock_irqrestore(&bank->slock, flags); 569 + 570 + clk_disable(drvdata->pclk); 583 571 } 584 572 585 573 /* gpiolib gpio_get callback function */ ··· 597 569 u32 data; 598 570 struct samsung_pin_bank *bank = gpiochip_get_data(gc); 599 571 const struct samsung_pin_bank_type *type = bank->type; 572 + struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; 573 + int ret; 600 574 601 575 reg = bank->pctl_base + bank->pctl_offset; 576 + 577 + ret = clk_enable(drvdata->pclk); 578 + if (ret) { 579 + dev_err(drvdata->dev, "failed to enable clock\n"); 580 + return ret; 581 + } 602 582 603 583 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); 604 584 data >>= offset; 605 585 data &= 1; 586 + 587 + clk_disable(drvdata->pclk); 588 + 606 589 return data; 607 590 } 608 591 ··· 658 619 static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 659 620 { 660 621 struct samsung_pin_bank *bank = gpiochip_get_data(gc); 622 + struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; 661 623 unsigned long flags; 662 624 int ret; 625 + 626 + ret = clk_enable(drvdata->pclk); 627 + if (ret) { 628 + dev_err(drvdata->dev, "failed to enable clock\n"); 629 + return ret; 630 + } 663 631 664 632 raw_spin_lock_irqsave(&bank->slock, flags); 665 633 ret = samsung_gpio_set_direction(gc, offset, true); 666 634 raw_spin_unlock_irqrestore(&bank->slock, flags); 635 + 636 + clk_disable(drvdata->pclk); 637 + 667 638 return ret; 668 639 } 669 640 ··· 682 633 int value) 683 634 { 684 635 struct samsung_pin_bank *bank = gpiochip_get_data(gc); 636 + struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; 685 637 unsigned long flags; 686 638 int ret; 639 + 640 + ret = clk_enable(drvdata->pclk); 641 + if (ret) { 642 + dev_err(drvdata->dev, "failed to enable clock\n"); 643 + return ret; 644 + } 687 645 688 646 raw_spin_lock_irqsave(&bank->slock, flags); 689 647 samsung_gpio_set_value(gc, offset, value); 690 648 ret = samsung_gpio_set_direction(gc, offset, false); 691 649 raw_spin_unlock_irqrestore(&bank->slock, flags); 650 + 651 + clk_disable(drvdata->pclk); 692 652 693 653 return ret; 694 654 } ··· 1222 1164 } 1223 1165 } 1224 1166 1167 + drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk"); 1168 + if (IS_ERR(drvdata->pclk)) { 1169 + ret = PTR_ERR(drvdata->pclk); 1170 + goto err_put_banks; 1171 + } 1172 + 1225 1173 ret = samsung_pinctrl_register(pdev, drvdata); 1226 1174 if (ret) 1227 1175 goto err_put_banks; ··· 1266 1202 struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); 1267 1203 int i; 1268 1204 1205 + i = clk_enable(drvdata->pclk); 1206 + if (i) { 1207 + dev_err(drvdata->dev, 1208 + "failed to enable clock for saving state\n"); 1209 + return i; 1210 + } 1211 + 1269 1212 for (i = 0; i < drvdata->nr_banks; i++) { 1270 1213 struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; 1271 1214 const void __iomem *reg = bank->pctl_base + bank->pctl_offset; ··· 1302 1231 } 1303 1232 } 1304 1233 1234 + clk_disable(drvdata->pclk); 1235 + 1305 1236 if (drvdata->suspend) 1306 1237 drvdata->suspend(drvdata); 1307 1238 if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) ··· 1323 1250 static int __maybe_unused samsung_pinctrl_resume(struct device *dev) 1324 1251 { 1325 1252 struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); 1253 + int ret; 1326 1254 int i; 1255 + 1256 + /* 1257 + * enable clock before the callback, as we don't want to have to deal 1258 + * with callback cleanup on clock failures. 1259 + */ 1260 + ret = clk_enable(drvdata->pclk); 1261 + if (ret) { 1262 + dev_err(drvdata->dev, 1263 + "failed to enable clock for restoring state\n"); 1264 + return ret; 1265 + } 1327 1266 1328 1267 if (drvdata->resume) 1329 1268 drvdata->resume(drvdata); ··· 1370 1285 if (widths[type]) 1371 1286 writel(bank->pm_save[type], reg + offs[type]); 1372 1287 } 1288 + 1289 + clk_disable(drvdata->pclk); 1373 1290 1374 1291 if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable) 1375 1292 drvdata->retention_ctrl->disable(drvdata);

+2

drivers/pinctrl/samsung/pinctrl-samsung.h

··· 274 274 * through samsung_pinctrl_drv_data, not samsung_pin_bank). 275 275 * @dev: device instance representing the controller. 276 276 * @irq: interrpt number used by the controller to notify gpio interrupts. 277 + * @pclk: optional bus clock if required for accessing registers 277 278 * @ctrl: pin controller instance managed by the driver. 278 279 * @pctl: pin controller descriptor registered with the pinctrl subsystem. 279 280 * @pctl_dev: cookie representing pinctrl device instance. ··· 294 293 void __iomem *virt_base; 295 294 struct device *dev; 296 295 int irq; 296 + struct clk *pclk; 297 297 298 298 struct pinctrl_desc pctl; 299 299 struct pinctrl_dev *pctl_dev;

-1

drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c

··· 169 169 .probe = sun9i_a80_r_pinctrl_probe, 170 170 .driver = { 171 171 .name = "sun9i-a80-r-pinctrl", 172 - .owner = THIS_MODULE, 173 172 .of_match_table = sun9i_a80_r_pinctrl_match, 174 173 }, 175 174 };

-95

include/dt-bindings/pinctrl/samsung.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Samsung's Exynos pinctrl bindings 4 - * 5 - * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 - * http://www.samsung.com 7 - * Author: Krzysztof Kozlowski <krzk@kernel.org> 8 - */ 9 - 10 - #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 11 - #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 12 - 13 - /* 14 - * These bindings are deprecated, because they do not match the actual 15 - * concept of bindings but rather contain pure register values. 16 - * Instead include the header in the DTS source directory. 17 - */ 18 - #warning "These bindings are deprecated. Instead use the header in the DTS source directory." 19 - 20 - #define EXYNOS_PIN_PULL_NONE 0 21 - #define EXYNOS_PIN_PULL_DOWN 1 22 - #define EXYNOS_PIN_PULL_UP 3 23 - 24 - #define S3C64XX_PIN_PULL_NONE 0 25 - #define S3C64XX_PIN_PULL_DOWN 1 26 - #define S3C64XX_PIN_PULL_UP 2 27 - 28 - /* Pin function in power down mode */ 29 - #define EXYNOS_PIN_PDN_OUT0 0 30 - #define EXYNOS_PIN_PDN_OUT1 1 31 - #define EXYNOS_PIN_PDN_INPUT 2 32 - #define EXYNOS_PIN_PDN_PREV 3 33 - 34 - /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 35 - #define EXYNOS4_PIN_DRV_LV1 0 36 - #define EXYNOS4_PIN_DRV_LV2 2 37 - #define EXYNOS4_PIN_DRV_LV3 1 38 - #define EXYNOS4_PIN_DRV_LV4 3 39 - 40 - /* Drive strengths for Exynos5260 */ 41 - #define EXYNOS5260_PIN_DRV_LV1 0 42 - #define EXYNOS5260_PIN_DRV_LV2 1 43 - #define EXYNOS5260_PIN_DRV_LV4 2 44 - #define EXYNOS5260_PIN_DRV_LV6 3 45 - 46 - /* 47 - * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except 48 - * GPIO_HSI block) 49 - */ 50 - #define EXYNOS5420_PIN_DRV_LV1 0 51 - #define EXYNOS5420_PIN_DRV_LV2 1 52 - #define EXYNOS5420_PIN_DRV_LV3 2 53 - #define EXYNOS5420_PIN_DRV_LV4 3 54 - 55 - /* Drive strengths for Exynos5433 */ 56 - #define EXYNOS5433_PIN_DRV_FAST_SR1 0 57 - #define EXYNOS5433_PIN_DRV_FAST_SR2 1 58 - #define EXYNOS5433_PIN_DRV_FAST_SR3 2 59 - #define EXYNOS5433_PIN_DRV_FAST_SR4 3 60 - #define EXYNOS5433_PIN_DRV_FAST_SR5 4 61 - #define EXYNOS5433_PIN_DRV_FAST_SR6 5 62 - #define EXYNOS5433_PIN_DRV_SLOW_SR1 8 63 - #define EXYNOS5433_PIN_DRV_SLOW_SR2 9 64 - #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa 65 - #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb 66 - #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc 67 - #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf 68 - 69 - /* Drive strengths for Exynos850 GPIO_HSI block */ 70 - #define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ 71 - #define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ 72 - #define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ 73 - #define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ 74 - #define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ 75 - #define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ 76 - 77 - #define EXYNOS_PIN_FUNC_INPUT 0 78 - #define EXYNOS_PIN_FUNC_OUTPUT 1 79 - #define EXYNOS_PIN_FUNC_2 2 80 - #define EXYNOS_PIN_FUNC_3 3 81 - #define EXYNOS_PIN_FUNC_4 4 82 - #define EXYNOS_PIN_FUNC_5 5 83 - #define EXYNOS_PIN_FUNC_6 6 84 - #define EXYNOS_PIN_FUNC_EINT 0xf 85 - #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 86 - 87 - /* Drive strengths for Exynos7 FSYS1 block */ 88 - #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 89 - #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 90 - #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 91 - #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 92 - #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 93 - #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 94 - 95 - #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */