Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
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linux
[ARM] tegra: Add timer support
v2: fixes from Russell King:
- include linux/io.h instead of asm/io.h
fixes from Gary King:
- remove extra (and incorrect) irq definitions
- use timer 3 instead of timer 1 for compatibility with other drivers
- fix typo that disabled oneshot mode
v3:
- Implement sched_clock
- Fix checkpatch issues
fixes from Gary King:
- Fix incorrect cycles calculation
- Fix min_delta_ns assignment
fixes from Linus Walleij:
- use calc_mult_shift() instead of hard coding values
Signed-off-by: Colin Cross <ccross@android.com>
authored by Colin Cross and committed by Erik Gilling 2d5cd9a3 1cea7326
+1
arch/arm/mach-tegra/Makefile
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arch/arm/mach-tegra/Makefile
+187
arch/arm/mach-tegra/timer.c
+187
arch/arm/mach-tegra/timer.c
···
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/*
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* arch/arch/mach-tegra/timer.c
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/cnt32_to_63.h>
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#include <asm/mach/time.h>
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#include <asm/mach/time.h>
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#include <asm/localtimer.h>
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#include <mach/iomap.h>
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#include <mach/irqs.h>
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#include "board.h"
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#include "clock.h"
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#define TIMERUS_CNTR_1US 0x10
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#define TIMERUS_USEC_CFG 0x14
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#define TIMERUS_CNTR_FREEZE 0x4c
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#define TIMER1_BASE 0x0
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#define TIMER2_BASE 0x8
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#define TIMER3_BASE 0x50
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#define TIMER4_BASE 0x58
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#define TIMER_PTV 0x0
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#define TIMER_PCR 0x4
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struct tegra_timer;
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static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
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#define timer_writel(value, reg) \
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__raw_writel(value, (u32)timer_reg_base + (reg))
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#define timer_readl(reg) \
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__raw_readl((u32)timer_reg_base + (reg))
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static int tegra_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 reg;
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reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
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timer_writel(reg, TIMER3_BASE + TIMER_PTV);
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return 0;
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}
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static void tegra_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 reg;
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timer_writel(0, TIMER3_BASE + TIMER_PTV);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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reg = 0xC0000000 | ((1000000/HZ)-1);
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timer_writel(reg, TIMER3_BASE + TIMER_PTV);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static cycle_t tegra_clocksource_read(struct clocksource *cs)
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{
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return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US));
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}
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static struct clock_event_device tegra_clockevent = {
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.name = "timer0",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.set_next_event = tegra_timer_set_next_event,
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.set_mode = tegra_timer_set_mode,
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};
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static struct clocksource tegra_clocksource = {
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.name = "timer_us",
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.rating = 300,
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.read = tegra_clocksource_read,
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.mask = 0x7FFFFFFFFFFFFFFFULL,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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unsigned long long sched_clock(void)
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{
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return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource),
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tegra_clocksource.mult, tegra_clocksource.shift);
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}
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static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction tegra_timer_irq = {
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.name = "timer0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
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.handler = tegra_timer_interrupt,
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.dev_id = &tegra_clockevent,
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.irq = INT_TMR3,
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};
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static void __init tegra_init_timer(void)
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{
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unsigned long rate = clk_measure_input_freq();
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int ret;
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#ifdef CONFIG_HAVE_ARM_TWD
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twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
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#endif
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switch (rate) {
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case 12000000:
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timer_writel(0x000b, TIMERUS_USEC_CFG);
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break;
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case 13000000:
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timer_writel(0x000c, TIMERUS_USEC_CFG);
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break;
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case 19200000:
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timer_writel(0x045f, TIMERUS_USEC_CFG);
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break;
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case 26000000:
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timer_writel(0x0019, TIMERUS_USEC_CFG);
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break;
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default:
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WARN(1, "Unknown clock rate");
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}
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if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
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printk(KERN_ERR "Failed to register clocksource\n");
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BUG();
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}
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ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
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if (ret) {
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printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
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BUG();
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}
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clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
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tegra_clockevent.max_delta_ns =
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clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
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tegra_clockevent.min_delta_ns =
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clockevent_delta2ns(0x1, &tegra_clockevent);
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tegra_clockevent.cpumask = cpu_all_mask;
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tegra_clockevent.irq = tegra_timer_irq.irq;
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clockevents_register_device(&tegra_clockevent);
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return;
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}
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struct sys_timer tegra_timer = {
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.init = tegra_init_timer,
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};