tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'common/mmcif' into rmobile/mmcif
+34
-28
-23
drivers/mmc/host/sh_mmcif.c
-23
drivers/mmc/host/sh_mmcif.c
···
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/* CE_BLOCK_SET */
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#define BLOCK_SIZE_MASK 0x0000ffff
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-
/* CE_CLK_CTRL */
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#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
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#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
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#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
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(1 << 9) | (1 << 8)) /* resp busy timeout */
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#define SRWDTO_29 ((1 << 7) | (1 << 6) | \
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(1 << 5) | (1 << 4)) /* read/write timeout */
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#define SCCSTO_29 ((1 << 3) | (1 << 2) | \
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(1 << 1) | (1 << 0)) /* ccs timeout */
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-
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/* CE_BUF_ACC */
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#define BUF_ACC_DMAWEN (1 << 25)
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#define BUF_ACC_DMAREN (1 << 24)
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#define BUF_ACC_BUSW_32 (0 << 17)
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#define BUF_ACC_BUSW_16 (1 << 17)
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#define BUF_ACC_ATYP (1 << 16)
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-
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/* CE_INT */
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#define INT_CCSDE (1 << 29)
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#define INT_CMD12DRE (1 << 26)
···
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STS2_DATBSYTO | STS2_CRCSTTO | \
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STS2_AC12BSYTO | STS2_RSPBSYTO | \
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STS2_AC12RSPTO | STS2_RSPTO)
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-
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/* CE_VERSION */
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#define SOFT_RST_ON (1 << 31)
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#define SOFT_RST_OFF (0 << 31)
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#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
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#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
+34
-5
include/linux/mmc/sh_mmcif.h
+34
-5
include/linux/mmc/sh_mmcif.h
···
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#define MMCIF_CE_HOST_STS2 0x0000004C
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#define MMCIF_CE_VERSION 0x0000007C
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+
/* CE_BUF_ACC */
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+
#define BUF_ACC_DMAWEN (1 << 25)
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+
#define BUF_ACC_DMAREN (1 << 24)
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+
#define BUF_ACC_BUSW_32 (0 << 17)
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+
#define BUF_ACC_BUSW_16 (1 << 17)
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+
#define BUF_ACC_ATYP (1 << 16)
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+
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/* CE_CLK_CTRL */
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#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
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+
#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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+
#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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+
#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
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+
#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
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+
(1 << 9) | (1 << 8)) /* resp busy timeout */
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+
#define SRWDTO_29 ((1 << 7) | (1 << 6) | \
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(1 << 5) | (1 << 4)) /* read/write timeout */
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+
#define SCCSTO_29 ((1 << 3) | (1 << 2) | \
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(1 << 1) | (1 << 0)) /* ccs timeout */
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+
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/* CE_VERSION */
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#define SOFT_RST_ON (1 << 31)
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#define SOFT_RST_OFF ~SOFT_RST_ON
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+
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static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
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{
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return readl(addr + reg);
···
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/* reset */
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tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
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-
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
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sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
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+
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON);
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sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF);
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/* byte swap */
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-
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
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+
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
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/* Set block size in MMCIF hardware */
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sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
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-
/* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
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sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
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+
/* Enable the clock, set it to Bus clock/256 (about 325Khz).
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* It is unclear where 0x70000 comes from or if it is even needed.
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* It is there for byte-compatibility with code that is known to
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+
* work.
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+
*/
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+
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
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+
CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |
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+
SCCSTO_29 | 0x70000);
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/* CMD0 */
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sh_mmcif_boot_cmd(base, 0x00000040, 0);