tjh.dev / kernel
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kernel os linux
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ARM: dts: Fix wrong clocks for dra7 mcasp

The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
This causes the following warning on beagle-x15:

ti-sysc 48468000.target-module: could not add child clock ahclkr: -19

Also the mcasp clkctrl clock bits are wrong:

For mcasp1 and 2 we have four clocks at bits 28, 24, 22 and 0:

bit 28 is ahclkr
bit 24 is ahclkx
bit 22 is auxclk
bit 0 is fck

For mcasp3 to 8 we have three clocks at bits 24, 22 and 0.

bit 24 is ahclkx
bit 22 is auxclk
bit 0 is fck

We do not have currently mapped auxclk at bit 22 for the drivers, that can
be added if needed.

Fixes: 5241ccbf2819 ("ARM: dts: Add missing ranges for dra7 mcasp l3 ports")
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Tony Lindgren 2d3c8ba3 dd8882a2

+21 -27
+21 -27
arch/arm/boot/dts/dra7-l4.dtsi
··· 2762 2762 interrupt-names = "tx", "rx"; 2763 2763 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 2764 2764 dma-names = "tx", "rx"; 2765 - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, 2765 + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2766 2766 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2767 2767 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2768 2768 clock-names = "fck", "ahclkx", "ahclkr"; ··· 2799 2799 interrupt-names = "tx", "rx"; 2800 2800 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 2801 2801 dma-names = "tx", "rx"; 2802 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, 2803 - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, 2802 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2803 + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2804 2804 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2805 2805 clock-names = "fck", "ahclkx", "ahclkr"; 2806 2806 status = "disabled"; ··· 2818 2818 <SYSC_IDLE_SMART>; 2819 2819 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2820 2820 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2821 - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, 2822 - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; 2823 - clock-names = "fck", "ahclkx", "ahclkr"; 2821 + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2822 + clock-names = "fck", "ahclkx"; 2824 2823 #address-cells = <1>; 2825 2824 #size-cells = <1>; 2826 2825 ranges = <0x0 0x68000 0x2000>, ··· 2835 2836 interrupt-names = "tx", "rx"; 2836 2837 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 2837 2838 dma-names = "tx", "rx"; 2838 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, 2839 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2839 2840 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2840 2841 clock-names = "fck", "ahclkx"; 2841 2842 status = "disabled"; ··· 2853 2854 <SYSC_IDLE_SMART>; 2854 2855 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2855 2856 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2856 - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, 2857 - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; 2858 - clock-names = "fck", "ahclkx", "ahclkr"; 2857 + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2858 + clock-names = "fck", "ahclkx"; 2859 2859 #address-cells = <1>; 2860 2860 #size-cells = <1>; 2861 2861 ranges = <0x0 0x6c000 0x2000>, ··· 2870 2872 interrupt-names = "tx", "rx"; 2871 2873 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 2872 2874 dma-names = "tx", "rx"; 2873 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, 2875 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2874 2876 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2875 2877 clock-names = "fck", "ahclkx"; 2876 2878 status = "disabled"; ··· 2888 2890 <SYSC_IDLE_SMART>; 2889 2891 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2890 2892 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2891 - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, 2892 - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; 2893 - clock-names = "fck", "ahclkx", "ahclkr"; 2893 + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2894 + clock-names = "fck", "ahclkx"; 2894 2895 #address-cells = <1>; 2895 2896 #size-cells = <1>; 2896 2897 ranges = <0x0 0x70000 0x2000>, ··· 2905 2908 interrupt-names = "tx", "rx"; 2906 2909 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 2907 2910 dma-names = "tx", "rx"; 2908 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, 2911 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2909 2912 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2910 2913 clock-names = "fck", "ahclkx"; 2911 2914 status = "disabled"; ··· 2923 2926 <SYSC_IDLE_SMART>; 2924 2927 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2925 2928 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2926 - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, 2927 - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; 2928 - clock-names = "fck", "ahclkx", "ahclkr"; 2929 + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2930 + clock-names = "fck", "ahclkx"; 2929 2931 #address-cells = <1>; 2930 2932 #size-cells = <1>; 2931 2933 ranges = <0x0 0x74000 0x2000>, ··· 2940 2944 interrupt-names = "tx", "rx"; 2941 2945 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 2942 2946 dma-names = "tx", "rx"; 2943 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, 2947 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2944 2948 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2945 2949 clock-names = "fck", "ahclkx"; 2946 2950 status = "disabled"; ··· 2958 2962 <SYSC_IDLE_SMART>; 2959 2963 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2960 2964 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2961 - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, 2962 - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; 2963 - clock-names = "fck", "ahclkx", "ahclkr"; 2965 + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2966 + clock-names = "fck", "ahclkx"; 2964 2967 #address-cells = <1>; 2965 2968 #size-cells = <1>; 2966 2969 ranges = <0x0 0x78000 0x2000>, ··· 2975 2980 interrupt-names = "tx", "rx"; 2976 2981 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 2977 2982 dma-names = "tx", "rx"; 2978 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, 2983 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2979 2984 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2980 2985 clock-names = "fck", "ahclkx"; 2981 2986 status = "disabled"; ··· 2993 2998 <SYSC_IDLE_SMART>; 2994 2999 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2995 3000 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 2996 - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, 2997 - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; 2998 - clock-names = "fck", "ahclkx", "ahclkr"; 3001 + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3002 + clock-names = "fck", "ahclkx"; 2999 3003 #address-cells = <1>; 3000 3004 #size-cells = <1>; 3001 3005 ranges = <0x0 0x7c000 0x2000>, ··· 3010 3016 interrupt-names = "tx", "rx"; 3011 3017 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 3012 3018 dma-names = "tx", "rx"; 3013 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, 3019 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 3014 3020 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3015 3021 clock-names = "fck", "ahclkx"; 3016 3022 status = "disabled";