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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: SAMSUNG: Convert irq-vic-timer to generic irq chip
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
authored by
Thomas Gleixner
and committed by
Mark Brown
2d2e1d3c
ad739dcf
+29
-55
+1
-6
arch/arm/mach-s3c64xx/irq.c
+1
-6
arch/arm/mach-s3c64xx/irq.c
···
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vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
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/* add the timer sub-irqs */
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-
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s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
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s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
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s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
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s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
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s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
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s3c_init_vic_timer_irq(5, IRQ_TIMER0);
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s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
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}
+1
-5
arch/arm/plat-s5p/irq.c
+1
-5
arch/arm/plat-s5p/irq.c
···
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vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
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#endif
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s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
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s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
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s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
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s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
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s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
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s3c_init_vic_timer_irq(5, IRQ_TIMER0);
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s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
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}
+1
-1
arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+1
-1
arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+26
-43
arch/arm/plat-samsung/irq-vic-timer.c
+26
-43
arch/arm/plat-samsung/irq-vic-timer.c
···
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}
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/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
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static void s3c_irq_timer_mask(struct irq_data *data)
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static void s3c_irq_timer_ack(struct irq_data *d)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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u32 mask = (u32)data->chip_data;
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = (1 << 5) << (d->irq - gc->irq_base);
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reg &= 0x1f; /* mask out pending interrupts */
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reg &= ~mask;
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
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}
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static void s3c_irq_timer_unmask(struct irq_data *data)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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u32 mask = (u32)data->chip_data;
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reg &= 0x1f; /* mask out pending interrupts */
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reg |= mask;
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_ack(struct irq_data *data)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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u32 mask = (u32)data->chip_data;
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reg &= 0x1f;
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reg |= mask << 5;
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static struct irq_chip s3c_irq_timer = {
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.name = "s3c-timer",
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.irq_mask = s3c_irq_timer_mask,
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.irq_unmask = s3c_irq_timer_unmask,
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.irq_ack = s3c_irq_timer_ack,
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};
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/**
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* s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
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* @parent_irq: The parent IRQ on the VIC for the timer.
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* @timer_irq: The IRQ to be used for the timer.
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* @num: Number of timers to initialize
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* @timer_irq: Base IRQ number to be used for the timers.
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*
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* Register the necessary IRQ chaining and support for the timer IRQs
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* chained of the VIC.
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*/
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void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
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unsigned int timer_irq)
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void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
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{
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unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
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IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
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struct irq_chip_generic *s3c_tgc;
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struct irq_chip_type *ct;
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unsigned int i;
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irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
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irq_set_handler_data(parent_irq, (void *)timer_irq);
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s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
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S3C64XX_TINT_CSTAT, handle_level_irq);
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ct = s3c_tgc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = s3c_irq_timer_ack;
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irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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/* Clear the upper bits of the mask_cache*/
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s3c_tgc->mask_cache &= 0x1f;
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irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
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irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
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set_irq_flags(timer_irq, IRQF_VALID);
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for (i = 0; i < num; i++, timer_irq++) {
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irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
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irq_set_handler_data(pirq[i], (void *)timer_irq);
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}
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}