tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

MIPS: TXx9: Modernize printing of kernel messages

- Convert from printk() to pr_*(),
- Add missing continuations, to fix user-visible breakage,
- Drop superfluous casts (u64 has been unsigned long long on all
architectures for many years).

On rbtx4927, this restores the kernel output like:

-TX4927 SDRAMC --
- CR0:0000007e00000544
- TR:32800030e
+TX4927 SDRAMC -- CR0:0000007e00000544 TR:32800030e

and:

-PCIC -- PCICLK:
-Internal(33.3MHz)
-
+PCIC -- PCICLK:Internal(33.3MHz)

Fixes: 4bcc595ccd80decb ("printk: reinstate KERN_CONT for printing continuation lines")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14646/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Geert Uytterhoeven and committed by
Ralf Baechle 2cec11d8 2b58a76e

+92 -102
+11 -11
arch/mips/pci/pci-tx4927.c
··· 21 21 { 22 22 int pciclk = 0; 23 23 24 - printk(KERN_INFO "PCIC --%s PCICLK:", 25 - (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ? 26 - " PCI66" : ""); 24 + pr_info("PCIC --%s PCICLK:", 25 + (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ? 26 + " PCI66" : ""); 27 27 if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { 28 28 u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); 29 29 switch ((unsigned long)ccfg & ··· 37 37 case TX4927_CCFG_PCIDIVMODE_6: 38 38 pciclk = txx9_cpu_clock / 6; break; 39 39 } 40 - printk("Internal(%u.%uMHz)", 41 - (pciclk + 50000) / 1000000, 42 - ((pciclk + 50000) / 100000) % 10); 40 + pr_cont("Internal(%u.%uMHz)", 41 + (pciclk + 50000) / 1000000, 42 + ((pciclk + 50000) / 100000) % 10); 43 43 } else { 44 - printk("External"); 44 + pr_cont("External"); 45 45 pciclk = -1; 46 46 } 47 - printk("\n"); 47 + pr_cont("\n"); 48 48 return pciclk; 49 49 } 50 50 ··· 74 74 } 75 75 tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK, 76 76 pcidivmode); 77 - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", 78 - (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg)); 77 + pr_debug("PCICLK: ccfg:%08lx\n", 78 + (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg)); 79 79 } else 80 80 pciclk = -1; 81 81 return pciclk; ··· 87 87 tx4927_pcierr_interrupt, 88 88 0, "PCI error", 89 89 (void *)TX4927_PCIC_REG)) 90 - printk(KERN_WARNING "Failed to request irq for PCIERR\n"); 90 + pr_warn("Failed to request irq for PCIERR\n"); 91 91 }
+15 -15
arch/mips/pci/pci-tx4938.c
··· 21 21 { 22 22 int pciclk = 0; 23 23 24 - printk(KERN_INFO "PCIC --%s PCICLK:", 25 - (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ? 26 - " PCI66" : ""); 24 + pr_info("PCIC --%s PCICLK:", 25 + (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ? 26 + " PCI66" : ""); 27 27 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { 28 28 u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); 29 29 switch ((unsigned long)ccfg & ··· 45 45 case TX4938_CCFG_PCIDIVMODE_11: 46 46 pciclk = txx9_cpu_clock / 11; break; 47 47 } 48 - printk("Internal(%u.%uMHz)", 49 - (pciclk + 50000) / 1000000, 50 - ((pciclk + 50000) / 100000) % 10); 48 + pr_cont("Internal(%u.%uMHz)", 49 + (pciclk + 50000) / 1000000, 50 + ((pciclk + 50000) / 100000) % 10); 51 51 } else { 52 - printk("External"); 52 + pr_cont("External"); 53 53 pciclk = -1; 54 54 } 55 - printk("\n"); 55 + pr_cont("\n"); 56 56 return pciclk; 57 57 } 58 58 ··· 62 62 unsigned int pciclk = 63 63 txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2); 64 64 65 - printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n", 66 - (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "", 67 - (pciclk + 50000) / 1000000, 68 - ((pciclk + 50000) / 100000) % 10); 65 + pr_info("PCIC1 -- %sPCICLK:%u.%uMHz\n", 66 + (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "", 67 + (pciclk + 50000) / 1000000, 68 + ((pciclk + 50000) / 100000) % 10); 69 69 } 70 70 71 71 int __init tx4938_pciclk66_setup(void) ··· 105 105 } 106 106 tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK, 107 107 pcidivmode); 108 - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", 109 - (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg)); 108 + pr_debug("PCICLK: ccfg:%08lx\n", 109 + (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg)); 110 110 } else 111 111 pciclk = -1; 112 112 return pciclk; ··· 138 138 tx4927_pcierr_interrupt, 139 139 0, "PCI error", 140 140 (void *)TX4927_PCIC_REG)) 141 - printk(KERN_WARNING "Failed to request irq for PCIERR\n"); 141 + pr_warn("Failed to request irq for PCIERR\n"); 142 142 }
+5 -5
arch/mips/pci/pci-tx4939.c
··· 28 28 pciclk = txx9_master_clock * 20 / 6; 29 29 if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66)) 30 30 pciclk /= 2; 31 - printk(KERN_CONT "Internal(%u.%uMHz)", 32 - (pciclk + 50000) / 1000000, 33 - ((pciclk + 50000) / 100000) % 10); 31 + pr_cont("Internal(%u.%uMHz)", 32 + (pciclk + 50000) / 1000000, 33 + ((pciclk + 50000) / 100000) % 10); 34 34 } else { 35 - printk(KERN_CONT "External"); 35 + pr_cont("External"); 36 36 pciclk = -1; 37 37 } 38 - printk(KERN_CONT "\n"); 38 + pr_cont("\n"); 39 39 return pciclk; 40 40 } 41 41
+13 -15
arch/mips/txx9/generic/pci.c
··· 55 55 /* It seems SLC90E66 needs some time after PCI reset... */ 56 56 mdelay(80); 57 57 58 - printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); 58 + pr_info("PCI: Checking 66MHz capabilities...\n"); 59 59 60 60 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 61 61 if (PCI_FUNC(pci_devfn)) ··· 74 74 early_read_config_word(hose, top_bus, current_bus, 75 75 pci_devfn, PCI_STATUS, &stat); 76 76 if (!(stat & PCI_STATUS_66MHZ)) { 77 - printk(KERN_DEBUG 78 - "PCI: %02x:%02x not 66MHz capable.\n", 79 - current_bus, pci_devfn); 77 + pr_debug("PCI: %02x:%02x not 66MHz capable.\n", 78 + current_bus, pci_devfn); 80 79 cap66 = 0; 81 80 break; 82 81 } ··· 208 209 209 210 pcic->mem_offset = 0; /* busaddr == physaddr */ 210 211 211 - printk(KERN_INFO "PCI: IO %pR MEM %pR\n", 212 - &pcic->mem_resource[1], &pcic->mem_resource[0]); 212 + pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1], 213 + &pcic->mem_resource[0]); 213 214 214 215 /* register_pci_controller() will request MEM resource */ 215 216 release_resource(&pcic->mem_resource[0]); ··· 218 219 release_resource(&pcic->mem_resource[0]); 219 220 free_and_exit: 220 221 kfree(new); 221 - printk(KERN_ERR "PCI: Failed to allocate resources.\n"); 222 + pr_err("PCI: Failed to allocate resources.\n"); 222 223 return NULL; 223 224 } 224 225 ··· 259 260 err = request_irq(irq, &i8259_interrupt, IRQF_SHARED, 260 261 "cascade(i8259)", (void *)(long)irq); 261 262 if (!err) 262 - printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); 263 + pr_info("PCI-ISA bridge PIC (irq %d)\n", irq); 263 264 return err; 264 265 } 265 266 ··· 307 308 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ 308 309 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14); 309 310 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat); 310 - printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); 311 + pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat); 311 312 /* enable SMSC SLC90E66 IDE */ 312 313 for (i = 0; i < ARRAY_SIZE(regs); i++) { 313 314 pci_read_config_byte(dev, regs[i], &dat); 314 315 pci_write_config_byte(dev, regs[i], dat | 0x80); 315 316 pci_read_config_byte(dev, regs[i], &dat); 316 - printk(KERN_CONT " IDETIM%d %02x", i, dat); 317 + pr_cont(" IDETIM%d %02x", i, dat); 317 318 } 318 319 pci_read_config_byte(dev, 0x5c, &dat); 319 320 /* ··· 328 329 dat |= 0x01; 329 330 pci_write_config_byte(dev, 0x5c, dat); 330 331 pci_read_config_byte(dev, 0x5c, &dat); 331 - printk(KERN_CONT " REG5C %02x", dat); 332 - printk(KERN_CONT "\n"); 332 + pr_cont(" REG5C %02x\n", dat); 333 333 } 334 334 #endif /* CONFIG_TOSHIBA_FPCIB0 */ 335 335 ··· 350 352 (bist & PCI_BIST_CAPABLE)) { 351 353 unsigned long timeout; 352 354 pci_set_power_state(dev, PCI_D0); 353 - printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); 355 + pr_info("PCI: %s BIST...", pci_name(dev)); 354 356 pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); 355 357 timeout = jiffies + HZ * 2; /* timeout after 2 sec */ 356 358 do { ··· 359 361 break; 360 362 } while (bist & PCI_BIST_START); 361 363 if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) 362 - printk(KERN_CONT "failed. (0x%x)\n", bist); 364 + pr_cont("failed. (0x%x)\n", bist); 363 365 else 364 - printk(KERN_CONT "OK.\n"); 366 + pr_cont("OK.\n"); 365 367 } 366 368 } 367 369
+3 -3
arch/mips/txx9/generic/setup_tx3927.c
··· 67 67 /* do reset on watchdog */ 68 68 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; 69 69 70 - printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", 71 - tx3927_ccfgptr->crir, 72 - tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); 70 + pr_info("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", 71 + tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg, 72 + tx3927_ccfgptr->pcfg); 73 73 74 74 /* TMR */ 75 75 for (i = 0; i < TX3927_NR_TMR; i++)
+9 -11
arch/mips/txx9/generic/setup_tx4927.c
··· 183 183 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB)) 184 184 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL); 185 185 186 - printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 187 - txx9_pcode_str, 188 - (cpuclk + 500000) / 1000000, 189 - (txx9_master_clock + 500000) / 1000000, 190 - (__u32)____raw_readq(&tx4927_ccfgptr->crir), 191 - (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg), 192 - (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg)); 186 + pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 187 + txx9_pcode_str, (cpuclk + 500000) / 1000000, 188 + (txx9_master_clock + 500000) / 1000000, 189 + (__u32)____raw_readq(&tx4927_ccfgptr->crir), 190 + ____raw_readq(&tx4927_ccfgptr->ccfg), 191 + ____raw_readq(&tx4927_ccfgptr->pcfg)); 193 192 194 - printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 193 + pr_info("%s SDRAMC --", txx9_pcode_str); 195 194 for (i = 0; i < 4; i++) { 196 195 __u64 cr = TX4927_SDRAMC_CR(i); 197 196 unsigned long base, size; ··· 198 199 continue; /* disabled */ 199 200 base = (unsigned long)(cr >> 49) << 21; 200 201 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; 201 - printk(" CR%d:%016llx", i, (unsigned long long)cr); 202 + pr_cont(" CR%d:%016llx", i, cr); 202 203 tx4927_sdram_resource[i].name = "SDRAM"; 203 204 tx4927_sdram_resource[i].start = base; 204 205 tx4927_sdram_resource[i].end = base + size - 1; 205 206 tx4927_sdram_resource[i].flags = IORESOURCE_MEM; 206 207 request_resource(&iomem_resource, &tx4927_sdram_resource[i]); 207 208 } 208 - printk(" TR:%09llx\n", 209 - (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr)); 209 + pr_cont(" TR:%09llx\n", ____raw_readq(&tx4927_sdramcptr->tr)); 210 210 211 211 /* TMR */ 212 212 /* disable all timers */
+12 -14
arch/mips/txx9/generic/setup_tx4938.c
··· 196 196 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) 197 197 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); 198 198 199 - printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 200 - txx9_pcode_str, 201 - (cpuclk + 500000) / 1000000, 202 - (txx9_master_clock + 500000) / 1000000, 203 - (__u32)____raw_readq(&tx4938_ccfgptr->crir), 204 - (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), 205 - (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); 199 + pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 200 + txx9_pcode_str, (cpuclk + 500000) / 1000000, 201 + (txx9_master_clock + 500000) / 1000000, 202 + (__u32)____raw_readq(&tx4938_ccfgptr->crir), 203 + ____raw_readq(&tx4938_ccfgptr->ccfg), 204 + ____raw_readq(&tx4938_ccfgptr->pcfg)); 206 205 207 - printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 206 + pr_info("%s SDRAMC --", txx9_pcode_str); 208 207 for (i = 0; i < 4; i++) { 209 208 __u64 cr = TX4938_SDRAMC_CR(i); 210 209 unsigned long base, size; ··· 211 212 continue; /* disabled */ 212 213 base = (unsigned long)(cr >> 49) << 21; 213 214 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; 214 - printk(" CR%d:%016llx", i, (unsigned long long)cr); 215 + pr_cont(" CR%d:%016llx", i, cr); 215 216 tx4938_sdram_resource[i].name = "SDRAM"; 216 217 tx4938_sdram_resource[i].start = base; 217 218 tx4938_sdram_resource[i].end = base + size - 1; 218 219 tx4938_sdram_resource[i].flags = IORESOURCE_MEM; 219 220 request_resource(&iomem_resource, &tx4938_sdram_resource[i]); 220 221 } 221 - printk(" TR:%09llx\n", 222 - (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr)); 222 + pr_cont(" TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr)); 223 223 224 224 /* SRAM */ 225 225 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) { ··· 252 254 txx9_clear64(&tx4938_ccfgptr->clkctr, 253 255 TX4938_CLKCTR_PCIC1RST); 254 256 } else { 255 - printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str); 257 + pr_info("%s: stop PCIC1\n", txx9_pcode_str); 256 258 /* stop PCIC1 */ 257 259 txx9_set64(&tx4938_ccfgptr->clkctr, 258 260 TX4938_CLKCTR_PCIC1CKD); 259 261 } 260 262 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) { 261 - printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str); 263 + pr_info("%s: stop ETH0\n", txx9_pcode_str); 262 264 txx9_set64(&tx4938_ccfgptr->clkctr, 263 265 TX4938_CLKCTR_ETH0RST); 264 266 txx9_set64(&tx4938_ccfgptr->clkctr, 265 267 TX4938_CLKCTR_ETH0CKD); 266 268 } 267 269 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) { 268 - printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str); 270 + pr_info("%s: stop ETH1\n", txx9_pcode_str); 269 271 txx9_set64(&tx4938_ccfgptr->clkctr, 270 272 TX4938_CLKCTR_ETH1RST); 271 273 txx9_set64(&tx4938_ccfgptr->clkctr,
+4 -4
arch/mips/txx9/generic/setup_tx4939.c
··· 221 221 (txx9_master_clock + 500000) / 1000000, 222 222 (txx9_gbus_clock + 500000) / 1000000, 223 223 (__u32)____raw_readq(&tx4939_ccfgptr->crir), 224 - (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg), 225 - (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg)); 224 + ____raw_readq(&tx4939_ccfgptr->ccfg), 225 + ____raw_readq(&tx4939_ccfgptr->pcfg)); 226 226 227 227 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str, 228 228 (__u32)____raw_readq(&tx4939_ddrcptr->winen)); ··· 230 230 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]); 231 231 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i))) 232 232 continue; /* disabled */ 233 - printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win); 233 + pr_cont(" #%d:%016llx", i, win); 234 234 tx4939_sdram_resource[i].name = "DDR SDRAM"; 235 235 tx4939_sdram_resource[i].start = 236 236 (unsigned long)(win >> 48) << 20; ··· 240 240 tx4939_sdram_resource[i].flags = IORESOURCE_MEM; 241 241 request_resource(&iomem_resource, &tx4939_sdram_resource[i]); 242 242 } 243 - printk(KERN_CONT "\n"); 243 + pr_cont("\n"); 244 244 245 245 /* SRAM */ 246 246 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
+7 -10
arch/mips/txx9/generic/smsc_fdc37m81x.c
··· 105 105 u8 chip_id; 106 106 107 107 if (g_smsc_fdc37m81x_base) 108 - printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n", 109 - __func__, 110 - field, g_smsc_fdc37m81x_base); 108 + pr_warn("%s: stepping on old base=0x%0*lx\n", __func__, field, 109 + g_smsc_fdc37m81x_base); 111 110 112 111 g_smsc_fdc37m81x_base = port; 113 112 ··· 116 117 if (chip_id == SMSC_FDC37M81X_CHIP_ID) 117 118 smsc_fdc37m81x_config_end(); 118 119 else { 119 - printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__, 120 - chip_id); 120 + pr_warn("%s: unknown chip id 0x%02x\n", __func__, chip_id); 121 121 g_smsc_fdc37m81x_base = 0; 122 122 } 123 123 ··· 126 128 #ifdef DEBUG 127 129 static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg) 128 130 { 129 - printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n", 130 - key, dev, reg, 131 - smsc_fdc37m81x_rd(reg)); 131 + pr_info("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, 132 + smsc_fdc37m81x_rd(reg)); 132 133 } 133 134 134 135 void smsc_fdc37m81x_config_dump(void) ··· 139 142 140 143 orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); 141 144 142 - printk(KERN_INFO "%s: common\n", fname); 145 + pr_info("%s: common\n", fname); 143 146 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, 144 147 SMSC_FDC37M81X_DNUM); 145 148 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, ··· 151 154 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, 152 155 SMSC_FDC37M81X_PMGT); 153 156 154 - printk(KERN_INFO "%s: keyboard\n", fname); 157 + pr_info("%s: keyboard\n", fname); 155 158 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); 156 159 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, 157 160 SMSC_FDC37M81X_ACTIVE);
+1 -1
arch/mips/txx9/jmr3927/prom.c
··· 45 45 { 46 46 /* CCFG */ 47 47 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) 48 - printk(KERN_ERR "TX3927 TLB off\n"); 48 + pr_err("TX3927 TLB off\n"); 49 49 50 50 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); 51 51 txx9_sio_putchar_init(TX3927_SIO_REG(1));
+5 -6
arch/mips/txx9/jmr3927/setup.c
··· 150 150 151 151 jmr3927_led_set(0); 152 152 153 - printk(KERN_INFO 154 - "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", 155 - jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, 156 - jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, 157 - jmr3927_dipsw1(), jmr3927_dipsw2(), 158 - jmr3927_dipsw3(), jmr3927_dipsw4()); 153 + pr_info("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", 154 + jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, 155 + jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, 156 + jmr3927_dipsw1(), jmr3927_dipsw2(), 157 + jmr3927_dipsw3(), jmr3927_dipsw4()); 159 158 } 160 159 161 160 /* This trick makes rtc-ds1742 driver usable as is. */
+7 -7
arch/mips/txx9/rbtx4938/setup.c
··· 123 123 124 124 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ 125 125 if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) { 126 - printk(KERN_ERR "seeprom: read error.\n"); 126 + pr_err("seeprom: read error.\n"); 127 127 return -ENODEV; 128 128 } else { 129 129 if (strcmp(dat, "MAC") != 0) 130 - printk(KERN_WARNING "seeprom: bad signature.\n"); 130 + pr_warn("seeprom: bad signature.\n"); 131 131 for (i = 0, sum = 0; i < sizeof(dat); i++) 132 132 sum += dat[i]; 133 133 if (sum) 134 - printk(KERN_WARNING "seeprom: bad checksum.\n"); 134 + pr_warn("seeprom: bad checksum.\n"); 135 135 } 136 136 tx4938_ethaddr_init(&dat[4], &dat[4 + 6]); 137 137 #endif /* CONFIG_PCI */ ··· 214 214 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; 215 215 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 216 216 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource)) 217 - printk(KERN_ERR "request resource for fpga failed\n"); 217 + pr_err("request resource for fpga failed\n"); 218 218 219 219 _machine_restart = rbtx4938_machine_restart; 220 220 221 221 writeb(0xff, rbtx4938_led_addr); 222 - printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", 223 - readb(rbtx4938_fpga_rev_addr), 224 - readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); 222 + pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", 223 + readb(rbtx4938_fpga_rev_addr), 224 + readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); 225 225 } 226 226 227 227 static void __init rbtx4938_ne_init(void)