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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
[ARM] 4394/1: ARMv7: Add the TLB range operations
We are currently using the ARMv6 operations but need to duplicate some
of the code because of the introduction of the new CPU barrier
instructions in ARMv7.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Catalin Marinas
and committed by
Russell King
2ccdd1e7
919a8429
+107
-2
+4
-1
arch/arm/mm/Kconfig
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-1
arch/arm/mm/Kconfig
···
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select CPU_CP15_MMU
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select CPU_HAS_ASID
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select CPU_COPY_V6 if MMU
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-
select CPU_TLB_V6 if MMU
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select CPU_TLB_V7 if MMU
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# Figure out what processor architecture version we should be using.
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# This defines the compiler instruction set which depends on the machine type.
···
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instruction cache entry.
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config CPU_TLB_V6
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bool
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config CPU_TLB_V7
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bool
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endif
+1
arch/arm/mm/Makefile
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arch/arm/mm/Makefile
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-1
arch/arm/mm/proc-v7.S
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-1
arch/arm/mm/proc-v7.S
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arch/arm/mm/tlb-v7.S
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arch/arm/mm/tlb-v7.S
···
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/*
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* linux/arch/arm/mm/tlb-v7.S
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*
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* Copyright (C) 1997-2002 Russell King
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* Modified for ARMv7 by Catalin Marinas
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM architecture version 6 TLB handling functions.
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* These assume a split I/D TLB.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* v7wbi_flush_user_tlb_range(start, end, vma)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_struct describing address range
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*
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* It is assumed that:
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* - the "Invalidate single entry" instruction will invalidate
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* both the I and the D TLBs on Harvard-style TLBs
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*/
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ENTRY(v7wbi_flush_user_tlb_range)
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vma_vm_mm r3, r2 @ get vma->vm_mm
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mmid r3, r3 @ get vm_mm->context.id
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dsb
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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asid r3, r3 @ mask ASID
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orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
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mov r1, r1, lsl #PAGE_SHIFT
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vma_vm_flags r2, r2 @ get vma->vm_flags
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1:
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mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
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tst r2, #VM_EXEC @ Executable area ?
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mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
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dsb
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mov pc, lr
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/*
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* v7wbi_flush_kern_tlb_range(start,end)
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*
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* Invalidate a range of kernel TLB entries
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*/
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ENTRY(v7wbi_flush_kern_tlb_range)
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dsb
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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mov r0, r0, lsl #PAGE_SHIFT
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mov r1, r1, lsl #PAGE_SHIFT
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1:
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mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
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mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mov r2, #0
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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dsb
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isb
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mov pc, lr
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.section ".text.init", #alloc, #execinstr
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.type v7wbi_tlb_fns, #object
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ENTRY(v7wbi_tlb_fns)
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.long v7wbi_flush_user_tlb_range
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.long v7wbi_flush_kern_tlb_range
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.long v6wbi_tlb_flags
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.size v7wbi_tlb_fns, . - v7wbi_tlb_fns
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include/asm-arm/tlbflush.h
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include/asm-arm/tlbflush.h
···
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# define v6wbi_always_flags (-1UL)
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#endif
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#ifdef CONFIG_CPU_TLB_V7
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# define v7wbi_possible_flags v6wbi_tlb_flags
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# define v7wbi_always_flags v6wbi_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v7wbi
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# endif
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#else
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# define v7wbi_possible_flags 0
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# define v7wbi_always_flags (-1UL)
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#endif
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#ifndef _TLB
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#error Unknown TLB model
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#endif