Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

[media] dvb-frontends/stv0367: add defaults for use w/DD-branded devices

Digital Devices uses defaults tables in their stv0367dd demod driver
variant which differ in a few registers, at least enough that no stable
operation can be provided with the tables already present in the driver
(init succeeds and DVB reception works but at least when the driver is
reloaded using rmmod/modprobe, the demod goes into a crashed state in a
way it doesn't react on any I2C command anymore, while even more
side-effects may occur), so there's a good reason to better have another
set of defaults.

Defaults originating from the stv0367dd driver. Permission to reuse them
was formally granted by Ralph Metzler <rjkm@metzlerbros.de>.

Signed-off-by: Daniel Scheller <d.scheller@gmx.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>

authored by

Daniel Scheller and committed by
Mauro Carvalho Chehab
2cafa6b2 8b39f076

+609 -1
+609 -1
drivers/media/dvb-frontends/stv0367_defs.h
··· 25 25 #include "stv0367_regs.h" 26 26 27 27 #define STV0367_DEFTAB_GENERIC 0 28 - #define STV0367_DEFTAB_MAX 1 28 + #define STV0367_DEFTAB_DDB 1 29 + #define STV0367_DEFTAB_MAX 2 29 30 30 31 #define STV0367_TAB_TER 0 31 32 #define STV0367_TAB_CAB 1 ··· 681 680 {0x0000, 0x00}, 682 681 }; 683 682 683 + /************** 684 + * 685 + * Defaults / Tables for Digital Devices C/T Cine/Flex devices 686 + * 687 + **************/ 688 + 689 + static const struct st_register def0367dd_ofdm[] = { 690 + {R367TER_AGC2MAX, 0xff}, 691 + {R367TER_AGC2MIN, 0x00}, 692 + {R367TER_AGC1MAX, 0xff}, 693 + {R367TER_AGC1MIN, 0x00}, 694 + {R367TER_AGCR, 0xbc}, 695 + {R367TER_AGC2TH, 0x00}, 696 + {R367TER_AGCCTRL1, 0x85}, 697 + {R367TER_AGCCTRL2, 0x1f}, 698 + {R367TER_AGC1VAL1, 0x00}, 699 + {R367TER_AGC1VAL2, 0x00}, 700 + {R367TER_AGC2VAL1, 0x6f}, 701 + {R367TER_AGC2VAL2, 0x05}, 702 + {R367TER_AGC2PGA, 0x00}, 703 + {R367TER_OVF_RATE1, 0x00}, 704 + {R367TER_OVF_RATE2, 0x00}, 705 + {R367TER_GAIN_SRC1, 0x2b}, 706 + {R367TER_GAIN_SRC2, 0x04}, 707 + {R367TER_INC_DEROT1, 0x55}, 708 + {R367TER_INC_DEROT2, 0x55}, 709 + {R367TER_PPM_CPAMP_DIR, 0x2c}, 710 + {R367TER_PPM_CPAMP_INV, 0x00}, 711 + {R367TER_FREESTFE_1, 0x00}, 712 + {R367TER_FREESTFE_2, 0x1c}, 713 + {R367TER_DCOFFSET, 0x00}, 714 + {R367TER_EN_PROCESS, 0x05}, 715 + {R367TER_SDI_SMOOTHER, 0x80}, 716 + {R367TER_FE_LOOP_OPEN, 0x1c}, 717 + {R367TER_FREQOFF1, 0x00}, 718 + {R367TER_FREQOFF2, 0x00}, 719 + {R367TER_FREQOFF3, 0x00}, 720 + {R367TER_TIMOFF1, 0x00}, 721 + {R367TER_TIMOFF2, 0x00}, 722 + {R367TER_EPQ, 0x02}, 723 + {R367TER_EPQAUTO, 0x01}, 724 + {R367TER_SYR_UPDATE, 0xf5}, 725 + {R367TER_CHPFREE, 0x00}, 726 + {R367TER_PPM_STATE_MAC, 0x23}, 727 + {R367TER_INR_THRESHOLD, 0xff}, 728 + {R367TER_EPQ_TPS_ID_CELL, 0xf9}, 729 + {R367TER_EPQ_CFG, 0x00}, 730 + {R367TER_EPQ_STATUS, 0x01}, 731 + {R367TER_AUTORELOCK, 0x81}, 732 + {R367TER_BER_THR_VMSB, 0x00}, 733 + {R367TER_BER_THR_MSB, 0x00}, 734 + {R367TER_BER_THR_LSB, 0x00}, 735 + {R367TER_CCD, 0x83}, 736 + {R367TER_SPECTR_CFG, 0x00}, 737 + {R367TER_CHC_DUMMY, 0x18}, 738 + {R367TER_INC_CTL, 0x88}, 739 + {R367TER_INCTHRES_COR1, 0xb4}, 740 + {R367TER_INCTHRES_COR2, 0x96}, 741 + {R367TER_INCTHRES_DET1, 0x0e}, 742 + {R367TER_INCTHRES_DET2, 0x11}, 743 + {R367TER_IIR_CELLNB, 0x8d}, 744 + {R367TER_IIRCX_COEFF1_MSB, 0x00}, 745 + {R367TER_IIRCX_COEFF1_LSB, 0x00}, 746 + {R367TER_IIRCX_COEFF2_MSB, 0x09}, 747 + {R367TER_IIRCX_COEFF2_LSB, 0x18}, 748 + {R367TER_IIRCX_COEFF3_MSB, 0x14}, 749 + {R367TER_IIRCX_COEFF3_LSB, 0x9c}, 750 + {R367TER_IIRCX_COEFF4_MSB, 0x00}, 751 + {R367TER_IIRCX_COEFF4_LSB, 0x00}, 752 + {R367TER_IIRCX_COEFF5_MSB, 0x36}, 753 + {R367TER_IIRCX_COEFF5_LSB, 0x42}, 754 + {R367TER_FEPATH_CFG, 0x00}, 755 + {R367TER_PMC1_FUNC, 0x65}, 756 + {R367TER_PMC1_FOR, 0x00}, 757 + {R367TER_PMC2_FUNC, 0x00}, 758 + {R367TER_STATUS_ERR_DA, 0xe0}, 759 + {R367TER_DIG_AGC_R, 0xfe}, 760 + {R367TER_COMAGC_TARMSB, 0x0b}, 761 + {R367TER_COM_AGC_TAR_ENMODE, 0x41}, 762 + {R367TER_COM_AGC_CFG, 0x3e}, 763 + {R367TER_COM_AGC_GAIN1, 0x39}, 764 + {R367TER_AUT_AGC_TARGETMSB, 0x0b}, 765 + {R367TER_LOCK_DET_MSB, 0x01}, 766 + {R367TER_AGCTAR_LOCK_LSBS, 0x40}, 767 + {R367TER_AUT_GAIN_EN, 0xf4}, 768 + {R367TER_AUT_CFG, 0xf0}, 769 + {R367TER_LOCKN, 0x23}, 770 + {R367TER_INT_X_3, 0x00}, 771 + {R367TER_INT_X_2, 0x03}, 772 + {R367TER_INT_X_1, 0x8d}, 773 + {R367TER_INT_X_0, 0xa0}, 774 + {R367TER_MIN_ERRX_MSB, 0x00}, 775 + {R367TER_COR_CTL, 0x00}, 776 + {R367TER_COR_STAT, 0xf6}, 777 + {R367TER_COR_INTEN, 0x00}, 778 + {R367TER_COR_INTSTAT, 0x3f}, 779 + {R367TER_COR_MODEGUARD, 0x03}, 780 + {R367TER_AGC_CTL, 0x08}, 781 + {R367TER_AGC_MANUAL1, 0x00}, 782 + {R367TER_AGC_MANUAL2, 0x00}, 783 + {R367TER_AGC_TARG, 0x16}, 784 + {R367TER_AGC_GAIN1, 0x53}, 785 + {R367TER_AGC_GAIN2, 0x1d}, 786 + {R367TER_RESERVED_1, 0x00}, 787 + {R367TER_RESERVED_2, 0x00}, 788 + {R367TER_RESERVED_3, 0x00}, 789 + {R367TER_CAS_CTL, 0x44}, 790 + {R367TER_CAS_FREQ, 0xb3}, 791 + {R367TER_CAS_DAGCGAIN, 0x12}, 792 + {R367TER_SYR_CTL, 0x04}, 793 + {R367TER_SYR_STAT, 0x10}, 794 + {R367TER_SYR_NCO1, 0x00}, 795 + {R367TER_SYR_NCO2, 0x00}, 796 + {R367TER_SYR_OFFSET1, 0x00}, 797 + {R367TER_SYR_OFFSET2, 0x00}, 798 + {R367TER_FFT_CTL, 0x00}, 799 + {R367TER_SCR_CTL, 0x70}, 800 + {R367TER_PPM_CTL1, 0xf8}, 801 + {R367TER_TRL_CTL, 0xac}, 802 + {R367TER_TRL_NOMRATE1, 0x1e}, 803 + {R367TER_TRL_NOMRATE2, 0x58}, 804 + {R367TER_TRL_TIME1, 0x1d}, 805 + {R367TER_TRL_TIME2, 0xfc}, 806 + {R367TER_CRL_CTL, 0x24}, 807 + {R367TER_CRL_FREQ1, 0xad}, 808 + {R367TER_CRL_FREQ2, 0x9d}, 809 + {R367TER_CRL_FREQ3, 0xff}, 810 + {R367TER_CHC_CTL, 0x01}, 811 + {R367TER_CHC_SNR, 0xf0}, 812 + {R367TER_BDI_CTL, 0x00}, 813 + {R367TER_DMP_CTL, 0x00}, 814 + {R367TER_TPS_RCVD1, 0x30}, 815 + {R367TER_TPS_RCVD2, 0x02}, 816 + {R367TER_TPS_RCVD3, 0x01}, 817 + {R367TER_TPS_RCVD4, 0x00}, 818 + {R367TER_TPS_ID_CELL1, 0x00}, 819 + {R367TER_TPS_ID_CELL2, 0x00}, 820 + {R367TER_TPS_RCVD5_SET1, 0x02}, 821 + {R367TER_TPS_SET2, 0x02}, 822 + {R367TER_TPS_SET3, 0x01}, 823 + {R367TER_TPS_CTL, 0x00}, 824 + {R367TER_CTL_FFTOSNUM, 0x34}, 825 + {R367TER_TESTSELECT, 0x09}, 826 + {R367TER_MSC_REV, 0x0a}, 827 + {R367TER_PIR_CTL, 0x00}, 828 + {R367TER_SNR_CARRIER1, 0xa1}, 829 + {R367TER_SNR_CARRIER2, 0x9a}, 830 + {R367TER_PPM_CPAMP, 0x2c}, 831 + {R367TER_TSM_AP0, 0x00}, 832 + {R367TER_TSM_AP1, 0x00}, 833 + {R367TER_TSM_AP2, 0x00}, 834 + {R367TER_TSM_AP3, 0x00}, 835 + {R367TER_TSM_AP4, 0x00}, 836 + {R367TER_TSM_AP5, 0x00}, 837 + {R367TER_TSM_AP6, 0x00}, 838 + {R367TER_TSM_AP7, 0x00}, 839 + {R367TER_CONSTMODE, 0x01}, 840 + {R367TER_CONSTCARR1, 0x00}, 841 + {R367TER_CONSTCARR2, 0x00}, 842 + {R367TER_ICONSTEL, 0x0a}, 843 + {R367TER_QCONSTEL, 0x15}, 844 + {R367TER_TSTBISTRES0, 0x00}, 845 + {R367TER_TSTBISTRES1, 0x00}, 846 + {R367TER_TSTBISTRES2, 0x28}, 847 + {R367TER_TSTBISTRES3, 0x00}, 848 + {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00}, 849 + {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00}, 850 + {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00}, 851 + {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00}, 852 + {R367TER_SYR_FLAG, 0x00}, 853 + {R367TER_CRL_TARGET1, 0x00}, 854 + {R367TER_CRL_TARGET2, 0x00}, 855 + {R367TER_CRL_TARGET3, 0x00}, 856 + {R367TER_CRL_TARGET4, 0x00}, 857 + {R367TER_CRL_FLAG, 0x00}, 858 + {R367TER_TRL_TARGET1, 0x00}, 859 + {R367TER_TRL_TARGET2, 0x00}, 860 + {R367TER_TRL_CHC, 0x00}, 861 + {R367TER_CHC_SNR_TARG, 0x00}, 862 + {R367TER_TOP_TRACK, 0x00}, 863 + {R367TER_TRACKER_FREE1, 0x00}, 864 + {R367TER_ERROR_CRL1, 0x00}, 865 + {R367TER_ERROR_CRL2, 0x00}, 866 + {R367TER_ERROR_CRL3, 0x00}, 867 + {R367TER_ERROR_CRL4, 0x00}, 868 + {R367TER_DEC_NCO1, 0x2c}, 869 + {R367TER_DEC_NCO2, 0x0f}, 870 + {R367TER_DEC_NCO3, 0x20}, 871 + {R367TER_SNR, 0xf1}, 872 + {R367TER_SYR_FFTADJ1, 0x00}, 873 + {R367TER_SYR_FFTADJ2, 0x00}, 874 + {R367TER_SYR_CHCADJ1, 0x00}, 875 + {R367TER_SYR_CHCADJ2, 0x00}, 876 + {R367TER_SYR_OFF, 0x00}, 877 + {R367TER_PPM_OFFSET1, 0x00}, 878 + {R367TER_PPM_OFFSET2, 0x03}, 879 + {R367TER_TRACKER_FREE2, 0x00}, 880 + {R367TER_DEBG_LT10, 0x00}, 881 + {R367TER_DEBG_LT11, 0x00}, 882 + {R367TER_DEBG_LT12, 0x00}, 883 + {R367TER_DEBG_LT13, 0x00}, 884 + {R367TER_DEBG_LT14, 0x00}, 885 + {R367TER_DEBG_LT15, 0x00}, 886 + {R367TER_DEBG_LT16, 0x00}, 887 + {R367TER_DEBG_LT17, 0x00}, 888 + {R367TER_DEBG_LT18, 0x00}, 889 + {R367TER_DEBG_LT19, 0x00}, 890 + {R367TER_DEBG_LT1A, 0x00}, 891 + {R367TER_DEBG_LT1B, 0x00}, 892 + {R367TER_DEBG_LT1C, 0x00}, 893 + {R367TER_DEBG_LT1D, 0x00}, 894 + {R367TER_DEBG_LT1E, 0x00}, 895 + {R367TER_DEBG_LT1F, 0x00}, 896 + {R367TER_RCCFGH, 0x00}, 897 + {R367TER_RCCFGM, 0x00}, 898 + {R367TER_RCCFGL, 0x00}, 899 + {R367TER_RCINSDELH, 0x00}, 900 + {R367TER_RCINSDELM, 0x00}, 901 + {R367TER_RCINSDELL, 0x00}, 902 + {R367TER_RCSTATUS, 0x00}, 903 + {R367TER_RCSPEED, 0x6f}, 904 + {R367TER_RCDEBUGM, 0xe7}, 905 + {R367TER_RCDEBUGL, 0x9b}, 906 + {R367TER_RCOBSCFG, 0x00}, 907 + {R367TER_RCOBSM, 0x00}, 908 + {R367TER_RCOBSL, 0x00}, 909 + {R367TER_RCFECSPY, 0x00}, 910 + {R367TER_RCFSPYCFG, 0x00}, 911 + {R367TER_RCFSPYDATA, 0x00}, 912 + {R367TER_RCFSPYOUT, 0x00}, 913 + {R367TER_RCFSTATUS, 0x00}, 914 + {R367TER_RCFGOODPACK, 0x00}, 915 + {R367TER_RCFPACKCNT, 0x00}, 916 + {R367TER_RCFSPYMISC, 0x00}, 917 + {R367TER_RCFBERCPT4, 0x00}, 918 + {R367TER_RCFBERCPT3, 0x00}, 919 + {R367TER_RCFBERCPT2, 0x00}, 920 + {R367TER_RCFBERCPT1, 0x00}, 921 + {R367TER_RCFBERCPT0, 0x00}, 922 + {R367TER_RCFBERERR2, 0x00}, 923 + {R367TER_RCFBERERR1, 0x00}, 924 + {R367TER_RCFBERERR0, 0x00}, 925 + {R367TER_RCFSTATESM, 0x00}, 926 + {R367TER_RCFSTATESL, 0x00}, 927 + {R367TER_RCFSPYBER, 0x00}, 928 + {R367TER_RCFSPYDISTM, 0x00}, 929 + {R367TER_RCFSPYDISTL, 0x00}, 930 + {R367TER_RCFSPYOBS7, 0x00}, 931 + {R367TER_RCFSPYOBS6, 0x00}, 932 + {R367TER_RCFSPYOBS5, 0x00}, 933 + {R367TER_RCFSPYOBS4, 0x00}, 934 + {R367TER_RCFSPYOBS3, 0x00}, 935 + {R367TER_RCFSPYOBS2, 0x00}, 936 + {R367TER_RCFSPYOBS1, 0x00}, 937 + {R367TER_RCFSPYOBS0, 0x00}, 938 + {R367TER_FECM, 0x01}, 939 + {R367TER_VTH12, 0xff}, 940 + {R367TER_VTH23, 0xa1}, 941 + {R367TER_VTH34, 0x64}, 942 + {R367TER_VTH56, 0x40}, 943 + {R367TER_VTH67, 0x00}, 944 + {R367TER_VTH78, 0x2c}, 945 + {R367TER_VITCURPUN, 0x12}, 946 + {R367TER_VERROR, 0x01}, 947 + {R367TER_PRVIT, 0x3f}, 948 + {R367TER_VAVSRVIT, 0x00}, 949 + {R367TER_VSTATUSVIT, 0xbd}, 950 + {R367TER_VTHINUSE, 0xa1}, 951 + {R367TER_KDIV12, 0x20}, 952 + {R367TER_KDIV23, 0x40}, 953 + {R367TER_KDIV34, 0x20}, 954 + {R367TER_KDIV56, 0x30}, 955 + {R367TER_KDIV67, 0x00}, 956 + {R367TER_KDIV78, 0x30}, 957 + {R367TER_SIGPOWER, 0x54}, 958 + {R367TER_DEMAPVIT, 0x40}, 959 + {R367TER_VITSCALE, 0x00}, 960 + {R367TER_FFEC1PRG, 0x00}, 961 + {R367TER_FVITCURPUN, 0x12}, 962 + {R367TER_FVERROR, 0x01}, 963 + {R367TER_FVSTATUSVIT, 0xbd}, 964 + {R367TER_DEBUG_LT1, 0x00}, 965 + {R367TER_DEBUG_LT2, 0x00}, 966 + {R367TER_DEBUG_LT3, 0x00}, 967 + {R367TER_TSTSFMET, 0x00}, 968 + {R367TER_SELOUT, 0x00}, 969 + {R367TER_TSYNC, 0x00}, 970 + {R367TER_TSTERR, 0x00}, 971 + {R367TER_TSFSYNC, 0x00}, 972 + {R367TER_TSTSFERR, 0x00}, 973 + {R367TER_TSTTSSF1, 0x01}, 974 + {R367TER_TSTTSSF2, 0x1f}, 975 + {R367TER_TSTTSSF3, 0x00}, 976 + {R367TER_TSTTS1, 0x00}, 977 + {R367TER_TSTTS2, 0x1f}, 978 + {R367TER_TSTTS3, 0x01}, 979 + {R367TER_TSTTS4, 0x00}, 980 + {R367TER_TSTTSRC, 0x00}, 981 + {R367TER_TSTTSRS, 0x00}, 982 + {R367TER_TSSTATEM, 0xb0}, 983 + {R367TER_TSSTATEL, 0x40}, 984 + {R367TER_TSCFGH, 0x80}, 985 + {R367TER_TSCFGM, 0x00}, 986 + {R367TER_TSCFGL, 0x20}, 987 + {R367TER_TSSYNC, 0x00}, 988 + {R367TER_TSINSDELH, 0x00}, 989 + {R367TER_TSINSDELM, 0x00}, 990 + {R367TER_TSINSDELL, 0x00}, 991 + {R367TER_TSDIVN, 0x03}, 992 + {R367TER_TSDIVPM, 0x00}, 993 + {R367TER_TSDIVPL, 0x00}, 994 + {R367TER_TSDIVQM, 0x00}, 995 + {R367TER_TSDIVQL, 0x00}, 996 + {R367TER_TSDILSTKM, 0x00}, 997 + {R367TER_TSDILSTKL, 0x00}, 998 + {R367TER_TSSPEED, 0x6f}, 999 + {R367TER_TSSTATUS, 0x81}, 1000 + {R367TER_TSSTATUS2, 0x6a}, 1001 + {R367TER_TSBITRATEM, 0x0f}, 1002 + {R367TER_TSBITRATEL, 0xc6}, 1003 + {R367TER_TSPACKLENM, 0x00}, 1004 + {R367TER_TSPACKLENL, 0xfc}, 1005 + {R367TER_TSBLOCLENM, 0x0a}, 1006 + {R367TER_TSBLOCLENL, 0x80}, 1007 + {R367TER_TSDLYH, 0x90}, 1008 + {R367TER_TSDLYM, 0x68}, 1009 + {R367TER_TSDLYL, 0x01}, 1010 + {R367TER_TSNPDAV, 0x00}, 1011 + {R367TER_TSBUFSTATH, 0x00}, 1012 + {R367TER_TSBUFSTATM, 0x00}, 1013 + {R367TER_TSBUFSTATL, 0x00}, 1014 + {R367TER_TSDEBUGM, 0xcf}, 1015 + {R367TER_TSDEBUGL, 0x1e}, 1016 + {R367TER_TSDLYSETH, 0x00}, 1017 + {R367TER_TSDLYSETM, 0x68}, 1018 + {R367TER_TSDLYSETL, 0x00}, 1019 + {R367TER_TSOBSCFG, 0x00}, 1020 + {R367TER_TSOBSM, 0x47}, 1021 + {R367TER_TSOBSL, 0x1f}, 1022 + {R367TER_ERRCTRL1, 0x95}, 1023 + {R367TER_ERRCNT1H, 0x80}, 1024 + {R367TER_ERRCNT1M, 0x00}, 1025 + {R367TER_ERRCNT1L, 0x00}, 1026 + {R367TER_ERRCTRL2, 0x95}, 1027 + {R367TER_ERRCNT2H, 0x00}, 1028 + {R367TER_ERRCNT2M, 0x00}, 1029 + {R367TER_ERRCNT2L, 0x00}, 1030 + {R367TER_FECSPY, 0x88}, 1031 + {R367TER_FSPYCFG, 0x2c}, 1032 + {R367TER_FSPYDATA, 0x3a}, 1033 + {R367TER_FSPYOUT, 0x06}, 1034 + {R367TER_FSTATUS, 0x61}, 1035 + {R367TER_FGOODPACK, 0xff}, 1036 + {R367TER_FPACKCNT, 0xff}, 1037 + {R367TER_FSPYMISC, 0x66}, 1038 + {R367TER_FBERCPT4, 0x00}, 1039 + {R367TER_FBERCPT3, 0x00}, 1040 + {R367TER_FBERCPT2, 0x36}, 1041 + {R367TER_FBERCPT1, 0x36}, 1042 + {R367TER_FBERCPT0, 0x14}, 1043 + {R367TER_FBERERR2, 0x00}, 1044 + {R367TER_FBERERR1, 0x03}, 1045 + {R367TER_FBERERR0, 0x28}, 1046 + {R367TER_FSTATESM, 0x00}, 1047 + {R367TER_FSTATESL, 0x02}, 1048 + {R367TER_FSPYBER, 0x00}, 1049 + {R367TER_FSPYDISTM, 0x01}, 1050 + {R367TER_FSPYDISTL, 0x9f}, 1051 + {R367TER_FSPYOBS7, 0xc9}, 1052 + {R367TER_FSPYOBS6, 0x99}, 1053 + {R367TER_FSPYOBS5, 0x08}, 1054 + {R367TER_FSPYOBS4, 0xec}, 1055 + {R367TER_FSPYOBS3, 0x01}, 1056 + {R367TER_FSPYOBS2, 0x0f}, 1057 + {R367TER_FSPYOBS1, 0xf5}, 1058 + {R367TER_FSPYOBS0, 0x08}, 1059 + {R367TER_SFDEMAP, 0x40}, 1060 + {R367TER_SFERROR, 0x00}, 1061 + {R367TER_SFAVSR, 0x30}, 1062 + {R367TER_SFECSTATUS, 0xcc}, 1063 + {R367TER_SFKDIV12, 0x20}, 1064 + {R367TER_SFKDIV23, 0x40}, 1065 + {R367TER_SFKDIV34, 0x20}, 1066 + {R367TER_SFKDIV56, 0x20}, 1067 + {R367TER_SFKDIV67, 0x00}, 1068 + {R367TER_SFKDIV78, 0x20}, 1069 + {R367TER_SFDILSTKM, 0x00}, 1070 + {R367TER_SFDILSTKL, 0x00}, 1071 + {R367TER_SFSTATUS, 0xb5}, 1072 + {R367TER_SFDLYH, 0x90}, 1073 + {R367TER_SFDLYM, 0x60}, 1074 + {R367TER_SFDLYL, 0x01}, 1075 + {R367TER_SFDLYSETH, 0xc0}, 1076 + {R367TER_SFDLYSETM, 0x60}, 1077 + {R367TER_SFDLYSETL, 0x00}, 1078 + {R367TER_SFOBSCFG, 0x00}, 1079 + {R367TER_SFOBSM, 0x47}, 1080 + {R367TER_SFOBSL, 0x05}, 1081 + {R367TER_SFECINFO, 0x40}, 1082 + {R367TER_SFERRCTRL, 0x74}, 1083 + {R367TER_SFERRCNTH, 0x80}, 1084 + {R367TER_SFERRCNTM, 0x00}, 1085 + {R367TER_SFERRCNTL, 0x00}, 1086 + {R367TER_SYMBRATEM, 0x2f}, 1087 + {R367TER_SYMBRATEL, 0x50}, 1088 + {R367TER_SYMBSTATUS, 0x7f}, 1089 + {R367TER_SYMBCFG, 0x00}, 1090 + {R367TER_SYMBFIFOM, 0xf4}, 1091 + {R367TER_SYMBFIFOL, 0x0d}, 1092 + {R367TER_SYMBOFFSM, 0xf0}, 1093 + {R367TER_SYMBOFFSL, 0x2d}, 1094 + {0x0000, 0x00} /* EOT */ 1095 + }; 1096 + 1097 + static const struct st_register def0367dd_qam[] = { 1098 + {R367CAB_CTRL_1, 0x06}, /* Orginal 0x04 */ 1099 + {R367CAB_CTRL_2, 0x03}, 1100 + {R367CAB_IT_STATUS1, 0x2b}, 1101 + {R367CAB_IT_STATUS2, 0x08}, 1102 + {R367CAB_IT_EN1, 0x00}, 1103 + {R367CAB_IT_EN2, 0x00}, 1104 + {R367CAB_CTRL_STATUS, 0x04}, 1105 + {R367CAB_TEST_CTL, 0x00}, 1106 + {R367CAB_AGC_CTL, 0x73}, 1107 + {R367CAB_AGC_IF_CFG, 0x50}, 1108 + {R367CAB_AGC_RF_CFG, 0x02}, /* RF Freeze */ 1109 + {R367CAB_AGC_PWM_CFG, 0x03}, 1110 + {R367CAB_AGC_PWR_REF_L, 0x5a}, 1111 + {R367CAB_AGC_PWR_REF_H, 0x00}, 1112 + {R367CAB_AGC_RF_TH_L, 0xff}, 1113 + {R367CAB_AGC_RF_TH_H, 0x07}, 1114 + {R367CAB_AGC_IF_LTH_L, 0x00}, 1115 + {R367CAB_AGC_IF_LTH_H, 0x08}, 1116 + {R367CAB_AGC_IF_HTH_L, 0xff}, 1117 + {R367CAB_AGC_IF_HTH_H, 0x07}, 1118 + {R367CAB_AGC_PWR_RD_L, 0xa0}, 1119 + {R367CAB_AGC_PWR_RD_M, 0xe9}, 1120 + {R367CAB_AGC_PWR_RD_H, 0x03}, 1121 + {R367CAB_AGC_PWM_IFCMD_L, 0xe4}, 1122 + {R367CAB_AGC_PWM_IFCMD_H, 0x00}, 1123 + {R367CAB_AGC_PWM_RFCMD_L, 0xff}, 1124 + {R367CAB_AGC_PWM_RFCMD_H, 0x07}, 1125 + {R367CAB_IQDEM_CFG, 0x01}, 1126 + {R367CAB_MIX_NCO_LL, 0x22}, 1127 + {R367CAB_MIX_NCO_HL, 0x96}, 1128 + {R367CAB_MIX_NCO_HH, 0x55}, 1129 + {R367CAB_SRC_NCO_LL, 0xff}, 1130 + {R367CAB_SRC_NCO_LH, 0x0c}, 1131 + {R367CAB_SRC_NCO_HL, 0xf5}, 1132 + {R367CAB_SRC_NCO_HH, 0x20}, 1133 + {R367CAB_IQDEM_GAIN_SRC_L, 0x06}, 1134 + {R367CAB_IQDEM_GAIN_SRC_H, 0x01}, 1135 + {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe}, 1136 + {R367CAB_IQDEM_DCRM_CFG_LH, 0xff}, 1137 + {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f}, 1138 + {R367CAB_IQDEM_DCRM_CFG_HH, 0x00}, 1139 + {R367CAB_IQDEM_ADJ_COEFF0, 0x34}, 1140 + {R367CAB_IQDEM_ADJ_COEFF1, 0xae}, 1141 + {R367CAB_IQDEM_ADJ_COEFF2, 0x46}, 1142 + {R367CAB_IQDEM_ADJ_COEFF3, 0x77}, 1143 + {R367CAB_IQDEM_ADJ_COEFF4, 0x96}, 1144 + {R367CAB_IQDEM_ADJ_COEFF5, 0x69}, 1145 + {R367CAB_IQDEM_ADJ_COEFF6, 0xc7}, 1146 + {R367CAB_IQDEM_ADJ_COEFF7, 0x01}, 1147 + {R367CAB_IQDEM_ADJ_EN, 0x04}, 1148 + {R367CAB_IQDEM_ADJ_AGC_REF, 0x94}, 1149 + {R367CAB_ALLPASSFILT1, 0xc9}, 1150 + {R367CAB_ALLPASSFILT2, 0x2d}, 1151 + {R367CAB_ALLPASSFILT3, 0xa3}, 1152 + {R367CAB_ALLPASSFILT4, 0xfb}, 1153 + {R367CAB_ALLPASSFILT5, 0xf6}, 1154 + {R367CAB_ALLPASSFILT6, 0x45}, 1155 + {R367CAB_ALLPASSFILT7, 0x6f}, 1156 + {R367CAB_ALLPASSFILT8, 0x7e}, 1157 + {R367CAB_ALLPASSFILT9, 0x05}, 1158 + {R367CAB_ALLPASSFILT10, 0x0a}, 1159 + {R367CAB_ALLPASSFILT11, 0x51}, 1160 + {R367CAB_TRL_AGC_CFG, 0x20}, 1161 + {R367CAB_TRL_LPF_CFG, 0x28}, 1162 + {R367CAB_TRL_LPF_ACQ_GAIN, 0x44}, 1163 + {R367CAB_TRL_LPF_TRK_GAIN, 0x22}, 1164 + {R367CAB_TRL_LPF_OUT_GAIN, 0x03}, 1165 + {R367CAB_TRL_LOCKDET_LTH, 0x04}, 1166 + {R367CAB_TRL_LOCKDET_HTH, 0x11}, 1167 + {R367CAB_TRL_LOCKDET_TRGVAL, 0x20}, 1168 + {R367CAB_IQ_QAM, 0x01}, 1169 + {R367CAB_FSM_STATE, 0xa0}, 1170 + {R367CAB_FSM_CTL, 0x08}, 1171 + {R367CAB_FSM_STS, 0x0c}, 1172 + {R367CAB_FSM_SNR0_HTH, 0x00}, 1173 + {R367CAB_FSM_SNR1_HTH, 0x00}, 1174 + {R367CAB_FSM_SNR2_HTH, 0x00}, 1175 + {R367CAB_FSM_SNR0_LTH, 0x00}, 1176 + {R367CAB_FSM_SNR1_LTH, 0x00}, 1177 + {R367CAB_FSM_EQA1_HTH, 0x00}, 1178 + {R367CAB_FSM_TEMPO, 0x32}, 1179 + {R367CAB_FSM_CONFIG, 0x03}, 1180 + {R367CAB_EQU_I_TESTTAP_L, 0x11}, 1181 + {R367CAB_EQU_I_TESTTAP_M, 0x00}, 1182 + {R367CAB_EQU_I_TESTTAP_H, 0x00}, 1183 + {R367CAB_EQU_TESTAP_CFG, 0x00}, 1184 + {R367CAB_EQU_Q_TESTTAP_L, 0xff}, 1185 + {R367CAB_EQU_Q_TESTTAP_M, 0x00}, 1186 + {R367CAB_EQU_Q_TESTTAP_H, 0x00}, 1187 + {R367CAB_EQU_TAP_CTRL, 0x00}, 1188 + {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11}, 1189 + {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05}, 1190 + {R367CAB_EQU_CTR_HIPOW_L, 0x00}, 1191 + {R367CAB_EQU_CTR_HIPOW_H, 0x00}, 1192 + {R367CAB_EQU_I_EQU_LO, 0xef}, 1193 + {R367CAB_EQU_I_EQU_HI, 0x00}, 1194 + {R367CAB_EQU_Q_EQU_LO, 0xee}, 1195 + {R367CAB_EQU_Q_EQU_HI, 0x00}, 1196 + {R367CAB_EQU_MAPPER, 0xc5}, 1197 + {R367CAB_EQU_SWEEP_RATE, 0x80}, 1198 + {R367CAB_EQU_SNR_LO, 0x64}, 1199 + {R367CAB_EQU_SNR_HI, 0x03}, 1200 + {R367CAB_EQU_GAMMA_LO, 0x00}, 1201 + {R367CAB_EQU_GAMMA_HI, 0x00}, 1202 + {R367CAB_EQU_ERR_GAIN, 0x36}, 1203 + {R367CAB_EQU_RADIUS, 0xaa}, 1204 + {R367CAB_EQU_FFE_MAINTAP, 0x00}, 1205 + {R367CAB_EQU_FFE_LEAKAGE, 0x63}, 1206 + {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf}, 1207 + {R367CAB_EQU_GAIN_WIDE, 0x88}, 1208 + {R367CAB_EQU_GAIN_NARROW, 0x41}, 1209 + {R367CAB_EQU_CTR_LPF_GAIN, 0xd1}, 1210 + {R367CAB_EQU_CRL_LPF_GAIN, 0xa7}, 1211 + {R367CAB_EQU_GLOBAL_GAIN, 0x06}, 1212 + {R367CAB_EQU_CRL_LD_SEN, 0x85}, 1213 + {R367CAB_EQU_CRL_LD_VAL, 0xe2}, 1214 + {R367CAB_EQU_CRL_TFR, 0x20}, 1215 + {R367CAB_EQU_CRL_BISTH_LO, 0x00}, 1216 + {R367CAB_EQU_CRL_BISTH_HI, 0x00}, 1217 + {R367CAB_EQU_SWEEP_RANGE_LO, 0x00}, 1218 + {R367CAB_EQU_SWEEP_RANGE_HI, 0x00}, 1219 + {R367CAB_EQU_CRL_LIMITER, 0x40}, 1220 + {R367CAB_EQU_MODULUS_MAP, 0x90}, 1221 + {R367CAB_EQU_PNT_GAIN, 0xa7}, 1222 + {R367CAB_FEC_AC_CTR_0, 0x16}, 1223 + {R367CAB_FEC_AC_CTR_1, 0x0b}, 1224 + {R367CAB_FEC_AC_CTR_2, 0x88}, 1225 + {R367CAB_FEC_AC_CTR_3, 0x02}, 1226 + {R367CAB_FEC_STATUS, 0x12}, 1227 + {R367CAB_RS_COUNTER_0, 0x7d}, 1228 + {R367CAB_RS_COUNTER_1, 0xd0}, 1229 + {R367CAB_RS_COUNTER_2, 0x19}, 1230 + {R367CAB_RS_COUNTER_3, 0x0b}, 1231 + {R367CAB_RS_COUNTER_4, 0xa3}, 1232 + {R367CAB_RS_COUNTER_5, 0x00}, 1233 + {R367CAB_BERT_0, 0x01}, 1234 + {R367CAB_BERT_1, 0x25}, 1235 + {R367CAB_BERT_2, 0x41}, 1236 + {R367CAB_BERT_3, 0x39}, 1237 + {R367CAB_OUTFORMAT_0, 0xc2}, 1238 + {R367CAB_OUTFORMAT_1, 0x22}, 1239 + {R367CAB_SMOOTHER_2, 0x28}, 1240 + {R367CAB_TSMF_CTRL_0, 0x01}, 1241 + {R367CAB_TSMF_CTRL_1, 0xc6}, 1242 + {R367CAB_TSMF_CTRL_3, 0x43}, 1243 + {R367CAB_TS_ON_ID_0, 0x00}, 1244 + {R367CAB_TS_ON_ID_1, 0x00}, 1245 + {R367CAB_TS_ON_ID_2, 0x00}, 1246 + {R367CAB_TS_ON_ID_3, 0x00}, 1247 + {R367CAB_RE_STATUS_0, 0x00}, 1248 + {R367CAB_RE_STATUS_1, 0x00}, 1249 + {R367CAB_RE_STATUS_2, 0x00}, 1250 + {R367CAB_RE_STATUS_3, 0x00}, 1251 + {R367CAB_TS_STATUS_0, 0x00}, 1252 + {R367CAB_TS_STATUS_1, 0x00}, 1253 + {R367CAB_TS_STATUS_2, 0xa0}, 1254 + {R367CAB_TS_STATUS_3, 0x00}, 1255 + {R367CAB_T_O_ID_0, 0x00}, 1256 + {R367CAB_T_O_ID_1, 0x00}, 1257 + {R367CAB_T_O_ID_2, 0x00}, 1258 + {R367CAB_T_O_ID_3, 0x00}, 1259 + {0x0000, 0x00} /* EOT */ 1260 + }; 1261 + 1262 + static const struct st_register def0367dd_base[] = { 1263 + {R367TER_IOCFG0, 0x80}, 1264 + {R367TER_DAC0R, 0x00}, 1265 + {R367TER_IOCFG1, 0x00}, 1266 + {R367TER_DAC1R, 0x00}, 1267 + {R367TER_IOCFG2, 0x00}, 1268 + {R367TER_SDFR, 0x00}, 1269 + {R367TER_AUX_CLK, 0x00}, 1270 + {R367TER_FREESYS1, 0x00}, 1271 + {R367TER_FREESYS2, 0x00}, 1272 + {R367TER_FREESYS3, 0x00}, 1273 + {R367TER_GPIO_CFG, 0x55}, 1274 + {R367TER_GPIO_CMD, 0x01}, 1275 + {R367TER_TSTRES, 0x00}, 1276 + {R367TER_ANACTRL, 0x00}, 1277 + {R367TER_TSTBUS, 0x00}, 1278 + {R367TER_RF_AGC2, 0x20}, 1279 + {R367TER_ANADIGCTRL, 0x0b}, 1280 + {R367TER_PLLMDIV, 0x01}, 1281 + {R367TER_PLLNDIV, 0x08}, 1282 + {R367TER_PLLSETUP, 0x18}, 1283 + {R367TER_DUAL_AD12, 0x04}, 1284 + {R367TER_TSTBIST, 0x00}, 1285 + {0x0000, 0x00} /* EOT */ 1286 + }; 1287 + 684 1288 /* 685 1289 * Tables combined 686 1290 */ ··· 1294 688 st_register *stv0367_deftabs[STV0367_DEFTAB_MAX][STV0367_TAB_MAX] = { 1295 689 /* generic default/init tabs */ 1296 690 { def0367ter, def0367cab, NULL }, 691 + /* default tabs for digital devices cards/flex modules */ 692 + { def0367dd_ofdm, def0367dd_qam, def0367dd_base }, 1297 693 }; 1298 694 1299 695 #endif