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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
[PATCH] ppc32: board-specific part of fs_enet update
This contains board-specific portion to respect driver changes (for 8272ads ,
885ads and 866ads). Altered platform_data structures as well as initial setup
routines relevant to fs_enet.
Changes to the mpc8560ads ppc/ code are also introduced, but mainly as
reference, since the entire board support is going to appear in arch/powerpc.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
authored by
Vitaly Bordug
and committed by
Jeff Garzik
2ca2d5e8
5b4b8454
+577
-390
+89
arch/ppc/platforms/85xx/mpc8560_ads.c
+89
arch/ppc/platforms/85xx/mpc8560_ads.c
···
29
29
#include <linux/initrd.h>
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#include <linux/module.h>
31
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#include <linux/fsl_devices.h>
32
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#include <linux/fs_enet_pd.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
···
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* Setup the architecture
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*
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*/
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static void init_fcc_ioports(void)
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{
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struct immap *immap;
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struct io_port *io;
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u32 tempval;
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+
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immap = cpm2_immr;
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+
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io = &immap->im_ioport;
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/* FCC2/3 are on the ports B/C. */
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB2_DIRB0;
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tempval |= PB2_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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+
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB2_PSORB0;
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tempval |= PB2_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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+
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tempval = in_be32(&io->iop_pparb);
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tempval |= (PB2_DIRB0 | PB2_DIRB1);
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out_be32(&io->iop_pparb, tempval);
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+
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB3_DIRB0;
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tempval |= PB3_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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+
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB3_PSORB0;
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tempval |= PB3_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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+
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tempval = in_be32(&io->iop_pparb);
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tempval |= (PB3_DIRB0 | PB3_DIRB1);
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out_be32(&io->iop_pparb, tempval);
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+
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tempval = in_be32(&io->iop_pdirc);
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tempval |= PC3_DIRC1;
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out_be32(&io->iop_pdirc, tempval);
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tempval = in_be32(&io->iop_pparc);
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tempval |= PC3_DIRC1;
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out_be32(&io->iop_pparc, tempval);
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+
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/* Port C has clocks...... */
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tempval = in_be32(&io->iop_psorc);
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tempval &= ~(CLK_TRX);
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out_be32(&io->iop_psorc, tempval);
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tempval = in_be32(&io->iop_pdirc);
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tempval &= ~(CLK_TRX);
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out_be32(&io->iop_pdirc, tempval);
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tempval = in_be32(&io->iop_pparc);
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tempval |= (CLK_TRX);
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out_be32(&io->iop_pparc, tempval);
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+
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/* Configure Serial Interface clock routing.
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* First, clear all FCC bits to zero,
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* then set the ones we want.
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*/
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immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
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immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
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}
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static void __init
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mpc8560ads_setup_arch(void)
···
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unsigned int freq;
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struct gianfar_platform_data *pdata;
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struct gianfar_mdio_data *mdata;
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struct fs_platform_info *fpi;
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cpm2_reset();
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···
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pdata->bus_id = 0;
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pdata->phy_id = 1;
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memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
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}
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+
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init_fcc_ioports();
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ppc_sys_device_remove(MPC85xx_CPM_FCC1);
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+
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fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
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if (fpi) {
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memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
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fpi->bus_id = "0:02";
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fpi->phy_addr = 2;
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fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
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fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
123
+
}
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+
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fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
126
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if (fpi) {
127
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memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
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fpi->macaddr[5] += 1;
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fpi->bus_id = "0:03";
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fpi->phy_addr = 3;
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fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
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fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
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}
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#ifdef CONFIG_BLK_DEV_INITRD
+19
arch/ppc/platforms/85xx/mpc85xx_ads_common.h
+19
arch/ppc/platforms/85xx/mpc85xx_ads_common.h
···
45
45
46
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#define MPC85XX_PCI1_IO_SIZE 0x01000000
47
47
48
+
/* FCC1 Clock Source Configuration. These can be
49
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* redefined in the board specific file.
50
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* Can only choose from CLK9-12 */
51
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#define F1_RXCLK 12
52
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#define F1_TXCLK 11
53
+
54
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/* FCC2 Clock Source Configuration. These can be
55
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* redefined in the board specific file.
56
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* Can only choose from CLK13-16 */
57
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#define F2_RXCLK 13
58
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#define F2_TXCLK 14
59
+
60
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/* FCC3 Clock Source Configuration. These can be
61
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* redefined in the board specific file.
62
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* Can only choose from CLK13-16 */
63
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#define F3_RXCLK 15
64
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#define F3_TXCLK 16
65
+
66
+
48
67
#endif /* __MACH_MPC85XX_ADS_H__ */
+84
-68
arch/ppc/platforms/mpc8272ads_setup.c
+84
-68
arch/ppc/platforms/mpc8272ads_setup.c
···
56
56
},
57
57
};
58
58
59
-
static struct fs_mii_bus_info mii_bus_info = {
60
-
.method = fsmii_bitbang,
61
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.id = 0,
62
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.i.bitbang = {
63
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.mdio_port = fsiop_portc,
64
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.mdio_bit = 18,
65
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.mdc_port = fsiop_portc,
66
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.mdc_bit = 19,
67
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.delay = 1,
59
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static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
60
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.mdio_dat.bit = 18,
61
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.mdio_dir.bit = 18,
62
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.mdc_dat.bit = 19,
63
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.delay = 1,
64
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};
65
+
66
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static struct fs_platform_info mpc82xx_enet_pdata[] = {
67
+
[fsid_fcc1] = {
68
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.fs_no = fsid_fcc1,
69
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.cp_page = CPM_CR_FCC1_PAGE,
70
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.cp_block = CPM_CR_FCC1_SBLOCK,
71
+
72
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.clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
73
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.clk_route = CMX1_CLK_ROUTE,
74
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.clk_mask = CMX1_CLK_MASK,
75
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.init_ioports = init_fcc1_ioports,
76
+
77
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.mem_offset = FCC1_MEM_OFFSET,
78
+
79
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.rx_ring = 32,
80
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.tx_ring = 32,
81
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.rx_copybreak = 240,
82
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.use_napi = 0,
83
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.napi_weight = 17,
84
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.bus_id = "0:00",
68
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},
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-
};
86
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[fsid_fcc2] = {
87
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.fs_no = fsid_fcc2,
88
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.cp_page = CPM_CR_FCC2_PAGE,
89
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.cp_block = CPM_CR_FCC2_SBLOCK,
90
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.clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
91
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.clk_route = CMX2_CLK_ROUTE,
92
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.clk_mask = CMX2_CLK_MASK,
93
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.init_ioports = init_fcc2_ioports,
70
94
71
-
static struct fs_platform_info mpc82xx_fcc1_pdata = {
72
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.fs_no = fsid_fcc1,
73
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.cp_page = CPM_CR_FCC1_PAGE,
74
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.cp_block = CPM_CR_FCC1_SBLOCK,
75
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.clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
76
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.clk_route = CMX1_CLK_ROUTE,
77
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.clk_mask = CMX1_CLK_MASK,
78
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.init_ioports = init_fcc1_ioports,
95
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.mem_offset = FCC2_MEM_OFFSET,
79
96
80
-
.phy_addr = 0,
81
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#ifdef PHY_INTERRUPT
82
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.phy_irq = PHY_INTERRUPT,
83
-
#else
84
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.phy_irq = -1;
85
-
#endif
86
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.mem_offset = FCC1_MEM_OFFSET,
87
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.bus_info = &mii_bus_info,
88
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.rx_ring = 32,
89
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.tx_ring = 32,
90
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.rx_copybreak = 240,
91
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.use_napi = 0,
92
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.napi_weight = 17,
93
-
};
94
-
95
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static struct fs_platform_info mpc82xx_fcc2_pdata = {
96
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.fs_no = fsid_fcc2,
97
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.cp_page = CPM_CR_FCC2_PAGE,
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.cp_block = CPM_CR_FCC2_SBLOCK,
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.clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
100
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.clk_route = CMX2_CLK_ROUTE,
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.clk_mask = CMX2_CLK_MASK,
102
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.init_ioports = init_fcc2_ioports,
103
-
104
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.phy_addr = 3,
105
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#ifdef PHY_INTERRUPT
106
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.phy_irq = PHY_INTERRUPT,
107
-
#else
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.phy_irq = -1;
109
-
#endif
110
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.mem_offset = FCC2_MEM_OFFSET,
111
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.bus_info = &mii_bus_info,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
115
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.use_napi = 0,
116
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.napi_weight = 17,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
100
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.use_napi = 0,
101
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.napi_weight = 17,
102
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.bus_id = "0:03",
103
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},
117
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};
118
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119
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static void init_fcc1_ioports(void)
···
196
209
bd_t* bi = (void*)__res;
197
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int fs_no = fsid_fcc1+pdev->id-1;
198
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199
-
mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
200
-
mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
201
-
202
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switch(fs_no) {
203
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case fsid_fcc1:
204
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memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
205
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pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
206
-
break;
207
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case fsid_fcc2:
208
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memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
209
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mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
210
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pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
211
-
break;
212
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if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) {
213
+
return;
212
214
}
215
+
216
+
mpc82xx_enet_pdata[fs_no].dpram_offset=
217
+
(u32)cpm2_immr->im_dprambase;
218
+
mpc82xx_enet_pdata[fs_no].fcc_regs_c =
219
+
(u32)cpm2_immr->im_fcc_c;
220
+
memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
221
+
222
+
/* prevent dup mac */
223
+
if(fs_no == fsid_fcc2)
224
+
mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
225
+
226
+
pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
213
227
}
214
228
215
229
static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
···
262
274
iounmap(immap);
263
275
}
264
276
277
+
static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
278
+
int idx)
279
+
{
280
+
m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
281
+
m82xx_mii_bb_pdata.irq[1] = -1;
282
+
m82xx_mii_bb_pdata.irq[2] = -1;
283
+
m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
284
+
m82xx_mii_bb_pdata.irq[31] = -1;
285
+
286
+
287
+
m82xx_mii_bb_pdata.mdio_dat.offset =
288
+
(u32)&cpm2_immr->im_ioport.iop_pdatc;
289
+
290
+
m82xx_mii_bb_pdata.mdio_dir.offset =
291
+
(u32)&cpm2_immr->im_ioport.iop_pdirc;
292
+
293
+
m82xx_mii_bb_pdata.mdc_dat.offset =
294
+
(u32)&cpm2_immr->im_ioport.iop_pdatc;
295
+
296
+
297
+
pdev->dev.platform_data = &m82xx_mii_bb_pdata;
298
+
}
299
+
265
300
static int mpc8272ads_platform_notify(struct device *dev)
266
301
{
267
302
static const struct platform_notify_dev_map dev_map[] = {
···
295
284
{
296
285
.bus_id = "fsl-cpm-scc:uart",
297
286
.rtn = mpc8272ads_fixup_uart_pdata,
287
+
},
288
+
{
289
+
.bus_id = "fsl-bb-mdio",
290
+
.rtn = mpc8272ads_fixup_mdio_pdata,
298
291
},
299
292
{
300
293
.bus_id = NULL
···
334
319
ppc_sys_device_enable(MPC82xx_CPM_SCC4);
335
320
#endif
336
321
322
+
ppc_sys_device_enable(MPC82xx_MDIO_BB);
337
323
338
324
return 0;
339
325
}
+96
-96
arch/ppc/platforms/mpc866ads_setup.c
+96
-96
arch/ppc/platforms/mpc866ads_setup.c
···
1
-
/*arch/ppc/platforms/mpc885ads-setup.c
1
+
/*arch/ppc/platforms/mpc866ads-setup.c
2
2
*
3
-
* Platform setup for the Freescale mpc885ads board
3
+
* Platform setup for the Freescale mpc866ads board
4
4
*
5
5
* Vitaly Bordug <vbordug@ru.mvista.com>
6
6
*
7
-
* Copyright 2005 MontaVista Software Inc.
7
+
* Copyright 2005-2006 MontaVista Software Inc.
8
8
*
9
9
* This file is licensed under the terms of the GNU General Public License
10
10
* version 2. This program is licensed "as is" without any warranty of any
···
42
42
static void setup_smc1_ioports(void);
43
43
static void setup_smc2_ioports(void);
44
44
45
-
static struct fs_mii_bus_info fec_mii_bus_info = {
46
-
.method = fsmii_fec,
47
-
.id = 0,
48
-
};
45
+
static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
49
46
50
-
static struct fs_mii_bus_info scc_mii_bus_info = {
51
-
.method = fsmii_fixed,
52
-
.id = 0,
53
-
.i.fixed.speed = 10,
54
-
.i.fixed.duplex = 0,
55
-
};
47
+
static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
56
48
57
-
static struct fs_platform_info mpc8xx_fec_pdata[] = {
58
-
{
59
-
.rx_ring = 128,
60
-
.tx_ring = 16,
61
-
.rx_copybreak = 240,
49
+
static struct fs_platform_info mpc8xx_enet_pdata[] = {
50
+
[fsid_fec1] = {
51
+
.rx_ring = 128,
52
+
.tx_ring = 16,
53
+
.rx_copybreak = 240,
62
54
63
-
.use_napi = 1,
64
-
.napi_weight = 17,
55
+
.use_napi = 1,
56
+
.napi_weight = 17,
65
57
66
-
.phy_addr = 15,
67
-
.phy_irq = -1,
58
+
.init_ioports = setup_fec1_ioports,
68
59
69
-
.use_rmii = 0,
60
+
.bus_id = "0:0f",
61
+
.has_phy = 1,
62
+
},
63
+
[fsid_scc1] = {
64
+
.rx_ring = 64,
65
+
.tx_ring = 8,
66
+
.rx_copybreak = 240,
67
+
.use_napi = 1,
68
+
.napi_weight = 17,
70
69
71
-
.bus_info = &fec_mii_bus_info,
72
-
}
73
-
};
74
70
75
-
static struct fs_platform_info mpc8xx_scc_pdata = {
76
-
.rx_ring = 64,
77
-
.tx_ring = 8,
78
-
.rx_copybreak = 240,
71
+
.init_ioports = setup_scc1_ioports,
79
72
80
-
.use_napi = 1,
81
-
.napi_weight = 17,
82
-
83
-
.phy_addr = -1,
84
-
.phy_irq = -1,
85
-
86
-
.bus_info = &scc_mii_bus_info,
87
-
73
+
.bus_id = "fixed@100:1",
74
+
},
88
75
};
89
76
90
77
static struct fs_uart_platform_info mpc866_uart_pdata[] = {
···
194
207
195
208
}
196
209
197
-
static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
198
-
{
199
-
struct fs_platform_info *fpi = pdev->dev.platform_data;
200
-
201
-
volatile cpm8xx_t *cp;
202
-
bd_t *bd = (bd_t *) __res;
203
-
char *e;
204
-
int i;
205
-
206
-
/* Get pointer to Communication Processor */
207
-
cp = cpmp;
208
-
switch (fs_no) {
209
-
case fsid_fec1:
210
-
fpi = &mpc8xx_fec_pdata[0];
211
-
fpi->init_ioports = &setup_fec1_ioports;
212
-
213
-
break;
214
-
case fsid_scc1:
215
-
fpi = &mpc8xx_scc_pdata;
216
-
fpi->init_ioports = &setup_scc1_ioports;
217
-
218
-
break;
219
-
default:
220
-
printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
221
-
return;
222
-
}
223
-
224
-
pdev->dev.platform_data = fpi;
225
-
fpi->fs_no = fs_no;
226
-
227
-
e = (unsigned char *)&bd->bi_enetaddr;
228
-
for (i = 0; i < 6; i++)
229
-
fpi->macaddr[i] = *e++;
230
-
231
-
fpi->macaddr[5 - pdev->id]++;
232
-
233
-
}
234
-
235
-
static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
236
-
int idx)
237
-
{
238
-
/* This is for FEC devices only */
239
-
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
240
-
return;
241
-
mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
242
-
}
243
-
244
-
static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
245
-
int idx)
246
-
{
247
-
/* This is for SCC devices only */
248
-
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
249
-
return;
250
-
251
-
mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
252
-
}
253
-
254
210
static void setup_smc1_ioports(void)
255
211
{
256
212
immap_t *immap = (immap_t *) IMAP_ADDR;
···
245
315
246
316
}
247
317
318
+
static int ma_count = 0;
319
+
320
+
static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
321
+
{
322
+
struct fs_platform_info *fpi;
323
+
324
+
volatile cpm8xx_t *cp;
325
+
bd_t *bd = (bd_t *) __res;
326
+
char *e;
327
+
int i;
328
+
329
+
/* Get pointer to Communication Processor */
330
+
cp = cpmp;
331
+
332
+
if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
333
+
printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
334
+
return;
335
+
}
336
+
337
+
338
+
fpi = &mpc8xx_enet_pdata[fs_no];
339
+
fpi->fs_no = fs_no;
340
+
pdev->dev.platform_data = fpi;
341
+
342
+
e = (unsigned char *)&bd->bi_enetaddr;
343
+
for (i = 0; i < 6; i++)
344
+
fpi->macaddr[i] = *e++;
345
+
346
+
fpi->macaddr[5] += ma_count++;
347
+
}
348
+
349
+
static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
350
+
int idx)
351
+
{
352
+
/* This is for FEC devices only */
353
+
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
354
+
return;
355
+
mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
356
+
}
357
+
358
+
static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
359
+
int idx)
360
+
{
361
+
/* This is for SCC devices only */
362
+
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
363
+
return;
364
+
365
+
mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
366
+
}
367
+
248
368
static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
249
369
int idx)
250
370
{
···
339
359
340
360
int __init mpc866ads_init(void)
341
361
{
362
+
bd_t *bd = (bd_t *) __res;
363
+
struct fs_mii_fec_platform_info* fmpi;
364
+
342
365
printk(KERN_NOTICE "mpc866ads: Init\n");
343
366
344
367
platform_notify = mpc866ads_platform_notify;
···
349
366
ppc_sys_device_initfunc();
350
367
ppc_sys_device_disable_all();
351
368
352
-
#ifdef MPC8xx_SECOND_ETH_SCC1
369
+
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1
353
370
ppc_sys_device_enable(MPC8xx_CPM_SCC1);
354
371
#endif
355
372
ppc_sys_device_enable(MPC8xx_CPM_FEC1);
373
+
374
+
ppc_sys_device_enable(MPC8xx_MDIO_FEC);
375
+
376
+
fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
377
+
&mpc8xx_mdio_fec_pdata;
378
+
379
+
fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
380
+
/* No PHY interrupt line here */
381
+
fmpi->irq[0xf] = -1;
356
382
357
383
/* Since either of the uarts could be used as console, they need to ready */
358
384
#ifdef CONFIG_SERIAL_CPM_SMC1
···
373
381
ppc_sys_device_enable(MPC8xx_CPM_SMC2);
374
382
ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
375
383
#endif
384
+
ppc_sys_device_enable(MPC8xx_MDIO_FEC);
385
+
386
+
fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
387
+
&mpc8xx_mdio_fec_pdata;
388
+
389
+
fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
390
+
/* No PHY interrupt line here */
391
+
fmpi->irq[0xf] = -1;
376
392
377
393
return 0;
378
394
}
+66
-109
arch/ppc/platforms/mpc885ads_setup.c
+66
-109
arch/ppc/platforms/mpc885ads_setup.c
···
38
38
static void setup_smc1_ioports(void);
39
39
static void setup_smc2_ioports(void);
40
40
41
-
static void __init mpc885ads_scc_phy_init(char);
41
+
static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
42
+
static void setup_fec1_ioports(void);
43
+
static void setup_fec2_ioports(void);
44
+
static void setup_scc3_ioports(void);
42
45
43
46
static struct fs_uart_platform_info mpc885_uart_pdata[] = {
44
47
[fsid_smc1_uart] = {
···
64
61
},
65
62
};
66
63
67
-
static struct fs_mii_bus_info fec_mii_bus_info = {
68
-
.method = fsmii_fec,
69
-
.id = 0,
70
-
};
71
-
72
-
static struct fs_mii_bus_info scc_mii_bus_info = {
73
-
#ifdef CONFIG_SCC_ENET_8xx_FIXED
74
-
.method = fsmii_fixed,
75
-
#else
76
-
.method = fsmii_fec,
77
-
#endif
78
-
79
-
.id = 0,
80
-
};
81
-
82
-
static struct fs_platform_info mpc8xx_fec_pdata[] = {
83
-
{
64
+
static struct fs_platform_info mpc8xx_enet_pdata[] = {
65
+
[fsid_fec1] = {
84
66
.rx_ring = 128,
85
67
.tx_ring = 16,
86
68
.rx_copybreak = 240,
···
73
85
.use_napi = 1,
74
86
.napi_weight = 17,
75
87
76
-
.phy_addr = 0,
77
-
.phy_irq = SIU_IRQ7,
88
+
.init_ioports = setup_fec1_ioports,
78
89
79
-
.bus_info = &fec_mii_bus_info,
80
-
}, {
90
+
.bus_id = "0:00",
91
+
.has_phy = 1,
92
+
},
93
+
[fsid_fec2] = {
81
94
.rx_ring = 128,
82
95
.tx_ring = 16,
83
96
.rx_copybreak = 240,
···
86
97
.use_napi = 1,
87
98
.napi_weight = 17,
88
99
89
-
.phy_addr = 1,
90
-
.phy_irq = SIU_IRQ7,
100
+
.init_ioports = setup_fec2_ioports,
91
101
92
-
.bus_info = &fec_mii_bus_info,
93
-
}
94
-
};
102
+
.bus_id = "0:01",
103
+
.has_phy = 1,
104
+
},
105
+
[fsid_scc3] = {
106
+
.rx_ring = 64,
107
+
.tx_ring = 8,
108
+
.rx_copybreak = 240,
95
109
96
-
static struct fs_platform_info mpc8xx_scc_pdata = {
97
-
.rx_ring = 64,
98
-
.tx_ring = 8,
99
-
.rx_copybreak = 240,
110
+
.use_napi = 1,
111
+
.napi_weight = 17,
100
112
101
-
.use_napi = 1,
102
-
.napi_weight = 17,
103
-
104
-
.phy_addr = 2,
105
-
#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED
106
-
.phy_irq = -1,
113
+
.init_ioports = setup_scc3_ioports,
114
+
#ifdef CONFIG_FIXED_MII_10_FDX
115
+
.bus_id = "fixed@100:1",
107
116
#else
108
-
.phy_irq = SIU_IRQ7,
109
-
#endif
110
-
111
-
.bus_info = &scc_mii_bus_info,
117
+
.bus_id = "0:02",
118
+
#endif
119
+
},
112
120
};
113
121
114
122
void __init board_init(void)
115
123
{
116
-
volatile cpm8xx_t *cp = cpmp;
117
-
unsigned int *bcsr_io;
124
+
cpm8xx_t *cp = cpmp;
125
+
unsigned int *bcsr_io;
118
126
119
127
#ifdef CONFIG_FS_ENET
120
128
immap_t *immap = (immap_t *) IMAP_ADDR;
···
150
164
/* use MDC for MII (common) */
151
165
setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
152
166
clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
167
+
bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
168
+
clrbits32(bcsr_io,BCSR5_MII1_EN);
169
+
clrbits32(bcsr_io,BCSR5_MII1_RST);
170
+
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
171
+
clrbits32(bcsr_io,BCSR5_MII2_EN);
172
+
clrbits32(bcsr_io,BCSR5_MII2_RST);
173
+
#endif
174
+
iounmap(bcsr_io);
153
175
#endif
154
176
}
155
177
···
188
194
/* configure FEC2 pins */
189
195
setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
190
196
setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
191
-
setbits32(&immap->im_cpm.cp_peso, 0x00037800);
192
197
clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
198
+
setbits32(&immap->im_cpm.cp_peso, 0x00037800);
193
199
clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
194
200
}
195
201
···
207
213
208
214
/* Enable the PHY.
209
215
*/
216
+
clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
217
+
udelay(1000);
210
218
setbits32(bcsr_io+4, BCSR4_ETH10_RST);
211
219
/* Configure port A pins for Txd and Rxd.
212
220
*/
···
250
254
clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
251
255
setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
252
256
253
-
setbits32(bcsr_io+1, BCSR1_ETHEN);
257
+
setbits32(bcsr_io+4, BCSR1_ETHEN);
254
258
iounmap(bcsr_io);
255
259
}
256
260
261
+
static int mac_count = 0;
262
+
257
263
static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
258
264
{
259
-
struct fs_platform_info *fpi = pdev->dev.platform_data;
260
-
261
-
volatile cpm8xx_t *cp;
265
+
struct fs_platform_info *fpi;
262
266
bd_t *bd = (bd_t *) __res;
263
267
char *e;
264
268
int i;
265
269
266
-
/* Get pointer to Communication Processor */
267
-
cp = cpmp;
270
+
if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
271
+
printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
272
+
return;
273
+
}
274
+
275
+
fpi = &mpc8xx_enet_pdata[fs_no];
276
+
268
277
switch (fs_no) {
269
278
case fsid_fec1:
270
-
fpi = &mpc8xx_fec_pdata[0];
271
279
fpi->init_ioports = &setup_fec1_ioports;
272
280
break;
273
281
case fsid_fec2:
274
-
fpi = &mpc8xx_fec_pdata[1];
275
282
fpi->init_ioports = &setup_fec2_ioports;
276
283
break;
277
284
case fsid_scc3:
278
-
fpi = &mpc8xx_scc_pdata;
279
285
fpi->init_ioports = &setup_scc3_ioports;
280
-
mpc885ads_scc_phy_init(fpi->phy_addr);
281
286
break;
282
287
default:
283
-
printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
288
+
printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
284
289
return;
285
290
}
286
291
···
292
295
for (i = 0; i < 6; i++)
293
296
fpi->macaddr[i] = *e++;
294
297
295
-
fpi->macaddr[5 - pdev->id]++;
298
+
fpi->macaddr[5] += mac_count++;
296
299
297
300
}
298
301
···
313
316
return;
314
317
315
318
mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
316
-
}
317
-
318
-
/* SCC ethernet controller does not have MII management channel. FEC1 MII
319
-
* channel is used to communicate with the 10Mbit PHY.
320
-
*/
321
-
322
-
#define MII_ECNTRL_PINMUX 0x4
323
-
#define FEC_ECNTRL_PINMUX 0x00000004
324
-
#define FEC_RCNTRL_MII_MODE 0x00000004
325
-
326
-
/* Make MII read/write commands.
327
-
*/
328
-
#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \
329
-
((VAL) & 0xffff) | ((PHY_ADDR) << 23))
330
-
331
-
static void mpc885ads_scc_phy_init(char phy_addr)
332
-
{
333
-
volatile immap_t *immap;
334
-
volatile fec_t *fecp;
335
-
bd_t *bd;
336
-
337
-
bd = (bd_t *) __res;
338
-
immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
339
-
fecp = &(immap->im_cpm.cp_fec);
340
-
341
-
/* Enable MII pins of the FEC1
342
-
*/
343
-
setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
344
-
clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
345
-
/* Set MII speed to 2.5 MHz
346
-
*/
347
-
out_be32(&fecp->fec_mii_speed,
348
-
((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
349
-
350
-
/* Enable FEC pin MUX
351
-
*/
352
-
setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
353
-
setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
354
-
355
-
out_be32(&fecp->fec_mii_data,
356
-
mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
357
-
udelay(100);
358
-
out_be32(&fecp->fec_mii_data,
359
-
mk_mii_write(MII_ADVERTISE,
360
-
ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));
361
-
udelay(100);
362
-
363
-
/* Disable FEC MII settings
364
-
*/
365
-
clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
366
-
clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
367
-
out_be32(&fecp->fec_mii_speed, 0);
368
319
}
369
320
370
321
static void setup_smc1_ioports(void)
···
407
462
408
463
int __init mpc885ads_init(void)
409
464
{
465
+
struct fs_mii_fec_platform_info* fmpi;
466
+
bd_t *bd = (bd_t *) __res;
467
+
410
468
printk(KERN_NOTICE "mpc885ads: Init\n");
411
469
412
470
platform_notify = mpc885ads_platform_notify;
···
419
471
420
472
ppc_sys_device_enable(MPC8xx_CPM_FEC1);
421
473
474
+
ppc_sys_device_enable(MPC8xx_MDIO_FEC);
475
+
fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
476
+
&mpc8xx_mdio_fec_pdata;
477
+
478
+
fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
479
+
480
+
/* No PHY interrupt line here */
481
+
fmpi->irq[0xf] = SIU_IRQ7;
482
+
422
483
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
423
-
ppc_sys_device_enable(MPC8xx_CPM_SCC1);
484
+
ppc_sys_device_enable(MPC8xx_CPM_SCC3);
424
485
425
486
#endif
426
487
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
-82
arch/ppc/platforms/pq2ads_pd.h
-82
arch/ppc/platforms/pq2ads_pd.h
···
29
29
#define F3_RXCLK 13
30
30
#define F3_TXCLK 14
31
31
32
-
/* Automatically generates register configurations */
33
-
#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
34
-
35
-
#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
36
-
#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
37
-
#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
38
-
#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
39
-
#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
40
-
#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
41
-
42
-
#define PC_F1RXCLK PC_CLK(F1_RXCLK)
43
-
#define PC_F1TXCLK PC_CLK(F1_TXCLK)
44
-
#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
45
-
#define CMX1_CLK_MASK ((uint)0xff000000)
46
-
47
-
#define PC_F2RXCLK PC_CLK(F2_RXCLK)
48
-
#define PC_F2TXCLK PC_CLK(F2_TXCLK)
49
-
#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
50
-
#define CMX2_CLK_MASK ((uint)0x00ff0000)
51
-
52
-
#define PC_F3RXCLK PC_CLK(F3_RXCLK)
53
-
#define PC_F3TXCLK PC_CLK(F3_TXCLK)
54
-
#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
55
-
#define CMX3_CLK_MASK ((uint)0x0000ff00)
56
-
57
-
/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
58
-
* but there is little variation among the choices.
59
-
*/
60
-
#define PA1_COL 0x00000001U
61
-
#define PA1_CRS 0x00000002U
62
-
#define PA1_TXER 0x00000004U
63
-
#define PA1_TXEN 0x00000008U
64
-
#define PA1_RXDV 0x00000010U
65
-
#define PA1_RXER 0x00000020U
66
-
#define PA1_TXDAT 0x00003c00U
67
-
#define PA1_RXDAT 0x0003c000U
68
-
#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
69
-
#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
70
-
PA1_RXDV | PA1_RXER)
71
-
#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
72
-
#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
73
-
74
-
75
-
/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
76
-
* but there is little variation among the choices.
77
-
*/
78
-
#define PB2_TXER 0x00000001U
79
-
#define PB2_RXDV 0x00000002U
80
-
#define PB2_TXEN 0x00000004U
81
-
#define PB2_RXER 0x00000008U
82
-
#define PB2_COL 0x00000010U
83
-
#define PB2_CRS 0x00000020U
84
-
#define PB2_TXDAT 0x000003c0U
85
-
#define PB2_RXDAT 0x00003c00U
86
-
#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
87
-
PB2_RXER | PB2_RXDV | PB2_TXER)
88
-
#define PB2_PSORB1 (PB2_TXEN)
89
-
#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
90
-
#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
91
-
92
-
93
-
/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
94
-
* but there is little variation among the choices.
95
-
*/
96
-
#define PB3_RXDV 0x00004000U
97
-
#define PB3_RXER 0x00008000U
98
-
#define PB3_TXER 0x00010000U
99
-
#define PB3_TXEN 0x00020000U
100
-
#define PB3_COL 0x00040000U
101
-
#define PB3_CRS 0x00080000U
102
-
#define PB3_TXDAT 0x0f000000U
103
-
#define PB3_RXDAT 0x00f00000U
104
-
#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
105
-
PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
106
-
#define PB3_PSORB1 0
107
-
#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
108
-
#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
109
-
110
-
#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
111
-
#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
112
-
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
113
-
114
32
#endif
+86
-3
arch/ppc/syslib/mpc85xx_devices.c
+86
-3
arch/ppc/syslib/mpc85xx_devices.c
···
16
16
#include <linux/device.h>
17
17
#include <linux/serial_8250.h>
18
18
#include <linux/fsl_devices.h>
19
+
#include <linux/fs_enet_pd.h>
19
20
#include <asm/mpc85xx.h>
20
21
#include <asm/irq.h>
21
22
#include <asm/ppc_sys.h>
23
+
#include <asm/cpm2.h>
22
24
23
25
/* We use offsets for IORESOURCE_MEM since we do not know at compile time
24
26
* what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
···
82
80
83
81
static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84
82
.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
83
+
};
84
+
85
+
static struct fs_platform_info mpc85xx_fcc1_pdata = {
86
+
.fs_no = fsid_fcc1,
87
+
.cp_page = CPM_CR_FCC1_PAGE,
88
+
.cp_block = CPM_CR_FCC1_SBLOCK,
89
+
90
+
.rx_ring = 32,
91
+
.tx_ring = 32,
92
+
.rx_copybreak = 240,
93
+
.use_napi = 0,
94
+
.napi_weight = 17,
95
+
96
+
.clk_mask = CMX1_CLK_MASK,
97
+
.clk_route = CMX1_CLK_ROUTE,
98
+
.clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
99
+
100
+
.mem_offset = FCC1_MEM_OFFSET,
101
+
};
102
+
103
+
static struct fs_platform_info mpc85xx_fcc2_pdata = {
104
+
.fs_no = fsid_fcc2,
105
+
.cp_page = CPM_CR_FCC2_PAGE,
106
+
.cp_block = CPM_CR_FCC2_SBLOCK,
107
+
108
+
.rx_ring = 32,
109
+
.tx_ring = 32,
110
+
.rx_copybreak = 240,
111
+
.use_napi = 0,
112
+
.napi_weight = 17,
113
+
114
+
.clk_mask = CMX2_CLK_MASK,
115
+
.clk_route = CMX2_CLK_ROUTE,
116
+
.clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
117
+
118
+
.mem_offset = FCC2_MEM_OFFSET,
119
+
};
120
+
121
+
static struct fs_platform_info mpc85xx_fcc3_pdata = {
122
+
.fs_no = fsid_fcc3,
123
+
.cp_page = CPM_CR_FCC3_PAGE,
124
+
.cp_block = CPM_CR_FCC3_SBLOCK,
125
+
126
+
.rx_ring = 32,
127
+
.tx_ring = 32,
128
+
.rx_copybreak = 240,
129
+
.use_napi = 0,
130
+
.napi_weight = 17,
131
+
132
+
.clk_mask = CMX3_CLK_MASK,
133
+
.clk_route = CMX3_CLK_ROUTE,
134
+
.clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
135
+
136
+
.mem_offset = FCC3_MEM_OFFSET,
85
137
};
86
138
87
139
static struct plat_serial8250_port serial_platform_data[] = {
···
374
318
[MPC85xx_CPM_FCC1] = {
375
319
.name = "fsl-cpm-fcc",
376
320
.id = 1,
377
-
.num_resources = 3,
321
+
.num_resources = 4,
322
+
.dev.platform_data = &mpc85xx_fcc1_pdata,
378
323
.resource = (struct resource[]) {
379
324
{
325
+
.name = "fcc_regs",
380
326
.start = 0x91300,
381
327
.end = 0x9131F,
382
328
.flags = IORESOURCE_MEM,
383
329
},
384
330
{
331
+
.name = "fcc_regs_c",
385
332
.start = 0x91380,
386
333
.end = 0x9139F,
334
+
.flags = IORESOURCE_MEM,
335
+
},
336
+
{
337
+
.name = "fcc_pram",
338
+
.start = 0x88400,
339
+
.end = 0x884ff,
387
340
.flags = IORESOURCE_MEM,
388
341
},
389
342
{
···
405
340
[MPC85xx_CPM_FCC2] = {
406
341
.name = "fsl-cpm-fcc",
407
342
.id = 2,
408
-
.num_resources = 3,
343
+
.num_resources = 4,
344
+
.dev.platform_data = &mpc85xx_fcc2_pdata,
409
345
.resource = (struct resource[]) {
410
346
{
347
+
.name = "fcc_regs",
411
348
.start = 0x91320,
412
349
.end = 0x9133F,
413
350
.flags = IORESOURCE_MEM,
414
351
},
415
352
{
353
+
.name = "fcc_regs_c",
416
354
.start = 0x913A0,
417
355
.end = 0x913CF,
356
+
.flags = IORESOURCE_MEM,
357
+
},
358
+
{
359
+
.name = "fcc_pram",
360
+
.start = 0x88500,
361
+
.end = 0x885ff,
418
362
.flags = IORESOURCE_MEM,
419
363
},
420
364
{
···
436
362
[MPC85xx_CPM_FCC3] = {
437
363
.name = "fsl-cpm-fcc",
438
364
.id = 3,
439
-
.num_resources = 3,
365
+
.num_resources = 4,
366
+
.dev.platform_data = &mpc85xx_fcc3_pdata,
440
367
.resource = (struct resource[]) {
441
368
{
369
+
.name = "fcc_regs",
442
370
.start = 0x91340,
443
371
.end = 0x9135F,
444
372
.flags = IORESOURCE_MEM,
445
373
},
446
374
{
375
+
.name = "fcc_regs_c",
447
376
.start = 0x913D0,
448
377
.end = 0x913FF,
378
+
.flags = IORESOURCE_MEM,
379
+
},
380
+
{
381
+
.name = "fcc_pram",
382
+
.start = 0x88600,
383
+
.end = 0x886ff,
449
384
.flags = IORESOURCE_MEM,
450
385
},
451
386
{
+8
arch/ppc/syslib/mpc8xx_devices.c
+8
arch/ppc/syslib/mpc8xx_devices.c
+4
-2
arch/ppc/syslib/mpc8xx_sys.c
+4
-2
arch/ppc/syslib/mpc8xx_sys.c
···
22
22
.ppc_sys_name = "MPC86X",
23
23
.mask = 0xFFFFFFFF,
24
24
.value = 0x00000000,
25
-
.num_devices = 7,
25
+
.num_devices = 8,
26
26
.device_list = (enum ppc_sys_devices[])
27
27
{
28
28
MPC8xx_CPM_FEC1,
···
32
32
MPC8xx_CPM_SCC4,
33
33
MPC8xx_CPM_SMC1,
34
34
MPC8xx_CPM_SMC2,
35
+
MPC8xx_MDIO_FEC,
35
36
},
36
37
},
37
38
{
38
39
.ppc_sys_name = "MPC885",
39
40
.mask = 0xFFFFFFFF,
40
41
.value = 0x00000000,
41
-
.num_devices = 8,
42
+
.num_devices = 9,
42
43
.device_list = (enum ppc_sys_devices[])
43
44
{
44
45
MPC8xx_CPM_FEC1,
···
50
49
MPC8xx_CPM_SCC4,
51
50
MPC8xx_CPM_SMC1,
52
51
MPC8xx_CPM_SMC2,
52
+
MPC8xx_MDIO_FEC,
53
53
},
54
54
},
55
55
{ /* default match */
+5
arch/ppc/syslib/pq2_devices.c
+5
arch/ppc/syslib/pq2_devices.c
+2
-1
arch/ppc/syslib/pq2_sys.c
+2
-1
arch/ppc/syslib/pq2_sys.c
···
139
139
.ppc_sys_name = "8272",
140
140
.mask = 0x0000ff00,
141
141
.value = 0x00000c00,
142
-
.num_devices = 12,
142
+
.num_devices = 13,
143
143
.device_list = (enum ppc_sys_devices[])
144
144
{
145
145
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
146
146
MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4,
147
147
MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
148
148
MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1,
149
+
MPC82xx_MDIO_BB,
149
150
},
150
151
},
151
152
/* below is a list of the 8280 family of processors */
+95
include/asm-ppc/cpm2.h
+95
include/asm-ppc/cpm2.h
···
1093
1093
1094
1094
#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1095
1095
1096
+
/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1097
+
* in order to use clock-computing stuff below for the FCC x
1098
+
*/
1099
+
1100
+
/* Automatically generates register configurations */
1101
+
#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1102
+
1103
+
#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1104
+
#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1105
+
#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1106
+
#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1107
+
#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1108
+
#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1109
+
1110
+
#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1111
+
#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1112
+
#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1113
+
#define CMX1_CLK_MASK ((uint)0xff000000)
1114
+
1115
+
#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1116
+
#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1117
+
#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1118
+
#define CMX2_CLK_MASK ((uint)0x00ff0000)
1119
+
1120
+
#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1121
+
#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1122
+
#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1123
+
#define CMX3_CLK_MASK ((uint)0x0000ff00)
1124
+
1125
+
#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1126
+
#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1127
+
1128
+
#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1129
+
1130
+
/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1131
+
* but there is little variation among the choices.
1132
+
*/
1133
+
#define PA1_COL 0x00000001U
1134
+
#define PA1_CRS 0x00000002U
1135
+
#define PA1_TXER 0x00000004U
1136
+
#define PA1_TXEN 0x00000008U
1137
+
#define PA1_RXDV 0x00000010U
1138
+
#define PA1_RXER 0x00000020U
1139
+
#define PA1_TXDAT 0x00003c00U
1140
+
#define PA1_RXDAT 0x0003c000U
1141
+
#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1142
+
#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1143
+
PA1_RXDV | PA1_RXER)
1144
+
#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1145
+
#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1146
+
1147
+
1148
+
/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1149
+
* but there is little variation among the choices.
1150
+
*/
1151
+
#define PB2_TXER 0x00000001U
1152
+
#define PB2_RXDV 0x00000002U
1153
+
#define PB2_TXEN 0x00000004U
1154
+
#define PB2_RXER 0x00000008U
1155
+
#define PB2_COL 0x00000010U
1156
+
#define PB2_CRS 0x00000020U
1157
+
#define PB2_TXDAT 0x000003c0U
1158
+
#define PB2_RXDAT 0x00003c00U
1159
+
#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1160
+
PB2_RXER | PB2_RXDV | PB2_TXER)
1161
+
#define PB2_PSORB1 (PB2_TXEN)
1162
+
#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1163
+
#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1164
+
1165
+
1166
+
/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1167
+
* but there is little variation among the choices.
1168
+
*/
1169
+
#define PB3_RXDV 0x00004000U
1170
+
#define PB3_RXER 0x00008000U
1171
+
#define PB3_TXER 0x00010000U
1172
+
#define PB3_TXEN 0x00020000U
1173
+
#define PB3_COL 0x00040000U
1174
+
#define PB3_CRS 0x00080000U
1175
+
#define PB3_TXDAT 0x0f000000U
1176
+
#define PC3_TXDAT 0x00000010U
1177
+
#define PB3_RXDAT 0x00f00000U
1178
+
#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1179
+
PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1180
+
#define PB3_PSORB1 0
1181
+
#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1182
+
#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1183
+
#define PC3_DIRC1 (PC3_TXDAT)
1184
+
1185
+
/* Handy macro to specify mem for FCCs*/
1186
+
#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1187
+
#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1188
+
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1189
+
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(2)
1190
+
1096
1191
#endif /* __CPM2__ */
1097
1192
#endif /* __KERNEL__ */
+1
include/asm-ppc/mpc8260.h
+1
include/asm-ppc/mpc8260.h
+1
include/asm-ppc/mpc8xx.h
+1
include/asm-ppc/mpc8xx.h
+21
-29
include/linux/fs_enet_pd.h
+21
-29
include/linux/fs_enet_pd.h
···
69
69
fsiop_porte,
70
70
};
71
71
72
-
struct fs_mii_bus_info {
73
-
int method; /* mii method */
74
-
int id; /* the id of the mii_bus */
75
-
int disable_aneg; /* if the controller needs to negothiate speed & duplex */
76
-
int lpa; /* the default board-specific vallues will be applied otherwise */
77
-
78
-
union {
79
-
struct {
80
-
int duplex;
81
-
int speed;
82
-
} fixed;
83
-
84
-
struct {
85
-
/* nothing */
86
-
} fec;
87
-
88
-
struct {
89
-
/* nothing */
90
-
} scc;
91
-
92
-
struct {
93
-
int mdio_port; /* port & bit for MDIO */
94
-
int mdio_bit;
95
-
int mdc_port; /* port & bit for MDC */
96
-
int mdc_bit;
97
-
int delay; /* delay in us */
98
-
} bitbang;
99
-
} i;
72
+
struct fs_mii_bit {
73
+
u32 offset;
74
+
u8 bit;
75
+
u8 polarity;
76
+
};
77
+
struct fs_mii_bb_platform_info {
78
+
struct fs_mii_bit mdio_dir;
79
+
struct fs_mii_bit mdio_dat;
80
+
struct fs_mii_bit mdc_dat;
81
+
int mdio_port; /* port & bit for MDIO */
82
+
int mdio_bit;
83
+
int mdc_port; /* port & bit for MDC */
84
+
int mdc_bit;
85
+
int delay; /* delay in us */
86
+
int irq[32]; /* irqs per phy's */
100
87
};
101
88
102
89
struct fs_platform_info {
···
106
119
u32 device_flags;
107
120
108
121
int phy_addr; /* the phy address (-1 no phy) */
122
+
const char* bus_id;
109
123
int phy_irq; /* the phy irq (if it exists) */
110
124
111
125
const struct fs_mii_bus_info *bus_info;
···
118
130
int napi_weight; /* NAPI weight */
119
131
120
132
int use_rmii; /* use RMII mode */
133
+
int has_phy; /* if the network is phy container as well...*/
121
134
};
122
-
135
+
struct fs_mii_fec_platform_info {
136
+
u32 irq[32];
137
+
u32 mii_speed;
138
+
};
123
139
#endif