Merge tag 'qcom-arm64-for-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

+105 -6

Documentation/devicetree/bindings/arm/qcom.yaml

··· 38 38 msm8992 39 39 msm8994 40 40 msm8996 41 + msm8998 42 + qcs404 41 43 sa8155p 42 44 sa8540p 43 45 sc7180 ··· 49 47 sda660 50 48 sdm630 51 49 sdm632 50 + sdm636 52 51 sdm660 53 52 sdm845 54 53 sdx55 55 54 sdx65 55 + sm6125 56 + sm6350 56 57 sm7225 57 58 sm8150 58 59 sm8250 ··· 164 159 - const: qcom,msm8974 165 160 166 161 - items: 167 - - enum: 168 - - alcatel,idol347 169 - - const: qcom,msm8916-mtp/1 170 162 - const: qcom,msm8916-mtp 163 + - const: qcom,msm8916-mtp/1 171 164 - const: qcom,msm8916 172 165 173 166 - items: 174 167 - enum: 175 - - longcheer,l8150 168 + - alcatel,idol347 169 + - asus,z00l 170 + - huawei,g7 171 + - longcheer,l8910 176 172 - samsung,a3u-eur 177 173 - samsung,a5u-eur 174 + - samsung,j5 175 + - samsung,serranove 176 + - wingtech,wt88047 178 177 - const: qcom,msm8916 178 + 179 + - items: 180 + - const: longcheer,l8150 181 + - const: qcom,msm8916-v1-qrd/9-v1 182 + - const: qcom,msm8916 183 + 184 + - items: 185 + - enum: 186 + - lg,bullhead 187 + - microsoft,talkman 188 + - xiaomi,libra 189 + - const: qcom,msm8992 179 190 180 191 - items: 181 192 - enum: 182 193 - sony,karin_windy 194 + - const: qcom,apq8094 195 + 196 + - items: 197 + - enum: 198 + - huawei,angler 199 + - microsoft,cityman 200 + - sony,ivy-row 183 201 - sony,karin-row 184 202 - sony,satsuki-row 185 203 - sony,sumire-row 186 204 - sony,suzuran-row 187 - - qcom,msm8994 188 - - const: qcom,apq8094 205 + - const: qcom,msm8994 189 206 190 207 - items: 191 208 - enum: ··· 226 199 - xiaomi,natrium 227 200 - xiaomi,scorpio 228 201 - const: qcom,msm8996 202 + 203 + - items: 204 + - enum: 205 + - asus,novago-tp370ql 206 + - fxtec,pro1 207 + - hp,envy-x2 208 + - lenovo,miix-630 209 + - oneplus,cheeseburger 210 + - oneplus,dumpling 211 + - qcom,msm8998-mtp 212 + - sony,xperia-lilac 213 + - sony,xperia-maple 214 + - sony,xperia-poplar 215 + - const: qcom,msm8998 229 216 230 217 - items: 231 218 - enum: ··· 591 550 592 551 - items: 593 552 - enum: 553 + - sony,discovery-row 554 + - sony,kirin-row 555 + - sony,pioneer-row 556 + - sony,voyager-row 557 + - const: qcom,sdm630 558 + 559 + - items: 560 + - enum: 594 561 - inforce,ifc6560 595 562 - const: qcom,sda660 596 563 ··· 606 557 - enum: 607 558 - fairphone,fp3 608 559 - const: qcom,sdm632 560 + 561 + - items: 562 + - enum: 563 + - sony,mermaid-row 564 + - const: qcom,sdm636 609 565 610 566 - items: 611 567 - enum: ··· 637 583 638 584 - items: 639 585 - enum: 586 + - qcom,qcs404-evb-1000 587 + - qcom,qcs404-evb-4000 588 + - const: qcom,qcs404-evb 589 + - const: qcom,qcs404 590 + 591 + - items: 592 + - enum: 640 593 - qcom,sa8155p-adp 641 594 - const: qcom,sa8155p 642 595 ··· 654 593 655 594 - items: 656 595 - enum: 596 + - lenovo,yoga-c630 597 + - lg,judyln 598 + - lg,judyp 599 + - oneplus,enchilada 600 + - oneplus,fajita 601 + - qcom,sdm845-mtp 602 + - shift,axolotl 603 + - samsung,w737 604 + - sony,akari-row 605 + - sony,akatsuki-row 606 + - sony,apollo-row 607 + - thundercomm,db845c 608 + - xiaomi,beryllium 609 + - xiaomi,polaris 610 + - const: qcom,sdm845 611 + 612 + - items: 613 + - enum: 614 + - sony,pdx201 615 + - const: qcom,sm6125 616 + 617 + - items: 618 + - enum: 619 + - sony,pdx213 620 + - const: qcom,sm6350 621 + 622 + - items: 623 + - enum: 657 624 - fairphone,fp4 658 625 - const: qcom,sm7225 659 626 660 627 - items: 661 628 - enum: 629 + - microsoft,surface-duo 630 + - qcom,sm8150-hdk 662 631 - qcom,sm8150-mtp 632 + - sony,bahamut-generic 633 + - sony,griffin-generic 663 634 - const: qcom,sm8150 664 635 665 636 - items: 666 637 - enum: 667 638 - qcom,qrb5165-rb5 639 + - qcom,sm8250-hdk 668 640 - qcom,sm8250-mtp 641 + - sony,pdx203-generic 642 + - sony,pdx206-generic 669 643 - const: qcom,sm8250 670 644 671 645 - items: 672 646 - enum: 647 + - microsoft,surface-duo2 673 648 - qcom,sm8350-hdk 674 649 - qcom,sm8350-mtp 650 + - sony,pdx214-generic 651 + - sony,pdx215-generic 675 652 - const: qcom,sm8350 676 653 677 654 - items:

+2 -2

Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml

··· 63 63 examples: 64 64 - | 65 65 / { 66 - model = "Qualcomm Technologies, Inc. QCS404"; 67 - compatible = "qcom,qcs404"; 66 + model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; 67 + compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404"; 68 68 #address-cells = <2>; 69 69 #size-cells = <2>; 70 70

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 1103 1103 description: SGX Sensortech 1104 1104 "^sharp,.*": 1105 1105 description: Sharp Corporation 1106 + "^shift,.*": 1107 + description: SHIFT GmbH 1106 1108 "^shimafuji,.*": 1107 1109 description: Shimafuji Electric, Inc. 1108 1110 "^shiratech,.*":

+1

arch/arm64/boot/dts/qcom/Makefile

··· 129 129 dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb 130 130 dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb 131 131 dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb 132 + dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb 132 133 dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb 133 134 dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb 134 135 dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb

-3

arch/arm64/boot/dts/qcom/ipq8074-hk01.dts

··· 5 5 #include "ipq8074.dtsi" 6 6 7 7 / { 8 - #address-cells = <0x2>; 9 - #size-cells = <0x2>; 10 8 model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; 11 9 compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; 12 - interrupt-parent = <&intc>; 13 10 14 11 aliases { 15 12 serial0 = &blsp1_uart5;

-5

arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi

··· 7 7 #include "ipq8074.dtsi" 8 8 9 9 / { 10 - #address-cells = <0x2>; 11 - #size-cells = <0x2>; 12 - 13 - interrupt-parent = <&intc>; 14 - 15 10 aliases { 16 11 serial0 = &blsp1_uart5; 17 12 };

+12

arch/arm64/boot/dts/qcom/ipq8074.dtsi

··· 7 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 8 9 9 / { 10 + #address-cells = <2>; 11 + #size-cells = <2>; 12 + 10 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 14 compatible = "qcom,ipq8074"; 15 + interrupt-parent = <&intc>; 12 16 13 17 clocks { 14 18 sleep_clk: sleep_clk { ··· 664 660 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 665 661 clocks = <&sleep_clk>; 666 662 timeout-sec = <30>; 663 + }; 664 + 665 + apcs_glb: mailbox@b111000 { 666 + compatible = "qcom,ipq8074-apcs-apps-global"; 667 + reg = <0x0b111000 0x6000>; 668 + 669 + #clock-cells = <1>; 670 + #mbox-cells = <1>; 667 671 }; 668 672 669 673 timer@b120000 {

+6 -4

arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts

··· 26 26 }; 27 27 28 28 &vreg_l18a_2p85 { 29 - regulator-min-microvolt = <2850000>; 30 - regulator-max-microvolt = <2850000>; 29 + /* Note: Round-down from 2850000 to be a multiple of PLDO step-size 8000 */ 30 + regulator-min-microvolt = <2848000>; 31 + regulator-max-microvolt = <2848000>; 31 32 }; 32 33 33 34 &vreg_l22a_2p85 { 34 - regulator-min-microvolt = <2700000>; 35 - regulator-max-microvolt = <2700000>; 35 + /* Note: Round-down from 2700000 to be a multiple of PLDO step-size 8000 */ 36 + regulator-min-microvolt = <2696000>; 37 + regulator-max-microvolt = <2696000>; 36 38 };

+2 -2

arch/arm64/boot/dts/qcom/qcs404.dtsi

··· 548 548 compatible = "snps,dwc3"; 549 549 reg = <0x07580000 0xcd00>; 550 550 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 551 - phys = <&usb2_phy_sec>, <&usb3_phy>; 551 + phys = <&usb2_phy_prim>, <&usb3_phy>; 552 552 phy-names = "usb2-phy", "usb3-phy"; 553 553 snps,has-lpm-erratum; 554 554 snps,hird-threshold = /bits/ 8 <0x10>; ··· 577 577 compatible = "snps,dwc3"; 578 578 reg = <0x078c0000 0xcc00>; 579 579 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 580 - phys = <&usb2_phy_prim>; 580 + phys = <&usb2_phy_sec>; 581 581 phy-names = "usb2-phy"; 582 582 snps,has-lpm-erratum; 583 583 snps,hird-threshold = /bits/ 8 <0x10>;

+6 -4

arch/arm64/boot/dts/qcom/qrb5165-rb5.dts

··· 58 58 leds { 59 59 compatible = "gpio-leds"; 60 60 61 - user4 { 61 + led-user4 { 62 62 label = "green:user4"; 63 63 function = LED_FUNCTION_INDICATOR; 64 64 color = <LED_COLOR_ID_GREEN>; ··· 67 67 default-state = "off"; 68 68 }; 69 69 70 - wlan { 70 + led-wlan { 71 71 label = "yellow:wlan"; 72 72 function = LED_FUNCTION_WLAN; 73 73 color = <LED_COLOR_ID_YELLOW>; ··· 76 76 default-state = "off"; 77 77 }; 78 78 79 - bt { 79 + led-bt { 80 80 label = "blue:bt"; 81 81 function = LED_FUNCTION_BLUETOOTH; 82 82 color = <LED_COLOR_ID_BLUE>; ··· 84 84 linux,default-trigger = "bluetooth-power"; 85 85 default-state = "off"; 86 86 }; 87 - 88 87 }; 89 88 90 89 lt9611_1v2: lt9611-vdd12-regulator { ··· 814 815 815 816 &pm8150l_lpg { 816 817 status = "okay"; 818 + 819 + #address-cells = <1>; 820 + #size-cells = <0>; 817 821 818 822 led@1 { 819 823 reg = <1>;

+6 -3

arch/arm64/boot/dts/qcom/sc7180.dtsi

··· 2911 2911 2912 2912 status = "disabled"; 2913 2913 2914 - mdp: mdp@ae01000 { 2914 + mdp: display-controller@ae01000 { 2915 2915 compatible = "qcom,sc7180-dpu"; 2916 2916 reg = <0 0x0ae01000 0 0x8f000>, 2917 2917 <0 0x0aeb0000 0 0x2008>; ··· 3080 3080 compatible = "qcom,sc7180-dp"; 3081 3081 status = "disabled"; 3082 3082 3083 - reg = <0 0x0ae90000 0 0x1400>; 3083 + reg = <0 0xae90000 0 0x200>, 3084 + <0 0xae90200 0 0x200>, 3085 + <0 0xae90400 0 0xc00>, 3086 + <0 0xae91000 0 0x400>, 3087 + <0 0xae91400 0 0x400>; 3084 3088 3085 3089 interrupt-parent = <&mdss>; 3086 3090 interrupts = <12>; ··· 3096 3092 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3097 3093 clock-names = "core_iface", "core_aux", "ctrl_link", 3098 3094 "ctrl_link_iface", "stream_pixel"; 3099 - #clock-cells = <1>; 3100 3095 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3101 3096 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3102 3097 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;

+64

arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi

··· 5 5 * Copyright (c) 2022, The Linux Foundation. All rights reserved. 6 6 */ 7 7 8 + /* PINCTRL */ 9 + 10 + &lpass_dmic01_clk { 11 + drive-strength = <8>; 12 + bias-disable; 13 + }; 14 + 15 + &lpass_dmic01_clk_sleep { 16 + drive-strength = <2>; 17 + }; 18 + 19 + &lpass_dmic01_data { 20 + bias-pull-down; 21 + }; 22 + 23 + &lpass_dmic23_clk { 24 + drive-strength = <8>; 25 + bias-disable; 26 + }; 27 + 28 + &lpass_dmic23_clk_sleep { 29 + drive-strength = <2>; 30 + }; 31 + 32 + &lpass_dmic23_data { 33 + bias-pull-down; 34 + }; 35 + 36 + &lpass_rx_swr_clk { 37 + drive-strength = <2>; 38 + slew-rate = <1>; 39 + bias-disable; 40 + }; 41 + 42 + &lpass_rx_swr_clk_sleep { 43 + bias-pull-down; 44 + }; 45 + 46 + &lpass_rx_swr_data { 47 + drive-strength = <2>; 48 + slew-rate = <1>; 49 + bias-bus-hold; 50 + }; 51 + 52 + &lpass_rx_swr_data_sleep { 53 + bias-pull-down; 54 + }; 55 + 56 + &lpass_tx_swr_clk { 57 + drive-strength = <2>; 58 + slew-rate = <1>; 59 + bias-disable; 60 + }; 61 + 62 + &lpass_tx_swr_clk_sleep { 63 + bias-pull-down; 64 + }; 65 + 66 + &lpass_tx_swr_data { 67 + drive-strength = <2>; 68 + slew-rate = <1>; 69 + bias-bus-hold; 70 + }; 71 + 8 72 &mi2s1_data0 { 9 73 drive-strength = <6>; 10 74 bias-disable;

-61

arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts

··· 155 155 * - If a pin is totally internal to Qcard then it gets Qcard name. 156 156 * - If a pin is not hooked up on Qcard, it gets no name. 157 157 */ 158 - &lpass_dmic01_clk { 159 - drive-strength = <8>; 160 - bias-disable; 161 - }; 162 - 163 - &lpass_dmic01_clk_sleep { 164 - drive-strength = <2>; 165 - }; 166 - 167 - &lpass_dmic01_data { 168 - bias-pull-down; 169 - }; 170 - 171 - &lpass_dmic23_clk { 172 - drive-strength = <8>; 173 - bias-disable; 174 - }; 175 - 176 - &lpass_dmic23_clk_sleep { 177 - drive-strength = <2>; 178 - }; 179 - 180 - &lpass_dmic23_data { 181 - bias-pull-down; 182 - }; 183 - 184 - &lpass_rx_swr_clk { 185 - drive-strength = <2>; 186 - slew-rate = <1>; 187 - bias-disable; 188 - }; 189 - 190 - &lpass_rx_swr_clk_sleep { 191 - bias-pull-down; 192 - }; 193 - 194 - &lpass_rx_swr_data { 195 - drive-strength = <2>; 196 - slew-rate = <1>; 197 - bias-bus-hold; 198 - }; 199 - 200 - &lpass_rx_swr_data_sleep { 201 - bias-pull-down; 202 - }; 203 - 204 - &lpass_tx_swr_clk { 205 - drive-strength = <2>; 206 - slew-rate = <1>; 207 - bias-disable; 208 - }; 209 - 210 - &lpass_tx_swr_clk_sleep { 211 - bias-pull-down; 212 - }; 213 - 214 - &lpass_tx_swr_data { 215 - drive-strength = <2>; 216 - slew-rate = <1>; 217 - bias-bus-hold; 218 - }; 219 158 220 159 &pm8350c_gpios { 221 160 gpio-line-names = "FLASH_STROBE_1", /* 1 */

-2

arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi

··· 435 435 pinctrl-names = "default"; 436 436 pinctrl-0 = <&dp_hot_plug_det>; 437 437 data-lanes = <0 1>; 438 - vdda-1p2-supply = <&vdd_a_usbssdp_0_1p2>; 439 - vdda-0p9-supply = <&vdd_a_usbssdp_0_core>; 440 438 }; 441 439 442 440 &mdss_mdp {

-3

arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi

··· 311 311 312 312 /* NOTE: Not all Qcards have eDP connector stuffed */ 313 313 &mdss_edp { 314 - vdda-0p9-supply = <&vdd_a_edp_0_0p9>; 315 - vdda-1p2-supply = <&vdd_a_edp_0_1p2>; 316 - 317 314 aux-bus { 318 315 edp_panel: panel { 319 316 compatible = "edp-panel";

+15 -19

arch/arm64/boot/dts/qcom/sc7280.dtsi

··· 3174 3174 assigned-clock-rates = <19200000>, <200000000>; 3175 3175 3176 3176 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3177 - <&pdc 13 IRQ_TYPE_EDGE_RISING>, 3178 - <&pdc 12 IRQ_TYPE_EDGE_RISING>; 3177 + <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3178 + <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3179 3179 interrupt-names = "hs_phy_irq", 3180 - "dm_hs_phy_irq", "dp_hs_phy_irq"; 3180 + "dp_hs_phy_irq", 3181 + "dm_hs_phy_irq"; 3181 3182 3182 3183 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3183 3184 ··· 3358 3357 assigned-clock-rates = <19200000>, <200000000>; 3359 3358 3360 3359 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3361 - <&pdc 17 IRQ_TYPE_EDGE_BOTH>, 3360 + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3362 3361 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3363 - <&pdc 14 IRQ_TYPE_LEVEL_HIGH>; 3362 + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3364 3363 interrupt-names = "hs_phy_irq", 3365 - "ss_phy_irq", 3364 + "dp_hs_phy_irq", 3366 3365 "dm_hs_phy_irq", 3367 - "dp_hs_phy_irq"; 3366 + "ss_phy_irq"; 3368 3367 3369 3368 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3370 3369 ··· 3717 3716 interrupt-parent = <&mdss>; 3718 3717 interrupts = <14>; 3719 3718 3720 - clocks = <&rpmhcc RPMH_CXO_CLK>, 3721 - <&gcc GCC_EDP_CLKREF_EN>, 3722 - <&dispcc DISP_CC_MDSS_AHB_CLK>, 3719 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3723 3720 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3724 3721 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3725 3722 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3726 3723 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3727 - clock-names = "core_xo", 3728 - "core_ref", 3729 - "core_iface", 3724 + clock-names = "core_iface", 3730 3725 "core_aux", 3731 3726 "ctrl_link", 3732 3727 "ctrl_link_iface", 3733 3728 "stream_pixel"; 3734 - #clock-cells = <1>; 3735 3729 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3736 3730 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3737 3731 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; ··· 3736 3740 3737 3741 operating-points-v2 = <&edp_opp_table>; 3738 3742 power-domains = <&rpmhpd SC7280_CX>; 3739 - 3740 - #address-cells = <1>; 3741 - #size-cells = <0>; 3742 3743 3743 3744 status = "disabled"; 3744 3745 ··· 3803 3810 mdss_dp: displayport-controller@ae90000 { 3804 3811 compatible = "qcom,sc7280-dp"; 3805 3812 3806 - reg = <0 0x0ae90000 0 0x1400>; 3813 + reg = <0 0xae90000 0 0x200>, 3814 + <0 0xae90200 0 0x200>, 3815 + <0 0xae90400 0 0xc00>, 3816 + <0 0xae91000 0 0x400>, 3817 + <0 0xae91400 0 0x400>; 3807 3818 3808 3819 interrupt-parent = <&mdss>; 3809 3820 interrupts = <12>; ··· 3822 3825 "ctrl_link", 3823 3826 "ctrl_link_iface", 3824 3827 "stream_pixel"; 3825 - #clock-cells = <1>; 3826 3828 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3827 3829 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3828 3830 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;

+24 -16

arch/arm64/boot/dts/qcom/sc8280xp.dtsi

··· 36 36 compatible = "operating-points-v2"; 37 37 opp-shared; 38 38 39 + opp-300000000 { 40 + opp-hz = /bits/ 64 <300000000>; 41 + }; 39 42 opp-403200000 { 40 43 opp-hz = /bits/ 64 <403200000>; 41 44 }; ··· 479 476 480 477 pmu { 481 478 compatible = "arm,armv8-pmuv3"; 482 - interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 479 + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 483 480 }; 484 481 485 482 psci { ··· 1279 1276 #size-cells = <2>; 1280 1277 ranges; 1281 1278 1282 - clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1283 - <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1279 + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1280 + <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1284 1281 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1285 - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1286 1282 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1283 + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1287 1284 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 1288 1285 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 1289 1286 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 1290 1287 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 1291 - clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", 1288 + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 1292 1289 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 1293 1290 1294 1291 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, ··· 1299 1296 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1300 1297 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1301 1298 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 1302 - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1303 - "dm_hs_phy_irq", "ss_phy_irq"; 1299 + interrupt-names = "pwr_event", 1300 + "dp_hs_phy_irq", 1301 + "dm_hs_phy_irq", 1302 + "ss_phy_irq"; 1304 1303 1305 1304 power-domains = <&gcc USB30_PRIM_GDSC>; 1306 1305 ··· 1331 1326 #size-cells = <2>; 1332 1327 ranges; 1333 1328 1334 - clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, 1335 - <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1329 + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1330 + <&gcc GCC_USB30_SEC_MASTER_CLK>, 1336 1331 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1337 - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1338 1332 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1333 + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1339 1334 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 1340 1335 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 1341 1336 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 1342 1337 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 1343 - clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", 1338 + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 1344 1339 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 1345 1340 1346 1341 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1347 1342 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1348 1343 assigned-clock-rates = <19200000>, <200000000>; 1349 1344 1350 - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1345 + interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 1351 1346 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 1352 1347 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 1353 - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 1354 - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1355 - "dm_hs_phy_irq", "ss_phy_irq"; 1348 + <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 1349 + interrupt-names = "pwr_event", 1350 + "dp_hs_phy_irq", 1351 + "dm_hs_phy_irq", 1352 + "ss_phy_irq"; 1356 1353 1357 1354 power-domains = <&gcc USB30_SEC_GDSC>; 1358 1355 ··· 1587 1580 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1588 1581 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1589 1582 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 1590 - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1591 1583 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1592 1584 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1593 1585 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, ··· 1597 1591 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1598 1592 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1599 1593 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1594 + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1600 1595 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1601 1596 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1602 1597 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, ··· 1672 1665 reg = <0x0 0x17c20000 0x0 0x1000>; 1673 1666 #address-cells = <1>; 1674 1667 #size-cells = <1>; 1668 + ranges = <0x0 0x0 0x0 0x20000000>; 1675 1669 1676 1670 frame@17c21000 { 1677 1671 frame-number = <0>;

+6

arch/arm64/boot/dts/qcom/sdm845-db845c.dts

··· 443 443 status = "okay"; 444 444 }; 445 445 446 + &gpi_dma1 { 447 + status = "okay"; 448 + }; 449 + 446 450 &gpu { 447 451 status = "okay"; 448 452 zap-shader { ··· 499 495 500 496 &i2c11 { 501 497 /* On Low speed expansion */ 498 + clock-frequency = <100000>; 502 499 label = "LS-I2C1"; 503 500 status = "okay"; 504 501 }; 505 502 506 503 &i2c14 { 507 504 /* On Low speed expansion */ 505 + clock-frequency = <100000>; 508 506 label = "LS-I2C0"; 509 507 status = "okay"; 510 508 };

+762

arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts

··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2020, Xilin Wu <strongtz@yeah.net> 4 + * Copyright (c) 2022, Molly Sophia <mollysophia379@gmail.com> 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 11 + #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 12 + #include <dt-bindings/input/linux-event-codes.h> 13 + #include <dt-bindings/sound/qcom,q6afe.h> 14 + #include <dt-bindings/sound/qcom,q6asm.h> 15 + #include "sdm845.dtsi" 16 + #include "pm8998.dtsi" 17 + #include "pmi8998.dtsi" 18 + #include "pm8005.dtsi" 19 + 20 + /* 21 + * Delete following upstream (sdm845.dtsi) reserved 22 + * memory mappings which are different in this device. 23 + */ 24 + /delete-node/ &rmtfs_mem; 25 + /delete-node/ &adsp_mem; 26 + /delete-node/ &wlan_msa_mem; 27 + /delete-node/ &mpss_region; 28 + /delete-node/ &venus_mem; 29 + /delete-node/ &cdsp_mem; 30 + /delete-node/ &mba_region; 31 + /delete-node/ &slpi_mem; 32 + /delete-node/ &spss_mem; 33 + 34 + / { 35 + model = "Xiaomi Mi MIX 2S"; 36 + compatible = "xiaomi,polaris", "qcom,sdm845"; 37 + chassis-type = "handset"; 38 + 39 + /* required for bootloader to select correct board */ 40 + qcom,msm-id = <0x141 0x20001>; 41 + qcom,board-id = <0x2a 0x0>; 42 + 43 + aliases { 44 + serial0 = &uart9; 45 + serial1 = &uart6; 46 + }; 47 + 48 + gpio-keys { 49 + compatible = "gpio-keys"; 50 + autorepeat; 51 + 52 + pinctrl-names = "default"; 53 + pinctrl-0 = <&volume_up_gpio>; 54 + 55 + key-vol-up { 56 + label = "Volume Up"; 57 + linux,code = <KEY_VOLUMEUP>; 58 + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; 59 + debounce-interval = <15>; 60 + }; 61 + }; 62 + 63 + reserved-memory { 64 + adsp_mem: memory@8c500000 { 65 + reg = <0 0x8c500000 0 0x1e00000>; 66 + no-map; 67 + }; 68 + 69 + wlan_msa_mem: memory@8e300000 { 70 + reg = <0 0x8e300000 0 0x100000>; 71 + no-map; 72 + }; 73 + 74 + mpss_region: memory@8e400000 { 75 + reg = <0 0x8e400000 0 0x7800000>; 76 + no-map; 77 + }; 78 + 79 + venus_mem: memory@95c00000 { 80 + reg = <0 0x95c00000 0 0x500000>; 81 + no-map; 82 + }; 83 + 84 + cdsp_mem: memory@96100000 { 85 + reg = <0 0x96100000 0 0x800000>; 86 + no-map; 87 + }; 88 + 89 + mba_region: memory@96900000 { 90 + reg = <0 0x96900000 0 0x200000>; 91 + no-map; 92 + }; 93 + 94 + slpi_mem: memory@96b00000 { 95 + reg = <0 0x96b00000 0 0x1400000>; 96 + no-map; 97 + }; 98 + 99 + spss_mem: memory@97f00000 { 100 + reg = <0 0x97f00000 0 0x100000>; 101 + no-map; 102 + }; 103 + 104 + rmtfs_mem: memory@f6301000 { 105 + compatible = "qcom,rmtfs-mem"; 106 + reg = <0 0xf6301000 0 0x200000>; 107 + no-map; 108 + 109 + qcom,client-id = <1>; 110 + qcom,vmid = <15>; 111 + }; 112 + }; 113 + 114 + battery: battery { 115 + compatible = "simple-battery"; 116 + 117 + charge-full-design-microamp-hours = <3400000>; 118 + voltage-min-design-microvolt = <3400000>; 119 + voltage-max-design-microvolt = <4400000>; 120 + }; 121 + 122 + vreg_tp_vddio: vreg-tp-vddio { 123 + compatible = "regulator-fixed"; 124 + regulator-name = "vreg_tp_vddio"; 125 + 126 + regulator-min-microvolt = <1800000>; 127 + regulator-max-microvolt = <1800000>; 128 + 129 + gpio = <&tlmm 23 0>; 130 + regulator-always-on; 131 + regulator-boot-on; 132 + enable-active-high; 133 + }; 134 + 135 + vreg_s4a_1p8: vreg-s4a-1p8 { 136 + compatible = "regulator-fixed"; 137 + regulator-name = "vreg_s4a_1p8"; 138 + 139 + regulator-min-microvolt = <1800000>; 140 + regulator-max-microvolt = <1800000>; 141 + regulator-always-on; 142 + }; 143 + }; 144 + 145 + &apps_rsc { 146 + pm8998-rpmh-regulators { 147 + compatible = "qcom,pm8998-rpmh-regulators"; 148 + qcom,pmic-id = "a"; 149 + 150 + vreg_s2a_1p1: smps2 { 151 + regulator-min-microvolt = <1100000>; 152 + regulator-max-microvolt = <1100000>; 153 + }; 154 + 155 + vreg_s3a_1p35: smps3 { 156 + regulator-min-microvolt = <1352000>; 157 + regulator-max-microvolt = <1352000>; 158 + }; 159 + 160 + vreg_s5a_2p04: smps5 { 161 + regulator-min-microvolt = <1904000>; 162 + regulator-max-microvolt = <2040000>; 163 + }; 164 + 165 + vreg_s7a_1p025: smps7 { 166 + regulator-min-microvolt = <900000>; 167 + regulator-max-microvolt = <1028000>; 168 + }; 169 + 170 + vdda_mipi_dsi0_pll: 171 + vdda_ufs1_core: 172 + vreg_l1a_0p875: ldo1 { 173 + regulator-min-microvolt = <880000>; 174 + regulator-max-microvolt = <880000>; 175 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 176 + }; 177 + 178 + vreg_l2a_1p2: ldo2 { 179 + regulator-min-microvolt = <1200000>; 180 + regulator-max-microvolt = <1200000>; 181 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 182 + regulator-always-on; 183 + }; 184 + 185 + vreg_l3a_1p0: ldo3 { 186 + regulator-min-microvolt = <1000000>; 187 + regulator-max-microvolt = <1000000>; 188 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 189 + }; 190 + 191 + vreg_l5a_0p8: ldo5 { 192 + regulator-min-microvolt = <800000>; 193 + regulator-max-microvolt = <800000>; 194 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 195 + }; 196 + 197 + vreg_l6a_1p8: ldo6 { 198 + regulator-min-microvolt = <1856000>; 199 + regulator-max-microvolt = <1856000>; 200 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 201 + }; 202 + 203 + vreg_l7a_1p8: ldo7 { 204 + regulator-min-microvolt = <1800000>; 205 + regulator-max-microvolt = <1800000>; 206 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 207 + }; 208 + 209 + vreg_l8a_1p2: ldo8 { 210 + regulator-min-microvolt = <1200000>; 211 + regulator-max-microvolt = <1248000>; 212 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 213 + }; 214 + 215 + vreg_l9a_1p8: ldo9 { 216 + regulator-min-microvolt = <1704000>; 217 + regulator-max-microvolt = <2928000>; 218 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 219 + }; 220 + 221 + vreg_l10a_2p95: ldo10 { 222 + regulator-min-microvolt = <1704000>; 223 + regulator-max-microvolt = <2928000>; 224 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 225 + }; 226 + 227 + vreg_l11a_1p05: ldo11 { 228 + regulator-min-microvolt = <1000000>; 229 + regulator-max-microvolt = <1048000>; 230 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 231 + }; 232 + 233 + vreg_l12a_1p8: ldo12 { 234 + regulator-min-microvolt = <1800000>; 235 + regulator-max-microvolt = <1800000>; 236 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 237 + }; 238 + 239 + vreg_l13a_2p95: ldo13 { 240 + regulator-min-microvolt = <1800000>; 241 + regulator-max-microvolt = <2960000>; 242 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 243 + }; 244 + 245 + vreg_l14a_1p8: ldo14 { 246 + regulator-min-microvolt = <1800000>; 247 + regulator-max-microvolt = <1880000>; 248 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 249 + regulator-always-on; 250 + }; 251 + 252 + vreg_l15a_1p8: ldo15 { 253 + regulator-min-microvolt = <1800000>; 254 + regulator-max-microvolt = <1800000>; 255 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 256 + }; 257 + 258 + vreg_l16a_2p7: ldo16 { 259 + regulator-min-microvolt = <2704000>; 260 + regulator-max-microvolt = <2704000>; 261 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 262 + }; 263 + 264 + vreg_l17a_1p3: ldo17 { 265 + regulator-min-microvolt = <1304000>; 266 + regulator-max-microvolt = <1304000>; 267 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 268 + regulator-always-on; 269 + }; 270 + 271 + vreg_l18a_2p9: ldo18 { 272 + regulator-min-microvolt = <2704000>; 273 + regulator-max-microvolt = <2960000>; 274 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 275 + }; 276 + 277 + vreg_l19a_3p1: ldo19 { 278 + regulator-min-microvolt = <2856000>; 279 + regulator-max-microvolt = <3104000>; 280 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 281 + }; 282 + 283 + vreg_l20a_2p95: ldo20 { 284 + regulator-min-microvolt = <2704000>; 285 + regulator-max-microvolt = <2960000>; 286 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 287 + }; 288 + 289 + vreg_l21a_2p95: ldo21 { 290 + regulator-min-microvolt = <2704000>; 291 + regulator-max-microvolt = <2960000>; 292 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 293 + }; 294 + 295 + vreg_l22a_3p3: ldo22 { 296 + regulator-min-microvolt = <2864000>; 297 + regulator-max-microvolt = <3312000>; 298 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 299 + }; 300 + 301 + vreg_l23a_3p3: ldo23 { 302 + regulator-min-microvolt = <3000000>; 303 + regulator-max-microvolt = <3312000>; 304 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 305 + }; 306 + 307 + vreg_l24a_3p075: ldo24 { 308 + regulator-min-microvolt = <3088000>; 309 + regulator-max-microvolt = <3088000>; 310 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 311 + }; 312 + 313 + vreg_l25a_3p3: ldo25 { 314 + regulator-min-microvolt = <3000000>; 315 + regulator-max-microvolt = <3312000>; 316 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 317 + regulator-always-on; 318 + }; 319 + 320 + vdda_mipi_dsi0_1p2: 321 + vdda_ufs1_1p2: 322 + vreg_l26a_1p2: ldo26 { 323 + regulator-min-microvolt = <1200000>; 324 + regulator-max-microvolt = <1200000>; 325 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 326 + }; 327 + 328 + vreg_l28a_3p0: ldo28 { 329 + regulator-min-microvolt = <2856000>; 330 + regulator-max-microvolt = <3008000>; 331 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 332 + regulator-always-on; 333 + }; 334 + 335 + vreg_lvs1a_1p8: lvs1 { 336 + regulator-min-microvolt = <1800000>; 337 + regulator-max-microvolt = <1800000>; 338 + }; 339 + 340 + vreg_lvs2a_1p8: lvs2 { 341 + regulator-min-microvolt = <1800000>; 342 + regulator-max-microvolt = <1800000>; 343 + }; 344 + }; 345 + 346 + pmi8998-rpmh-regulators { 347 + compatible = "qcom,pmi8998-rpmh-regulators"; 348 + qcom,pmic-id = "b"; 349 + 350 + vreg_bob: bob { 351 + regulator-min-microvolt = <3312000>; 352 + regulator-max-microvolt = <3600000>; 353 + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; 354 + regulator-allow-bypass; 355 + }; 356 + }; 357 + 358 + pm8005-rpmh-regulators { 359 + compatible = "qcom,pm8005-rpmh-regulators"; 360 + qcom,pmic-id = "c"; 361 + 362 + vreg_smp3c_0p6: smps3 { 363 + regulator-min-microvolt = <600000>; 364 + regulator-max-microvolt = <600000>; 365 + regulator-always-on; 366 + }; 367 + }; 368 + }; 369 + 370 + &cdsp_pas { 371 + firmware-name = "qcom/sdm845/polaris/cdsp.mbn"; 372 + status = "okay"; 373 + }; 374 + 375 + &dsi0 { 376 + vdda-supply = <&vdda_mipi_dsi0_1p2>; 377 + status = "okay"; 378 + 379 + display_panel: panel@0 { 380 + compatible = "jdi,fhd-nt35596s"; 381 + #address-cells = <1>; 382 + #size-cells = <0>; 383 + reg = <0>; 384 + 385 + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; 386 + vddio-supply = <&vreg_l14a_1p8>; 387 + backlight = <&pmi8998_wled>; 388 + vddpos-supply = <&lab>; 389 + vddneg-supply = <&ibb>; 390 + 391 + pinctrl-names = "default", "sleep"; 392 + pinctrl-0 = <&sde_dsi_active>; 393 + pinctrl-1 = <&sde_dsi_suspend>; 394 + 395 + port { 396 + panel_in: endpoint { 397 + remote-endpoint = <&dsi0_out>; 398 + }; 399 + }; 400 + }; 401 + }; 402 + 403 + &dsi0_out { 404 + remote-endpoint = <&panel_in>; 405 + data-lanes = <0 1 2 3>; 406 + }; 407 + 408 + &dsi0_phy { 409 + vdds-supply = <&vdda_mipi_dsi0_pll>; 410 + status = "okay"; 411 + }; 412 + 413 + &gcc { 414 + protected-clocks = <GCC_QSPI_CORE_CLK>, 415 + <GCC_QSPI_CORE_CLK_SRC>, 416 + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 417 + <GCC_LPASS_Q6_AXI_CLK>, 418 + <GCC_LPASS_SWAY_CLK>; 419 + }; 420 + 421 + &gmu { 422 + status = "okay"; 423 + }; 424 + 425 + &gpi_dma0 { 426 + status = "okay"; 427 + }; 428 + 429 + &gpi_dma1 { 430 + status = "okay"; 431 + }; 432 + 433 + &gpu { 434 + status = "okay"; 435 + 436 + zap-shader { 437 + memory-region = <&gpu_mem>; 438 + firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; 439 + }; 440 + }; 441 + 442 + &ibb { 443 + regulator-min-microvolt = <4600000>; 444 + regulator-max-microvolt = <6000000>; 445 + regulator-over-current-protection; 446 + regulator-pull-down; 447 + regulator-soft-start; 448 + qcom,discharge-resistor-kohms = <300>; 449 + }; 450 + 451 + &ipa { 452 + memory-region = <&ipa_fw_mem>; 453 + firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; 454 + status = "okay"; 455 + }; 456 + 457 + &i2c14 { 458 + clock-frequency = <400000>; 459 + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 460 + <&gpi_dma1 1 6 QCOM_GPI_I2C>; 461 + dma-names = "tx", "rx"; 462 + status = "okay"; 463 + 464 + touchscreen@20 { 465 + compatible = "syna,rmi4-i2c"; 466 + reg = <0x20>; 467 + #address-cells = <1>; 468 + #size-cells = <0>; 469 + interrupts-extended = <&tlmm 125 0x2008>; 470 + 471 + pinctrl-names = "default", "sleep"; 472 + pinctrl-0 = <&ts_int_default &ts_reset_default>; 473 + pinctrl-1 = <&ts_int_sleep &ts_reset_sleep>; 474 + 475 + vdd-supply = <&vreg_l28a_3p0>; 476 + vio-supply = <&vreg_tp_vddio>; 477 + 478 + syna,startup-delay-ms = <0xc8>; 479 + syna,reset-delay-ms = <0xc8>; 480 + 481 + rmi4-f01@1 { 482 + syna,nosleep-mode = <0x1>; 483 + reg = <0x1>; 484 + }; 485 + 486 + rmi4-f12@12 { 487 + syna,rezero-wait-ms = <0xc8>; 488 + syna,clip-x-high = <0x438>; 489 + syna,clip-y-high = <0x870>; 490 + syna,sensor-type = <0x1>; 491 + syna,clip-x-low = <0x0>; 492 + syna,clip-y-low = <0x0>; 493 + }; 494 + }; 495 + }; 496 + 497 + &lab { 498 + regulator-min-microvolt = <4600000>; 499 + regulator-max-microvolt = <6000000>; 500 + regulator-soft-start; 501 + regulator-pull-down; 502 + }; 503 + 504 + &mdss { 505 + status = "okay"; 506 + }; 507 + 508 + &mss_pil { 509 + firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; 510 + status = "okay"; 511 + }; 512 + 513 + &pmi8998_wled { 514 + qcom,current-limit-microamp = <20000>; 515 + qcom,current-boost-limit = <970>; 516 + qcom,ovp-millivolt = <19600>; 517 + qcom,switching-freq = <600>; 518 + qcom,num-strings = <4>; 519 + qcom,cabc; 520 + 521 + status = "okay"; 522 + }; 523 + 524 + &pm8998_gpio { 525 + volume_up_gpio: pm8998_gpio6 { 526 + pinconf { 527 + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 528 + function = "normal"; 529 + pins = "gpio6"; 530 + input-enable; 531 + bias-pull-up; 532 + }; 533 + }; 534 + }; 535 + 536 + &pm8998_pon { 537 + resin { 538 + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; 539 + compatible = "qcom,pm8941-resin"; 540 + linux,code = <KEY_VOLUMEDOWN>; 541 + debounce = <15625>; 542 + bias-pull-up; 543 + }; 544 + }; 545 + 546 + &q6afedai { 547 + qi2s@22 { 548 + reg = <22>; 549 + qcom,sd-lines = <0>; 550 + }; 551 + }; 552 + 553 + &q6asmdai { 554 + dai@0 { 555 + reg = <0>; 556 + }; 557 + 558 + dai@1 { 559 + reg = <1>; 560 + }; 561 + 562 + dai@2 { 563 + reg = <2>; 564 + }; 565 + }; 566 + 567 + &qupv3_id_0 { 568 + status = "okay"; 569 + }; 570 + 571 + &qupv3_id_1 { 572 + status = "okay"; 573 + }; 574 + 575 + &qup_i2c14_default { 576 + pinconf { 577 + pins = "gpio33", "gpio34"; 578 + drive-strength = <2>; 579 + bias-disable; 580 + }; 581 + }; 582 + 583 + &tlmm { 584 + gpio-reserved-ranges = <0 4>, <81 4>; 585 + 586 + ts_reset_default: ts-reset-default { 587 + pins = "gpio99"; 588 + function = "gpio"; 589 + drive-strength = <16>; 590 + output-high; 591 + }; 592 + 593 + ts_int_default: ts-int-default { 594 + pins = "gpio125"; 595 + function = "gpio"; 596 + bias-pull-down; 597 + drive-strength = <16>; 598 + input-enable; 599 + }; 600 + 601 + ts_reset_sleep: ts-reset-sleep { 602 + pins = "gpio99"; 603 + function = "gpio"; 604 + bias-disable; 605 + drive-strength = <2>; 606 + }; 607 + 608 + ts_int_sleep: ts-int-sleep { 609 + pins = "gpio125"; 610 + function = "gpio"; 611 + bias-pull-down; 612 + drive-strength = <2>; 613 + input-enable; 614 + }; 615 + 616 + sde_dsi_active: sde-dsi-active { 617 + pins = "gpio6", "gpio10"; 618 + function = "gpio"; 619 + drive-strength = <8>; 620 + bias-disable = <0>; 621 + }; 622 + 623 + sde_dsi_suspend: sde-dsi-suspend { 624 + pins = "gpio6", "gpio10"; 625 + function = "gpio"; 626 + drive-strength = <2>; 627 + bias-pull-down; 628 + }; 629 + 630 + wcd_intr_default: wcd-intr-default { 631 + pins = "goui54"; 632 + function = "gpio"; 633 + input-enable; 634 + bias-pull-down; 635 + drive-strength = <2>; 636 + }; 637 + }; 638 + 639 + &uart6 { 640 + status = "okay"; 641 + 642 + bluetooth { 643 + compatible = "qcom,wcn3990-bt"; 644 + 645 + /* This path is relative to the qca/ subdir under lib/firmware. */ 646 + firmware-name = "polaris/crnv21.bin"; 647 + 648 + vddio-supply = <&vreg_s4a_1p8>; 649 + vddxo-supply = <&vreg_l7a_1p8>; 650 + vddrf-supply = <&vreg_l17a_1p3>; 651 + vddch0-supply = <&vreg_l25a_3p3>; 652 + max-speed = <3200000>; 653 + }; 654 + }; 655 + 656 + &usb_1 { 657 + /* We'll use this as USB 2.0 only */ 658 + qcom,select-utmi-as-pipe-clk; 659 + status = "okay"; 660 + }; 661 + 662 + &usb_1_dwc3 { 663 + dr_mode = "peripheral"; 664 + 665 + /* Fastest mode for USB 2 */ 666 + maximum-speed = "high-speed"; 667 + 668 + /* Remove USB3 phy */ 669 + phys = <&usb_1_hsphy>; 670 + phy-names = "usb2-phy"; 671 + }; 672 + 673 + &usb_1_hsphy { 674 + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; 675 + vdda-pll-supply = <&vreg_l12a_1p8>; 676 + vdd-supply = <&vreg_l1a_0p875>; 677 + 678 + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 679 + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 680 + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 681 + qcom,imp-res-offset-value = <8>; 682 + 683 + status = "okay"; 684 + }; 685 + 686 + &usb_1_qmpphy { 687 + vdda-pll-supply = <&vreg_l1a_0p875>; 688 + vdda-phy-supply = <&vreg_l26a_1p2>; 689 + status = "okay"; 690 + }; 691 + 692 + &ufs_mem_hc { 693 + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 694 + vcc-supply = <&vreg_l20a_2p95>; 695 + vcc-max-microamp = <800000>; 696 + status = "okay"; 697 + }; 698 + 699 + &ufs_mem_phy { 700 + vdda-phy-supply = <&vdda_ufs1_core>; 701 + vdda-pll-supply = <&vdda_ufs1_1p2>; 702 + status = "okay"; 703 + }; 704 + 705 + &venus { 706 + firmware-name = "qcom/sdm845/polaris/venus.mbn"; 707 + status = "okay"; 708 + }; 709 + 710 + &wcd9340 { 711 + pinctrl-0 = <&wcd_intr_default>; 712 + pinctrl-names = "default"; 713 + clock-names = "extclk"; 714 + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 715 + reset-gpios = <&tlmm 64 0>; 716 + vdd-buck-sido-supply = <&vreg_s4a_1p8>; 717 + vdd-buck-supply = <&vreg_s4a_1p8>; 718 + vdd-tx-supply = <&vreg_s4a_1p8>; 719 + vdd-rx-supply = <&vreg_s4a_1p8>; 720 + vdd-io-supply = <&vreg_s4a_1p8>; 721 + 722 + qcom,micbias1-microvolt = <2700000>; 723 + qcom,micbias2-microvolt = <1800000>; 724 + qcom,micbias3-microvolt = <2700000>; 725 + qcom,micbias4-microvolt = <2700000>; 726 + }; 727 + 728 + &wifi { 729 + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; 730 + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 731 + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 732 + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 733 + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; 734 + 735 + qcom,snoc-host-cap-skip-quirk; 736 + status = "okay"; 737 + }; 738 + 739 + /* PINCTRL - additions to nodes defined in sdm845.dtsi */ 740 + 741 + &qup_uart6_default { 742 + pinmux { 743 + pins = "gpio45", "gpio46", "gpio47", "gpio48"; 744 + function = "qup6"; 745 + }; 746 + 747 + cts { 748 + pins = "gpio45"; 749 + bias-disable; 750 + }; 751 + 752 + rts-tx { 753 + pins = "gpio46", "gpio47"; 754 + drive-strength = <2>; 755 + bias-disable; 756 + }; 757 + 758 + rx { 759 + pins = "gpio48"; 760 + bias-pull-up; 761 + }; 762 + };

+91 -1

arch/arm64/boot/dts/qcom/sdm845.dtsi

··· 1208 1208 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1209 1209 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1210 1210 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1211 + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1212 + <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1213 + dma-names = "tx", "rx"; 1211 1214 status = "disabled"; 1212 1215 }; 1213 1216 ··· 1265 1262 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1266 1263 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1267 1264 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1265 + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1266 + <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1267 + dma-names = "tx", "rx"; 1268 1268 status = "disabled"; 1269 1269 }; 1270 1270 ··· 1284 1278 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1285 1279 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1286 1280 interconnect-names = "qup-core", "qup-config"; 1281 + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1282 + <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1283 + dma-names = "tx", "rx"; 1287 1284 status = "disabled"; 1288 1285 }; 1289 1286 ··· 1322 1313 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1323 1314 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1324 1315 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1316 + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1317 + <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1318 + dma-names = "tx", "rx"; 1325 1319 status = "disabled"; 1326 1320 }; 1327 1321 ··· 1341 1329 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1342 1330 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1343 1331 interconnect-names = "qup-core", "qup-config"; 1332 + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1333 + <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1334 + dma-names = "tx", "rx"; 1344 1335 status = "disabled"; 1345 1336 }; 1346 1337 ··· 1379 1364 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1380 1365 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1381 1366 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1367 + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1368 + <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1369 + dma-names = "tx", "rx"; 1382 1370 status = "disabled"; 1383 1371 }; 1384 1372 ··· 1398 1380 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1399 1381 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1400 1382 interconnect-names = "qup-core", "qup-config"; 1383 + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1384 + <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1385 + dma-names = "tx", "rx"; 1401 1386 status = "disabled"; 1402 1387 }; 1403 1388 ··· 1436 1415 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1437 1416 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1438 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1419 + <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1420 + dma-names = "tx", "rx"; 1439 1421 status = "disabled"; 1440 1422 }; 1441 1423 ··· 1455 1431 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1456 1432 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1457 1433 interconnect-names = "qup-core", "qup-config"; 1434 + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1435 + <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1436 + dma-names = "tx", "rx"; 1458 1437 status = "disabled"; 1459 1438 }; 1460 1439 ··· 1493 1466 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1494 1467 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1495 1468 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1469 + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1470 + <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1471 + dma-names = "tx", "rx"; 1496 1472 status = "disabled"; 1497 1473 }; 1498 1474 ··· 1512 1482 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1513 1483 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1514 1484 interconnect-names = "qup-core", "qup-config"; 1485 + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1486 + <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1487 + dma-names = "tx", "rx"; 1515 1488 status = "disabled"; 1516 1489 }; 1517 1490 ··· 1550 1517 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1551 1518 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1552 1519 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1520 + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1521 + <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1522 + dma-names = "tx", "rx"; 1553 1523 status = "disabled"; 1554 1524 }; 1555 1525 ··· 1569 1533 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1570 1534 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1571 1535 interconnect-names = "qup-core", "qup-config"; 1536 + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1537 + <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1538 + dma-names = "tx", "rx"; 1572 1539 status = "disabled"; 1573 1540 }; 1574 1541 ··· 1619 1580 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1620 1581 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1621 1582 interconnect-names = "qup-core", "qup-config"; 1583 + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1584 + <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1585 + dma-names = "tx", "rx"; 1622 1586 status = "disabled"; 1623 1587 }; 1624 1588 ··· 1695 1653 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1696 1654 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1697 1655 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1656 + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1657 + <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1658 + dma-names = "tx", "rx"; 1698 1659 status = "disabled"; 1699 1660 }; 1700 1661 ··· 1714 1669 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1715 1670 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1716 1671 interconnect-names = "qup-core", "qup-config"; 1672 + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1673 + <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1674 + dma-names = "tx", "rx"; 1717 1675 status = "disabled"; 1718 1676 }; 1719 1677 ··· 1752 1704 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1753 1705 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1754 1706 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1707 + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1708 + <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1709 + dma-names = "tx", "rx"; 1755 1710 status = "disabled"; 1756 1711 }; 1757 1712 ··· 1771 1720 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1772 1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1773 1722 interconnect-names = "qup-core", "qup-config"; 1723 + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1724 + <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1725 + dma-names = "tx", "rx"; 1774 1726 status = "disabled"; 1775 1727 }; 1776 1728 ··· 1809 1755 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1810 1756 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1811 1757 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1758 + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1759 + <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1760 + dma-names = "tx", "rx"; 1812 1761 status = "disabled"; 1813 1762 }; 1814 1763 ··· 1828 1771 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1829 1772 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1830 1773 interconnect-names = "qup-core", "qup-config"; 1774 + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1775 + <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1776 + dma-names = "tx", "rx"; 1831 1777 status = "disabled"; 1832 1778 }; 1833 1779 ··· 1866 1806 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1867 1807 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1868 1808 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1809 + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1810 + <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1811 + dma-names = "tx", "rx"; 1869 1812 status = "disabled"; 1870 1813 }; 1871 1814 ··· 1885 1822 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1886 1823 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1887 1824 interconnect-names = "qup-core", "qup-config"; 1825 + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1826 + <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1827 + dma-names = "tx", "rx"; 1888 1828 status = "disabled"; 1889 1829 }; 1890 1830 ··· 1923 1857 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1924 1858 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1925 1859 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1860 + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1861 + <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1862 + dma-names = "tx", "rx"; 1926 1863 status = "disabled"; 1927 1864 }; 1928 1865 ··· 1942 1873 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1943 1874 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1944 1875 interconnect-names = "qup-core", "qup-config"; 1876 + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1877 + <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1878 + dma-names = "tx", "rx"; 1945 1879 status = "disabled"; 1946 1880 }; 1947 1881 ··· 1980 1908 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1981 1909 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1982 1910 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1911 + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1912 + <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1913 + dma-names = "tx", "rx"; 1983 1914 status = "disabled"; 1984 1915 }; 1985 1916 ··· 1999 1924 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2000 1925 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2001 1926 interconnect-names = "qup-core", "qup-config"; 1927 + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1928 + <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1929 + dma-names = "tx", "rx"; 2002 1930 status = "disabled"; 2003 1931 }; 2004 1932 ··· 2037 1959 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2038 1960 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2039 1961 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1962 + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1963 + <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1964 + dma-names = "tx", "rx"; 2040 1965 status = "disabled"; 2041 1966 }; 2042 1967 ··· 2056 1975 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2057 1976 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2058 1977 interconnect-names = "qup-core", "qup-config"; 1978 + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1979 + <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1980 + dma-names = "tx", "rx"; 2059 1981 status = "disabled"; 2060 1982 }; 2061 1983 ··· 2095 2011 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2096 2012 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2097 2013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2014 + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2015 + <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2016 + dma-names = "tx", "rx"; 2098 2017 }; 2099 2018 2100 2019 spi15: spi@a9c000 { ··· 2113 2026 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2114 2027 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2115 2028 interconnect-names = "qup-core", "qup-config"; 2029 + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2030 + <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2031 + dma-names = "tx", "rx"; 2116 2032 status = "disabled"; 2117 2033 }; 2118 2034 ··· 4419 4329 #size-cells = <2>; 4420 4330 ranges; 4421 4331 4422 - mdss_mdp: mdp@ae01000 { 4332 + mdss_mdp: display-controller@ae01000 { 4423 4333 compatible = "qcom,sdm845-dpu"; 4424 4334 reg = <0 0x0ae01000 0 0x8f000>, 4425 4335 <0 0x0aeb0000 0 0x2008>;

-1

arch/arm64/boot/dts/qcom/sdm850.dtsi

··· 16 16 cpu4_opp34: opp-2956800000 { 17 17 opp-hz = /bits/ 64 <2956800000>; 18 18 opp-peak-kBps = <7216000 25497600>; 19 - turbo-mode; 20 19 }; 21 20 };

+2 -2

arch/arm64/boot/dts/qcom/sm6350.dtsi

··· 489 489 clock-names = "iface", "core", "xo"; 490 490 qcom,dll-config = <0x000f642c>; 491 491 qcom,ddr-config = <0x80040868>; 492 - power-domains = <&rpmhpd 0>; 492 + power-domains = <&rpmhpd SM6350_CX>; 493 493 operating-points-v2 = <&sdhc1_opp_table>; 494 494 bus-width = <8>; 495 495 non-removable; ··· 935 935 clock-names = "iface", "core", "xo"; 936 936 qcom,dll-config = <0x0007642c>; 937 937 qcom,ddr-config = <0x80040868>; 938 - power-domains = <&rpmhpd 0>; 938 + power-domains = <&rpmhpd SM6350_CX>; 939 939 operating-points-v2 = <&sdhc2_opp_table>; 940 940 bus-width = <4>; 941 941

+13 -9

arch/arm64/boot/dts/qcom/sm8250.dtsi

··· 3018 3018 assigned-clock-rates = <19200000>, <200000000>; 3019 3019 3020 3020 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3021 - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3021 + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3022 3022 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3023 - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3024 - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3025 - "dm_hs_phy_irq", "ss_phy_irq"; 3023 + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3024 + interrupt-names = "hs_phy_irq", 3025 + "ss_phy_irq", 3026 + "dm_hs_phy_irq", 3027 + "dp_hs_phy_irq"; 3026 3028 3027 3029 power-domains = <&gcc USB30_PRIM_GDSC>; 3028 3030 ··· 3075 3073 assigned-clock-rates = <19200000>, <200000000>; 3076 3074 3077 3075 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3078 - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3076 + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3079 3077 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3080 - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 3081 - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3082 - "dm_hs_phy_irq", "ss_phy_irq"; 3078 + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3079 + interrupt-names = "hs_phy_irq", 3080 + "ss_phy_irq", 3081 + "dm_hs_phy_irq", 3082 + "dp_hs_phy_irq"; 3083 3083 3084 3084 power-domains = <&gcc USB30_SEC_GDSC>; 3085 3085 ··· 3454 3450 #size-cells = <2>; 3455 3451 ranges; 3456 3452 3457 - mdss_mdp: mdp@ae01000 { 3453 + mdss_mdp: display-controller@ae01000 { 3458 3454 compatible = "qcom,sm8250-dpu"; 3459 3455 reg = <0 0x0ae01000 0 0x8f000>, 3460 3456 <0 0x0aeb0000 0 0x2008>;

+12 -8

arch/arm64/boot/dts/qcom/sm8350.dtsi

··· 2461 2461 assigned-clock-rates = <19200000>, <200000000>; 2462 2462 2463 2463 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2464 - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2464 + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2465 2465 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2466 - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2467 - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2468 - "dm_hs_phy_irq", "ss_phy_irq"; 2466 + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2467 + interrupt-names = "hs_phy_irq", 2468 + "ss_phy_irq", 2469 + "dm_hs_phy_irq", 2470 + "dp_hs_phy_irq"; 2469 2471 2470 2472 power-domains = <&gcc USB30_PRIM_GDSC>; 2471 2473 ··· 2511 2509 assigned-clock-rates = <19200000>, <200000000>; 2512 2510 2513 2511 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2514 - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2512 + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2515 2513 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2516 - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2517 - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2518 - "dm_hs_phy_irq", "ss_phy_irq"; 2514 + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2515 + interrupt-names = "hs_phy_irq", 2516 + "ss_phy_irq", 2517 + "dm_hs_phy_irq", 2518 + "dp_hs_phy_irq"; 2519 2519 2520 2520 power-domains = <&gcc USB30_SEC_GDSC>; 2521 2521