Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] MTX1: clear PCI errors
[MIPS] MTX1: add idsel cardbus ressources
[MIPS] MTX1: remove unneeded settings
[MIPS] dma_sync_sg_for_cpu is a no-op except for non-coherent R10000s.
[MIPS] Cobalt: update reserved resources
[MIPS] SN: PCI fixup needs to include <irq.h>.
[MIPS] DMA: Fix a bunch of warnings due to missing inline keywords.
[MIPS] RM: It should be #ifdef CONFIG_FOO not #if CONFIG_FOO ...
[MIPS] Fix and cleanup the mess that a dozen prom_printf variants are.
[MIPS] DEC: Remove redeclarations of mips_machgroup and mips_machtype.
[MIPS] No need to write c0_compare in plat_timer_setup
[MIPS] Convert to RTC-class ds1742 driver
[MIPS] Oprofile: Add missing break statements.
[MIPS] jmr3927: build fix
[MIPS] SNI: Fix mc146818_decode_year
[MIPS] Replace sys32_timer_create with the generic compat_sys_timer_create.
[MIPS] Replace sys32_socketcall with the generic compat_sys_socketcall.
[MIPS] N32 waitid is the same as o32.

+430 -1022
+28 -7
arch/mips/Kconfig
··· 176 bool "DECstations" 177 select BOOT_ELF32 178 select DMA_NONCOHERENT 179 - select EARLY_PRINTK 180 select IRQ_CPU 181 select SYS_HAS_CPU_R3000 182 select SYS_HAS_CPU_R4X00 ··· 242 config LASAT 243 bool "LASAT Networks platforms" 244 select DMA_NONCOHERENT 245 select HW_HAS_PCI 246 select MIPS_GT64120 247 select MIPS_NILE4 ··· 257 bool "MIPS Atlas board" 258 select BOOT_ELF32 259 select DMA_NONCOHERENT 260 select IRQ_CPU 261 select HW_HAS_PCI 262 select MIPS_BOARDS_GEN ··· 303 select SYS_HAS_CPU_MIPS64_R1 304 select SYS_HAS_CPU_NEVADA 305 select SYS_HAS_CPU_RM7000 306 select SYS_SUPPORTS_32BIT_KERNEL 307 select SYS_SUPPORTS_64BIT_KERNEL 308 select SYS_SUPPORTS_BIG_ENDIAN ··· 319 depends on EXPERIMENTAL 320 select IRQ_CPU 321 select DMA_NONCOHERENT 322 select MIPS_BOARDS_GEN 323 select SYS_HAS_CPU_MIPS32_R1 324 select SYS_HAS_CPU_MIPS32_R2 ··· 357 config MIPS_SIM 358 bool 'MIPS simulator (MIPSsim)' 359 select DMA_NONCOHERENT 360 select IRQ_CPU 361 select SYS_HAS_CPU_MIPS32_R1 362 select SYS_HAS_CPU_MIPS32_R2 363 select SYS_SUPPORTS_32BIT_KERNEL 364 select SYS_SUPPORTS_BIG_ENDIAN 365 select SYS_SUPPORTS_LITTLE_ENDIAN ··· 382 select RM7000_CPU_SCACHE 383 select SWAP_IO_SPACE 384 select SYS_HAS_CPU_RM9000 385 select SYS_SUPPORTS_32BIT_KERNEL 386 select SYS_SUPPORTS_64BIT_KERNEL 387 select SYS_SUPPORTS_BIG_ENDIAN ··· 520 select IRQ_CPU_RM9K 521 select SWAP_IO_SPACE 522 select SYS_HAS_CPU_RM9000 523 select SYS_SUPPORTS_32BIT_KERNEL 524 select SYS_SUPPORTS_64BIT_KERNEL 525 select SYS_SUPPORTS_BIG_ENDIAN ··· 581 select SWAP_IO_SPACE 582 select SYS_HAS_CPU_R4X00 583 select SYS_HAS_CPU_R5000 584 select SYS_SUPPORTS_32BIT_KERNEL 585 select SYS_SUPPORTS_64BIT_KERNEL 586 select SYS_SUPPORTS_BIG_ENDIAN ··· 596 select ARC64 597 select BOOT_ELF64 598 select DMA_IP27 599 - select EARLY_PRINTK 600 select HW_HAS_PCI 601 select NR_CPUS_DEFAULT_64 602 select PCI_DOMAINS ··· 758 select SYS_HAS_CPU_R5000 759 select SYS_HAS_CPU_R10000 760 select R5000_CPU_SCACHE 761 select SYS_SUPPORTS_32BIT_KERNEL 762 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 763 select SYS_SUPPORTS_BIG_ENDIAN ··· 907 bool 908 909 config EARLY_PRINTK 910 bool 911 912 config GENERIC_ISA_DMA ··· 1057 select DMA_NONCOHERENT 1058 select HW_HAS_PCI 1059 select SYS_HAS_CPU_MIPS32_R1 1060 select SYS_SUPPORTS_32BIT_KERNEL 1061 select GENERIC_HARDIRQS_NO__DO_IRQ 1062 select SYS_SUPPORTS_KGDB ··· 1118 1119 config ARC_CONSOLE 1120 bool "ARC console support" 1121 - depends on SGI_IP22 || SNI_RM 1122 1123 config ARC_MEMORY 1124 bool ··· 1919 default 1024 if HZ_1024 1920 1921 source "kernel/Kconfig.preempt" 1922 - 1923 - config RTC_DS1742 1924 - bool "DS1742 BRAM/RTC support" 1925 - depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 1926 1927 config MIPS_INSANE_LARGE 1928 bool "Support for large 64-bit configurations"
··· 176 bool "DECstations" 177 select BOOT_ELF32 178 select DMA_NONCOHERENT 179 + select SYS_HAS_EARLY_PRINTK 180 select IRQ_CPU 181 select SYS_HAS_CPU_R3000 182 select SYS_HAS_CPU_R4X00 ··· 242 config LASAT 243 bool "LASAT Networks platforms" 244 select DMA_NONCOHERENT 245 + select SYS_HAS_EARLY_PRINTK 246 select HW_HAS_PCI 247 select MIPS_GT64120 248 select MIPS_NILE4 ··· 256 bool "MIPS Atlas board" 257 select BOOT_ELF32 258 select DMA_NONCOHERENT 259 + select SYS_HAS_EARLY_PRINTK 260 select IRQ_CPU 261 select HW_HAS_PCI 262 select MIPS_BOARDS_GEN ··· 301 select SYS_HAS_CPU_MIPS64_R1 302 select SYS_HAS_CPU_NEVADA 303 select SYS_HAS_CPU_RM7000 304 + select SYS_HAS_EARLY_PRINTK 305 select SYS_SUPPORTS_32BIT_KERNEL 306 select SYS_SUPPORTS_64BIT_KERNEL 307 select SYS_SUPPORTS_BIG_ENDIAN ··· 316 depends on EXPERIMENTAL 317 select IRQ_CPU 318 select DMA_NONCOHERENT 319 + select SYS_HAS_EARLY_PRINTK 320 select MIPS_BOARDS_GEN 321 select SYS_HAS_CPU_MIPS32_R1 322 select SYS_HAS_CPU_MIPS32_R2 ··· 353 config MIPS_SIM 354 bool 'MIPS simulator (MIPSsim)' 355 select DMA_NONCOHERENT 356 + select SYS_HAS_EARLY_PRINTK 357 select IRQ_CPU 358 select SYS_HAS_CPU_MIPS32_R1 359 select SYS_HAS_CPU_MIPS32_R2 360 + select SYS_HAS_EARLY_PRINTK 361 select SYS_SUPPORTS_32BIT_KERNEL 362 select SYS_SUPPORTS_BIG_ENDIAN 363 select SYS_SUPPORTS_LITTLE_ENDIAN ··· 376 select RM7000_CPU_SCACHE 377 select SWAP_IO_SPACE 378 select SYS_HAS_CPU_RM9000 379 + select SYS_HAS_EARLY_PRINTK 380 select SYS_SUPPORTS_32BIT_KERNEL 381 select SYS_SUPPORTS_64BIT_KERNEL 382 select SYS_SUPPORTS_BIG_ENDIAN ··· 513 select IRQ_CPU_RM9K 514 select SWAP_IO_SPACE 515 select SYS_HAS_CPU_RM9000 516 + select SYS_HAS_EARLY_PRINTK 517 select SYS_SUPPORTS_32BIT_KERNEL 518 select SYS_SUPPORTS_64BIT_KERNEL 519 select SYS_SUPPORTS_BIG_ENDIAN ··· 573 select SWAP_IO_SPACE 574 select SYS_HAS_CPU_R4X00 575 select SYS_HAS_CPU_R5000 576 + select SYS_HAS_EARLY_PRINTK 577 select SYS_SUPPORTS_32BIT_KERNEL 578 select SYS_SUPPORTS_64BIT_KERNEL 579 select SYS_SUPPORTS_BIG_ENDIAN ··· 587 select ARC64 588 select BOOT_ELF64 589 select DMA_IP27 590 + select SYS_HAS_EARLY_PRINTK 591 select HW_HAS_PCI 592 select NR_CPUS_DEFAULT_64 593 select PCI_DOMAINS ··· 749 select SYS_HAS_CPU_R5000 750 select SYS_HAS_CPU_R10000 751 select R5000_CPU_SCACHE 752 + select SYS_HAS_EARLY_PRINTK 753 select SYS_SUPPORTS_32BIT_KERNEL 754 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 755 select SYS_SUPPORTS_BIG_ENDIAN ··· 897 bool 898 899 config EARLY_PRINTK 900 + bool "Early printk" if EMBEDDED && DEBUG_KERNEL 901 + depends on SYS_HAS_EARLY_PRINTK 902 + default y 903 + help 904 + This option enables special console drivers which allow the kernel 905 + to print messages very early in the bootup process. 906 + 907 + This is useful for kernel debugging when your machine crashes very 908 + early before the console code is initialized. For normal operation 909 + it is not recommended because it looks on some machines ugly and 910 + oesn't cooperate with an X server. You should normally N here, 911 + unless you want to debug such a crash. 912 + 913 + config SYS_HAS_EARLY_PRINTK 914 bool 915 916 config GENERIC_ISA_DMA ··· 1033 select DMA_NONCOHERENT 1034 select HW_HAS_PCI 1035 select SYS_HAS_CPU_MIPS32_R1 1036 + select SYS_HAS_EARLY_PRINTK 1037 select SYS_SUPPORTS_32BIT_KERNEL 1038 select GENERIC_HARDIRQS_NO__DO_IRQ 1039 select SYS_SUPPORTS_KGDB ··· 1093 1094 config ARC_CONSOLE 1095 bool "ARC console support" 1096 + depends on SGI_IP22 || (SNI_RM && CPU_LITTLE_ENDIAN) 1097 1098 config ARC_MEMORY 1099 bool ··· 1894 default 1024 if HZ_1024 1895 1896 source "kernel/Kconfig.preempt" 1897 1898 config MIPS_INSANE_LARGE 1899 bool "Support for large 64-bit configurations"
-32
arch/mips/arc/console.c
··· 29 ArcWrite(1, &it, 1, &cnt); 30 bc_enable(); 31 } 32 - 33 - char prom_getchar(void) 34 - { 35 - ULONG cnt; 36 - CHAR c; 37 - 38 - bc_disable(); 39 - ArcRead(0, &c, 1, &cnt); 40 - bc_enable(); 41 - 42 - return c; 43 - } 44 - 45 - void prom_printf(char *fmt, ...) 46 - { 47 - va_list args; 48 - char ppbuf[1024]; 49 - char *bptr; 50 - 51 - va_start(args, fmt); 52 - vsprintf(ppbuf, fmt, args); 53 - 54 - bptr = ppbuf; 55 - 56 - while (*bptr != 0) { 57 - if (*bptr == '\n') 58 - prom_putchar('\r'); 59 - 60 - prom_putchar(*bptr++); 61 - } 62 - va_end(args); 63 - }
··· 29 ArcWrite(1, &it, 1, &cnt); 30 bc_enable(); 31 }
+6 -3
arch/mips/arc/init.c
··· 24 { 25 PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK; 26 romvec = ROMVECTOR; 27 prom_argc = fw_arg0; 28 _prom_argv = (LONG *) fw_arg1; 29 _prom_envp = (LONG *) fw_arg2; 30 31 if (pb->magic != 0x53435241) { 32 - prom_printf("Aieee, bad prom vector magic %08lx\n", pb->magic); 33 while(1) 34 ; 35 } ··· 44 prom_meminit(); 45 46 #ifdef DEBUG_PROM_INIT 47 - prom_printf("Press a key to reboot\n"); 48 - prom_getchar(); 49 ArcEnterInteractiveMode(); 50 #endif 51 }
··· 24 { 25 PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK; 26 romvec = ROMVECTOR; 27 + ULONG cnt; 28 + CHAR c; 29 + 30 prom_argc = fw_arg0; 31 _prom_argv = (LONG *) fw_arg1; 32 _prom_envp = (LONG *) fw_arg2; 33 34 if (pb->magic != 0x53435241) { 35 + printk(KERN_CRIT "Aieee, bad prom vector magic %08lx\n", pb->magic); 36 while(1) 37 ; 38 } ··· 41 prom_meminit(); 42 43 #ifdef DEBUG_PROM_INIT 44 + pr_info("Press a key to reboot\n"); 45 + ArcRead(0, &c, 1, &cnt); 46 ArcEnterInteractiveMode(); 47 #endif 48 }
+3 -3
arch/mips/arc/memory.c
··· 118 #ifdef DEBUG 119 int i = 0; 120 121 - prom_printf("ARCS MEMORY DESCRIPTOR dump:\n"); 122 p = ArcGetMemoryDescriptor(PROM_NULL_MDESC); 123 while(p) { 124 - prom_printf("[%d,%p]: base<%08lx> pages<%08lx> type<%s>\n", 125 - i, p, p->base, p->pages, mtypes(p->type)); 126 p = ArcGetMemoryDescriptor(p); 127 i++; 128 }
··· 118 #ifdef DEBUG 119 int i = 0; 120 121 + printk("ARCS MEMORY DESCRIPTOR dump:\n"); 122 p = ArcGetMemoryDescriptor(PROM_NULL_MDESC); 123 while(p) { 124 + printk("[%d,%p]: base<%08lx> pages<%08lx> type<%s>\n", 125 + i, p, p->base, p->pages, mtypes(p->type)); 126 p = ArcGetMemoryDescriptor(p); 127 i++; 128 }
+5 -5
arch/mips/arc/tree.c
··· 93 static void __init 94 dump_component(pcomponent *p) 95 { 96 - prom_printf("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>", 97 - p, classes[p->class], types[p->type], 98 - iflags[p->iflags], p->vers, p->rev); 99 - prom_printf("key<%08lx>\n\tamask<%08lx>cdsize<%d>ilen<%d>iname<%s>\n", 100 - p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname); 101 } 102 103 static void __init
··· 93 static void __init 94 dump_component(pcomponent *p) 95 { 96 + printk("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>", 97 + p, classes[p->class], types[p->type], 98 + iflags[p->iflags], p->vers, p->rev); 99 + printk("key<%08lx>\n\tamask<%08lx>cdsize<%d>ilen<%d>iname<%s>\n", 100 + p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname); 101 } 102 103 static void __init
+30 -3
arch/mips/au1000/mtx-1/board_setup.c
··· 43 #include <asm/pgtable.h> 44 #include <asm/mach-au1x00/au1000.h> 45 46 void board_reset (void) 47 { 48 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ ··· 69 #endif 70 71 // initialize sys_pinfunc: 72 - // disable second ethernet port (SYS_PF_NI2) 73 - // set U3/GPIO23 to GPIO23 (SYS_PF_U3) 74 - au_writel( SYS_PF_NI2 | SYS_PF_U3, SYS_PINFUNC ); 75 76 // initialize GPIO 77 au_writel( 0xFFFFFFFF, SYS_TRIOUTCLR ); 78 au_writel( 0x00000001, SYS_OUTPUTCLR ); // set M66EN (PCI 66MHz) to OFF 79 au_writel( 0x00000008, SYS_OUTPUTSET ); // set PCI CLKRUN# to OFF 80 au_writel( 0x00000020, SYS_OUTPUTCLR ); // set eth PHY TX_ER to OFF 81 82 // enable LED and set it to green 83 au_writel( au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR ); 84 au_writel( 0x18000800, GPIO2_OUTPUT ); 85 86 printk("4G Systems MTX-1 Board\n"); 87 }
··· 43 #include <asm/pgtable.h> 44 #include <asm/mach-au1x00/au1000.h> 45 46 + extern int (*board_pci_idsel)(unsigned int devsel, int assert); 47 + int mtx1_pci_idsel(unsigned int devsel, int assert); 48 + 49 void board_reset (void) 50 { 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ ··· 66 #endif 67 68 // initialize sys_pinfunc: 69 + au_writel( SYS_PF_NI2, SYS_PINFUNC ); 70 71 // initialize GPIO 72 au_writel( 0xFFFFFFFF, SYS_TRIOUTCLR ); 73 au_writel( 0x00000001, SYS_OUTPUTCLR ); // set M66EN (PCI 66MHz) to OFF 74 au_writel( 0x00000008, SYS_OUTPUTSET ); // set PCI CLKRUN# to OFF 75 + au_writel( 0x00000002, SYS_OUTPUTSET ); // set EXT_IO3 ON 76 au_writel( 0x00000020, SYS_OUTPUTCLR ); // set eth PHY TX_ER to OFF 77 78 // enable LED and set it to green 79 au_writel( au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR ); 80 au_writel( 0x18000800, GPIO2_OUTPUT ); 81 82 + board_pci_idsel = mtx1_pci_idsel; 83 + 84 printk("4G Systems MTX-1 Board\n"); 85 } 86 + 87 + int 88 + mtx1_pci_idsel(unsigned int devsel, int assert) 89 + { 90 + #define MTX_IDSEL_ONLY_0_AND_3 0 91 + #if MTX_IDSEL_ONLY_0_AND_3 92 + if (devsel != 0 && devsel != 3) { 93 + printk("*** not 0 or 3\n"); 94 + return 0; 95 + } 96 + #endif 97 + 98 + if (assert && devsel != 0) { 99 + // supress signal to cardbus 100 + au_writel( 0x00000002, SYS_OUTPUTCLR ); // set EXT_IO3 OFF 101 + } 102 + else { 103 + au_writel( 0x00000002, SYS_OUTPUTSET ); // set EXT_IO3 ON 104 + } 105 + au_sync_udelay(1); 106 + return 1; 107 + } 108 +
+1 -1
arch/mips/au1000/mtx-1/irqmap.c
··· 48 #include <asm/mach-au1x00/au1000.h> 49 50 char irq_tab_alchemy[][5] __initdata = { 51 - [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */ 52 [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ 53 [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */ 54 [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
··· 48 #include <asm/mach-au1x00/au1000.h> 49 50 char irq_tab_alchemy[][5] __initdata = { 51 + [0] = { -1, INTA, INTA, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */ 52 [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ 53 [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */ 54 [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
-26
arch/mips/cobalt/console.c
··· 19 20 COBALT_UART[UART_TX] = c; 21 } 22 - 23 - static void cons_write(struct console *c, const char *s, unsigned n) 24 - { 25 - while(n-- && *s) 26 - putchar(*s++); 27 - } 28 - 29 - static struct console cons_info = 30 - { 31 - .name = "uart", 32 - .write = cons_write, 33 - .flags = CON_PRINTBUFFER | CON_BOOT, 34 - .index = -1, 35 - }; 36 - 37 - void __init cobalt_early_console(void) 38 - { 39 - register_console(&cons_info); 40 - 41 - printk("Cobalt: early console registered\n"); 42 - } 43 - 44 - void __init disable_early_printk(void) 45 - { 46 - unregister_console(&cons_info); 47 - }
··· 19 20 COBALT_UART[UART_TX] = c; 21 }
+24 -27
arch/mips/cobalt/setup.c
··· 79 .flags = IORESOURCE_IO 80 }; 81 82 - static struct resource cobalt_io_resources[] = { 83 - { 84 .start = 0x00, 85 .end = 0x1f, 86 - .name = "dma1", 87 - .flags = IORESOURCE_BUSY 88 - }, { 89 - .start = 0x40, 90 - .end = 0x5f, 91 - .name = "timer", 92 - .flags = IORESOURCE_BUSY 93 - }, { 94 .start = 0x60, 95 .end = 0x6f, 96 - .name = "keyboard", 97 - .flags = IORESOURCE_BUSY 98 - }, { 99 .start = 0x80, 100 .end = 0x8f, 101 - .name = "dma page reg", 102 - .flags = IORESOURCE_BUSY 103 - }, { 104 .start = 0xc0, 105 .end = 0xdf, 106 - .name = "dma2", 107 - .flags = IORESOURCE_BUSY 108 }, 109 }; 110 - 111 - #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource)) 112 113 static struct pci_controller cobalt_pci_controller = { 114 .pci_ops = &gt64111_pci_ops, ··· 134 /* I/O port resource must include LCD/buttons */ 135 ioport_resource.end = 0x0fffffff; 136 137 - /* request I/O space for devices used on all i[345]86 PCs */ 138 - for (i = 0; i < COBALT_IO_RESOURCES; i++) 139 - request_resource(&ioport_resource, cobalt_io_resources + i); 140 141 /* Read the cobalt id register out of the PCI config space */ 142 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); ··· 151 #endif 152 153 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 154 - #ifdef CONFIG_EARLY_PRINTK 155 - cobalt_early_console(); 156 - #endif 157 - 158 #ifdef CONFIG_SERIAL_8250 159 uart.line = 0; 160 uart.type = PORT_UNKNOWN;
··· 79 .flags = IORESOURCE_IO 80 }; 81 82 + /* 83 + * Cobalt doesn't have PS/2 keyboard/mouse interfaces, 84 + * keyboard conntroller is never used. 85 + * Also PCI-ISA bridge DMA contoroller is never used. 86 + */ 87 + static struct resource cobalt_reserved_resources[] = { 88 + { /* dma1 */ 89 .start = 0x00, 90 .end = 0x1f, 91 + .name = "reserved", 92 + .flags = IORESOURCE_BUSY | IORESOURCE_IO, 93 + }, 94 + { /* keyboard */ 95 .start = 0x60, 96 .end = 0x6f, 97 + .name = "reserved", 98 + .flags = IORESOURCE_BUSY | IORESOURCE_IO, 99 + }, 100 + { /* dma page reg */ 101 .start = 0x80, 102 .end = 0x8f, 103 + .name = "reserved", 104 + .flags = IORESOURCE_BUSY | IORESOURCE_IO, 105 + }, 106 + { /* dma2 */ 107 .start = 0xc0, 108 .end = 0xdf, 109 + .name = "reserved", 110 + .flags = IORESOURCE_BUSY | IORESOURCE_IO, 111 }, 112 }; 113 114 static struct pci_controller cobalt_pci_controller = { 115 .pci_ops = &gt64111_pci_ops, ··· 133 /* I/O port resource must include LCD/buttons */ 134 ioport_resource.end = 0x0fffffff; 135 136 + /* These resources have been reserved by VIA SuperI/O chip. */ 137 + for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) 138 + request_resource(&ioport_resource, cobalt_reserved_resources + i); 139 140 /* Read the cobalt id register out of the PCI config space */ 141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); ··· 150 #endif 151 152 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 153 #ifdef CONFIG_SERIAL_8250 154 uart.line = 0; 155 uart.type = PORT_UNKNOWN;
+22 -2
arch/mips/configs/jmr3927_defconfig
··· 148 CONFIG_PREEMPT_NONE=y 149 # CONFIG_PREEMPT_VOLUNTARY is not set 150 # CONFIG_PREEMPT is not set 151 - CONFIG_RTC_DS1742=y 152 # CONFIG_KEXEC is not set 153 CONFIG_LOCKDEP_SUPPORT=y 154 CONFIG_STACKTRACE_SUPPORT=y ··· 801 # 802 # Real Time Clock 803 # 804 - # CONFIG_RTC_CLASS is not set 805 806 # 807 # DMA Engine support
··· 148 CONFIG_PREEMPT_NONE=y 149 # CONFIG_PREEMPT_VOLUNTARY is not set 150 # CONFIG_PREEMPT is not set 151 # CONFIG_KEXEC is not set 152 CONFIG_LOCKDEP_SUPPORT=y 153 CONFIG_STACKTRACE_SUPPORT=y ··· 802 # 803 # Real Time Clock 804 # 805 + CONFIG_RTC_LIB=y 806 + CONFIG_RTC_CLASS=y 807 + CONFIG_RTC_HCTOSYS=y 808 + CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 809 + # CONFIG_RTC_DEBUG is not set 810 + 811 + # 812 + # RTC interfaces 813 + # 814 + CONFIG_RTC_INTF_SYSFS=y 815 + CONFIG_RTC_INTF_PROC=y 816 + CONFIG_RTC_INTF_DEV=y 817 + # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 818 + 819 + # 820 + # RTC drivers 821 + # 822 + # CONFIG_RTC_DRV_DS1553 is not set 823 + CONFIG_RTC_DRV_DS1742=y 824 + # CONFIG_RTC_DRV_M48T86 is not set 825 + # CONFIG_RTC_DRV_TEST is not set 826 + # CONFIG_RTC_DRV_V3020 is not set 827 828 # 829 # DMA Engine support
+6 -34
arch/mips/dec/prom/console.c
··· 16 17 #include <asm/dec/prom.h> 18 19 - static void __init prom_console_write(struct console *con, const char *s, 20 - unsigned int c) 21 { 22 - static char sfmt[] __initdata = "%%%us"; 23 - char fmt[13]; 24 25 - snprintf(fmt, sizeof(fmt), sfmt, c); 26 - prom_printf(fmt, s); 27 } 28 - 29 - static struct console promcons __initdata = { 30 - .name = "prom", 31 - .write = prom_console_write, 32 - .flags = CON_PRINTBUFFER, 33 - .index = -1, 34 - }; 35 - 36 - static int promcons_output __initdata = 0; 37 - 38 - void __init register_prom_console(void) 39 - { 40 - if (!promcons_output) { 41 - promcons_output = 1; 42 - register_console(&promcons); 43 - } 44 - } 45 - 46 - void __init unregister_prom_console(void) 47 - { 48 - if (promcons_output) { 49 - unregister_console(&promcons); 50 - promcons_output = 0; 51 - } 52 - } 53 - 54 - void disable_early_printk(void) 55 - __attribute__((alias("unregister_prom_console")));
··· 16 17 #include <asm/dec/prom.h> 18 19 + void prom_putchar(char c) 20 { 21 + char s[2]; 22 23 + s[0] = c; 24 + s[1] = '\0'; 25 + 26 + prom_printf( s); 27 }
-3
arch/mips/dec/prom/identify.c
··· 26 27 #include "dectypes.h" 28 29 - extern unsigned long mips_machgroup; 30 - extern unsigned long mips_machtype; 31 - 32 static const char *dec_system_strings[] = { 33 [MACH_DSUNKNOWN] "unknown DECstation", 34 [MACH_DS23100] "DECstation 2100/3100",
··· 26 27 #include "dectypes.h" 28 29 static const char *dec_system_strings[] = { 30 [MACH_DSUNKNOWN] "unknown DECstation", 31 [MACH_DS23100] "DECstation 2100/3100",
-5
arch/mips/gt64120/ev64120/promcon.c
··· 24 } 25 } 26 27 - int prom_getchar(void) 28 - { 29 - return 0; 30 - } 31 - 32 static struct console sercons = { 33 .name = "ttyS", 34 .write = prom_console_write,
··· 24 } 25 } 26 27 static struct console sercons = { 28 .name = "ttyS", 29 .write = prom_console_write,
+1 -1
arch/mips/jmr3927/common/Makefile
··· 2 # Makefile for the common code of TOSHIBA JMR-TX3927 board 3 # 4 5 - obj-y += prom.o puts.o rtc_ds1742.o
··· 2 # Makefile for the common code of TOSHIBA JMR-TX3927 board 3 # 4 5 + obj-y += prom.o puts.o
-171
arch/mips/jmr3927/common/rtc_ds1742.c
··· 1 - /* 2 - * Copyright 2001 MontaVista Software Inc. 3 - * Author: MontaVista Software, Inc. 4 - * ahennessy@mvista.com 5 - * 6 - * arch/mips/jmr3927/common/rtc_ds1742.c 7 - * Based on arch/mips/ddb5xxx/common/rtc_ds1386.c 8 - * low-level RTC hookups for s for Dallas 1742 chip. 9 - * 10 - * Copyright (C) 2000-2001 Toshiba Corporation 11 - * 12 - * This program is free software; you can redistribute it and/or modify it 13 - * under the terms of the GNU General Public License as published by the 14 - * Free Software Foundation; either version 2 of the License, or (at your 15 - * option) any later version. 16 - * 17 - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 18 - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 24 - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 - * 28 - * You should have received a copy of the GNU General Public License along 29 - * with this program; if not, write to the Free Software Foundation, Inc., 30 - * 675 Mass Ave, Cambridge, MA 02139, USA. 31 - */ 32 - 33 - 34 - /* 35 - * This file exports a function, rtc_ds1386_init(), which expects an 36 - * uncached base address as the argument. It will set the two function 37 - * pointers expected by the MIPS generic timer code. 38 - */ 39 - 40 - #include <linux/bcd.h> 41 - #include <linux/types.h> 42 - #include <linux/time.h> 43 - #include <linux/rtc.h> 44 - #include <linux/ds1742rtc.h> 45 - 46 - #include <asm/time.h> 47 - #include <asm/addrspace.h> 48 - 49 - #include <asm/debug.h> 50 - 51 - #define EPOCH 2000 52 - 53 - static unsigned long rtc_base; 54 - 55 - static unsigned long 56 - rtc_ds1742_get_time(void) 57 - { 58 - unsigned int year, month, day, hour, minute, second; 59 - unsigned int century; 60 - unsigned long flags; 61 - 62 - spin_lock_irqsave(&rtc_lock, flags); 63 - rtc_write(RTC_READ, RTC_CONTROL); 64 - second = BCD2BIN(rtc_read(RTC_SECONDS) & RTC_SECONDS_MASK); 65 - minute = BCD2BIN(rtc_read(RTC_MINUTES)); 66 - hour = BCD2BIN(rtc_read(RTC_HOURS)); 67 - day = BCD2BIN(rtc_read(RTC_DATE)); 68 - month = BCD2BIN(rtc_read(RTC_MONTH)); 69 - year = BCD2BIN(rtc_read(RTC_YEAR)); 70 - century = BCD2BIN(rtc_read(RTC_CENTURY) & RTC_CENTURY_MASK); 71 - rtc_write(0, RTC_CONTROL); 72 - spin_unlock_irqrestore(&rtc_lock, flags); 73 - 74 - year += century * 100; 75 - 76 - return mktime(year, month, day, hour, minute, second); 77 - } 78 - extern void to_tm(unsigned long tim, struct rtc_time * tm); 79 - 80 - static int 81 - rtc_ds1742_set_time(unsigned long t) 82 - { 83 - struct rtc_time tm; 84 - u8 year, month, day, hour, minute, second; 85 - u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second; 86 - int cmos_century; 87 - unsigned long flags; 88 - 89 - spin_lock_irqsave(&rtc_lock, flags); 90 - rtc_write(RTC_READ, RTC_CONTROL); 91 - cmos_second = (u8)(rtc_read(RTC_SECONDS) & RTC_SECONDS_MASK); 92 - cmos_minute = (u8)rtc_read(RTC_MINUTES); 93 - cmos_hour = (u8)rtc_read(RTC_HOURS); 94 - cmos_day = (u8)rtc_read(RTC_DATE); 95 - cmos_month = (u8)rtc_read(RTC_MONTH); 96 - cmos_year = (u8)rtc_read(RTC_YEAR); 97 - cmos_century = rtc_read(RTC_CENTURY) & RTC_CENTURY_MASK; 98 - 99 - rtc_write(RTC_WRITE, RTC_CONTROL); 100 - 101 - /* convert */ 102 - to_tm(t, &tm); 103 - 104 - /* check each field one by one */ 105 - year = BIN2BCD(tm.tm_year - EPOCH); 106 - if (year != cmos_year) { 107 - rtc_write(year,RTC_YEAR); 108 - } 109 - 110 - month = BIN2BCD(tm.tm_mon); 111 - if (month != (cmos_month & 0x1f)) { 112 - rtc_write((month & 0x1f) | (cmos_month & ~0x1f),RTC_MONTH); 113 - } 114 - 115 - day = BIN2BCD(tm.tm_mday); 116 - if (day != cmos_day) { 117 - 118 - rtc_write(day, RTC_DATE); 119 - } 120 - 121 - if (cmos_hour & 0x40) { 122 - /* 12 hour format */ 123 - hour = 0x40; 124 - if (tm.tm_hour > 12) { 125 - hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f); 126 - } else { 127 - hour |= BIN2BCD(tm.tm_hour); 128 - } 129 - } else { 130 - /* 24 hour format */ 131 - hour = BIN2BCD(tm.tm_hour) & 0x3f; 132 - } 133 - if (hour != cmos_hour) rtc_write(hour, RTC_HOURS); 134 - 135 - minute = BIN2BCD(tm.tm_min); 136 - if (minute != cmos_minute) { 137 - rtc_write(minute, RTC_MINUTES); 138 - } 139 - 140 - second = BIN2BCD(tm.tm_sec); 141 - if (second != cmos_second) { 142 - rtc_write(second & RTC_SECONDS_MASK,RTC_SECONDS); 143 - } 144 - 145 - /* RTC_CENTURY and RTC_CONTROL share same address... */ 146 - rtc_write(cmos_century, RTC_CONTROL); 147 - spin_unlock_irqrestore(&rtc_lock, flags); 148 - 149 - return 0; 150 - } 151 - 152 - void 153 - rtc_ds1742_init(unsigned long base) 154 - { 155 - u8 cmos_second; 156 - 157 - /* remember the base */ 158 - rtc_base = base; 159 - db_assert((rtc_base & 0xe0000000) == KSEG1); 160 - 161 - /* set the function pointers */ 162 - rtc_mips_get_time = rtc_ds1742_get_time; 163 - rtc_mips_set_time = rtc_ds1742_set_time; 164 - 165 - /* clear oscillator stop bit */ 166 - rtc_write(RTC_READ, RTC_CONTROL); 167 - cmos_second = (u8)(rtc_read(RTC_SECONDS) & RTC_SECONDS_MASK); 168 - rtc_write(RTC_WRITE, RTC_CONTROL); 169 - rtc_write(cmos_second, RTC_SECONDS); /* clear msb */ 170 - rtc_write(0, RTC_CONTROL); 171 - }
···
+30 -9
arch/mips/jmr3927/rbhma3100/setup.c
··· 45 #include <linux/param.h> /* for HZ */ 46 #include <linux/delay.h> 47 #include <linux/pm.h> 48 #ifdef CONFIG_SERIAL_TXX9 49 #include <linux/tty.h> 50 #include <linux/serial.h> ··· 173 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; 174 } 175 176 - #define USE_RTC_DS1742 177 - #ifdef USE_RTC_DS1742 178 - extern void rtc_ds1742_init(unsigned long base); 179 - #endif 180 static void __init jmr3927_time_init(void) 181 { 182 clocksource_mips.read = jmr3927_hpt_read; 183 mips_hpt_frequency = JMR3927_TIMER_CLK; 184 - #ifdef USE_RTC_DS1742 185 - if (jmr3927_have_nvram()) { 186 - rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR); 187 - } 188 - #endif 189 } 190 191 void __init plat_timer_setup(struct irqaction *irq) ··· 532 printk("TX3927 D-Cache WriteBack (CWF) .\n"); 533 } 534 }
··· 45 #include <linux/param.h> /* for HZ */ 46 #include <linux/delay.h> 47 #include <linux/pm.h> 48 + #include <linux/platform_device.h> 49 #ifdef CONFIG_SERIAL_TXX9 50 #include <linux/tty.h> 51 #include <linux/serial.h> ··· 172 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; 173 } 174 175 static void __init jmr3927_time_init(void) 176 { 177 clocksource_mips.read = jmr3927_hpt_read; 178 mips_hpt_frequency = JMR3927_TIMER_CLK; 179 } 180 181 void __init plat_timer_setup(struct irqaction *irq) ··· 540 printk("TX3927 D-Cache WriteBack (CWF) .\n"); 541 } 542 } 543 + 544 + /* This trick makes rtc-ds1742 driver usable as is. */ 545 + unsigned long __swizzle_addr_b(unsigned long port) 546 + { 547 + if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) 548 + return port; 549 + port = (port & 0xffff0000) | (port & 0x7fff << 1); 550 + #ifdef __BIG_ENDIAN 551 + return port; 552 + #else 553 + return port | 1; 554 + #endif 555 + } 556 + EXPORT_SYMBOL(__swizzle_addr_b); 557 + 558 + static int __init jmr3927_rtc_init(void) 559 + { 560 + struct resource res = { 561 + .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, 562 + .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, 563 + .flags = IORESOURCE_MEM, 564 + }; 565 + struct platform_device *dev; 566 + if (!jmr3927_have_nvram()) 567 + return -ENODEV; 568 + dev = platform_device_register_simple("ds1742", -1, &res, 1); 569 + return IS_ERR(dev) ? PTR_ERR(dev) : 0; 570 + } 571 + device_initcall(jmr3927_rtc_init);
+1
arch/mips/kernel/Makefile
··· 65 obj-$(CONFIG_I8253) += i8253.o 66 67 obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o 68 69 CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
··· 65 obj-$(CONFIG_I8253) += i8253.o 66 67 obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o 68 + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 69 70 CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
+40
arch/mips/kernel/early_printk.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2002, 2003, 06, 07 Ralf Baechle (ralf@linux-mips.org) 7 + * Copyright (C) 2007 MIPS Technologies, Inc. 8 + * written by Ralf Baechle (ralf@linux-mips.org) 9 + */ 10 + #include <linux/console.h> 11 + #include <linux/init.h> 12 + 13 + extern void prom_putchar(char); 14 + 15 + static void early_console_write(struct console *con, const char *s, unsigned n) 16 + { 17 + while (n-- && *s) { 18 + if (*s == '\n') 19 + prom_putchar('\r'); 20 + prom_putchar(*s); 21 + s++; 22 + } 23 + } 24 + 25 + static struct console early_console = { 26 + .name = "early", 27 + .write = early_console_write, 28 + .flags = CON_PRINTBUFFER | CON_BOOT, 29 + .index = -1 30 + }; 31 + 32 + void __init setup_early_printk(void) 33 + { 34 + register_console(&early_console); 35 + } 36 + 37 + void __init disable_early_printk(void) 38 + { 39 + unregister_console(&early_console); 40 + }
-173
arch/mips/kernel/linux32.c
··· 166 return error; 167 } 168 169 - asmlinkage long 170 - sysn32_waitid(int which, compat_pid_t pid, 171 - siginfo_t __user *uinfo, int options, 172 - struct compat_rusage __user *uru) 173 - { 174 - struct rusage ru; 175 - long ret; 176 - mm_segment_t old_fs = get_fs(); 177 - int si_signo; 178 - 179 - if (!access_ok(VERIFY_WRITE, uinfo, sizeof(*uinfo))) 180 - return -EFAULT; 181 - 182 - set_fs (KERNEL_DS); 183 - ret = sys_waitid(which, pid, uinfo, options, 184 - uru ? (struct rusage __user *) &ru : NULL); 185 - set_fs (old_fs); 186 - 187 - if (__get_user(si_signo, &uinfo->si_signo)) 188 - return -EFAULT; 189 - if (ret < 0 || si_signo == 0) 190 - return ret; 191 - 192 - if (uru) 193 - ret = put_compat_rusage(&ru, uru); 194 - return ret; 195 - } 196 - 197 #define RLIM_INFINITY32 0x7fffffff 198 #define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x) 199 ··· 542 return sys_sync_file_range(fd, 543 merge_64(a2, a3), merge_64(a4, a5), 544 flags); 545 - } 546 - 547 - /* Argument list sizes for sys_socketcall */ 548 - #define AL(x) ((x) * sizeof(unsigned int)) 549 - static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), 550 - AL(3),AL(3),AL(4),AL(4),AL(4),AL(6), 551 - AL(6),AL(2),AL(5),AL(5),AL(3),AL(3)}; 552 - #undef AL 553 - 554 - /* 555 - * System call vectors. 556 - * 557 - * Argument checking cleaned up. Saved 20% in size. 558 - * This function doesn't need to set the kernel lock because 559 - * it is set by the callees. 560 - */ 561 - 562 - asmlinkage long sys32_socketcall(int call, unsigned int __user *args32) 563 - { 564 - unsigned int a[6]; 565 - unsigned int a0,a1; 566 - int err; 567 - 568 - extern asmlinkage long sys_socket(int family, int type, int protocol); 569 - extern asmlinkage long sys_bind(int fd, struct sockaddr __user *umyaddr, int addrlen); 570 - extern asmlinkage long sys_connect(int fd, struct sockaddr __user *uservaddr, int addrlen); 571 - extern asmlinkage long sys_listen(int fd, int backlog); 572 - extern asmlinkage long sys_accept(int fd, struct sockaddr __user *upeer_sockaddr, int __user *upeer_addrlen); 573 - extern asmlinkage long sys_getsockname(int fd, struct sockaddr __user *usockaddr, int __user *usockaddr_len); 574 - extern asmlinkage long sys_getpeername(int fd, struct sockaddr __user *usockaddr, int __user *usockaddr_len); 575 - extern asmlinkage long sys_socketpair(int family, int type, int protocol, int __user *usockvec); 576 - extern asmlinkage long sys_send(int fd, void __user * buff, size_t len, unsigned flags); 577 - extern asmlinkage long sys_sendto(int fd, void __user * buff, size_t len, unsigned flags, 578 - struct sockaddr __user *addr, int addr_len); 579 - extern asmlinkage long sys_recv(int fd, void __user * ubuf, size_t size, unsigned flags); 580 - extern asmlinkage long sys_recvfrom(int fd, void __user * ubuf, size_t size, unsigned flags, 581 - struct sockaddr __user *addr, int __user *addr_len); 582 - extern asmlinkage long sys_shutdown(int fd, int how); 583 - extern asmlinkage long sys_setsockopt(int fd, int level, int optname, char __user *optval, int optlen); 584 - extern asmlinkage long sys_getsockopt(int fd, int level, int optname, char __user *optval, int __user *optlen); 585 - extern asmlinkage long sys_sendmsg(int fd, struct msghdr __user *msg, unsigned flags); 586 - extern asmlinkage long sys_recvmsg(int fd, struct msghdr __user *msg, unsigned int flags); 587 - 588 - 589 - if(call<1||call>SYS_RECVMSG) 590 - return -EINVAL; 591 - 592 - /* copy_from_user should be SMP safe. */ 593 - if (copy_from_user(a, args32, socketcall_nargs[call])) 594 - return -EFAULT; 595 - 596 - a0=a[0]; 597 - a1=a[1]; 598 - 599 - switch(call) 600 - { 601 - case SYS_SOCKET: 602 - err = sys_socket(a0,a1,a[2]); 603 - break; 604 - case SYS_BIND: 605 - err = sys_bind(a0,(struct sockaddr __user *)A(a1), a[2]); 606 - break; 607 - case SYS_CONNECT: 608 - err = sys_connect(a0, (struct sockaddr __user *)A(a1), a[2]); 609 - break; 610 - case SYS_LISTEN: 611 - err = sys_listen(a0,a1); 612 - break; 613 - case SYS_ACCEPT: 614 - err = sys_accept(a0,(struct sockaddr __user *)A(a1), (int __user *)A(a[2])); 615 - break; 616 - case SYS_GETSOCKNAME: 617 - err = sys_getsockname(a0,(struct sockaddr __user *)A(a1), (int __user *)A(a[2])); 618 - break; 619 - case SYS_GETPEERNAME: 620 - err = sys_getpeername(a0, (struct sockaddr __user *)A(a1), (int __user *)A(a[2])); 621 - break; 622 - case SYS_SOCKETPAIR: 623 - err = sys_socketpair(a0,a1, a[2], (int __user *)A(a[3])); 624 - break; 625 - case SYS_SEND: 626 - err = sys_send(a0, (void __user *)A(a1), a[2], a[3]); 627 - break; 628 - case SYS_SENDTO: 629 - err = sys_sendto(a0,(void __user *)A(a1), a[2], a[3], 630 - (struct sockaddr __user *)A(a[4]), a[5]); 631 - break; 632 - case SYS_RECV: 633 - err = sys_recv(a0, (void __user *)A(a1), a[2], a[3]); 634 - break; 635 - case SYS_RECVFROM: 636 - err = sys_recvfrom(a0, (void __user *)A(a1), a[2], a[3], 637 - (struct sockaddr __user *)A(a[4]), (int __user *)A(a[5])); 638 - break; 639 - case SYS_SHUTDOWN: 640 - err = sys_shutdown(a0,a1); 641 - break; 642 - case SYS_SETSOCKOPT: 643 - err = sys_setsockopt(a0, a1, a[2], (char __user *)A(a[3]), a[4]); 644 - break; 645 - case SYS_GETSOCKOPT: 646 - err = sys_getsockopt(a0, a1, a[2], (char __user *)A(a[3]), (int __user *)A(a[4])); 647 - break; 648 - case SYS_SENDMSG: 649 - err = sys_sendmsg(a0, (struct msghdr __user *) A(a1), a[2]); 650 - break; 651 - case SYS_RECVMSG: 652 - err = sys_recvmsg(a0, (struct msghdr __user *) A(a1), a[2]); 653 - break; 654 - default: 655 - err = -EINVAL; 656 - break; 657 - } 658 - return err; 659 - } 660 - 661 - struct sigevent32 { 662 - u32 sigev_value; 663 - u32 sigev_signo; 664 - u32 sigev_notify; 665 - u32 payload[(64 / 4) - 3]; 666 - }; 667 - 668 - extern asmlinkage long 669 - sys_timer_create(clockid_t which_clock, 670 - struct sigevent __user *timer_event_spec, 671 - timer_t __user * created_timer_id); 672 - 673 - long 674 - sys32_timer_create(u32 clock, struct sigevent32 __user *se32, timer_t __user *timer_id) 675 - { 676 - struct sigevent __user *p = NULL; 677 - if (se32) { 678 - struct sigevent se; 679 - p = compat_alloc_user_space(sizeof(struct sigevent)); 680 - memset(&se, 0, sizeof(struct sigevent)); 681 - if (get_user(se.sigev_value.sival_int, &se32->sigev_value) || 682 - __get_user(se.sigev_signo, &se32->sigev_signo) || 683 - __get_user(se.sigev_notify, &se32->sigev_notify) || 684 - __copy_from_user(&se._sigev_un._pad, &se32->payload, 685 - sizeof(se32->payload)) || 686 - copy_to_user(p, &se, sizeof(se))) 687 - return -EFAULT; 688 - } 689 - return sys_timer_create(clock, p, timer_id); 690 } 691 692 save_static_function(sys32_clone);
··· 166 return error; 167 } 168 169 #define RLIM_INFINITY32 0x7fffffff 170 #define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x) 171 ··· 570 return sys_sync_file_range(fd, 571 merge_64(a2, a3), merge_64(a4, a5), 572 flags); 573 } 574 575 save_static_function(sys32_clone);
+2 -2
arch/mips/kernel/scall64-n32.S
··· 340 PTR compat_sys_statfs64 341 PTR compat_sys_fstatfs64 342 PTR sys_sendfile64 343 - PTR sys32_timer_create /* 6220 */ 344 PTR compat_sys_timer_settime 345 PTR compat_sys_timer_gettime 346 PTR sys_timer_getoverrun ··· 361 PTR compat_sys_mq_notify 362 PTR compat_sys_mq_getsetattr 363 PTR sys_ni_syscall /* 6240, sys_vserver */ 364 - PTR sysn32_waitid 365 PTR sys_ni_syscall /* available, was setaltroot */ 366 PTR sys_add_key 367 PTR sys_request_key
··· 340 PTR compat_sys_statfs64 341 PTR compat_sys_fstatfs64 342 PTR sys_sendfile64 343 + PTR compat_sys_timer_create /* 6220 */ 344 PTR compat_sys_timer_settime 345 PTR compat_sys_timer_gettime 346 PTR sys_timer_getoverrun ··· 361 PTR compat_sys_mq_notify 362 PTR compat_sys_mq_getsetattr 363 PTR sys_ni_syscall /* 6240, sys_vserver */ 364 + PTR compat_sys_waitid 365 PTR sys_ni_syscall /* available, was setaltroot */ 366 PTR sys_add_key 367 PTR sys_request_key
+2 -2
arch/mips/kernel/scall64-o32.S
··· 307 PTR compat_sys_statfs 308 PTR compat_sys_fstatfs /* 4100 */ 309 PTR sys_ni_syscall /* sys_ioperm */ 310 - PTR sys32_socketcall 311 PTR sys_syslog 312 PTR compat_sys_setitimer 313 PTR compat_sys_getitimer /* 4105 */ ··· 462 PTR sys_fadvise64_64 463 PTR compat_sys_statfs64 /* 4255 */ 464 PTR compat_sys_fstatfs64 465 - PTR sys32_timer_create 466 PTR compat_sys_timer_settime 467 PTR compat_sys_timer_gettime 468 PTR sys_timer_getoverrun /* 4260 */
··· 307 PTR compat_sys_statfs 308 PTR compat_sys_fstatfs /* 4100 */ 309 PTR sys_ni_syscall /* sys_ioperm */ 310 + PTR compat_sys_socketcall 311 PTR sys_syslog 312 PTR compat_sys_setitimer 313 PTR compat_sys_getitimer /* 4105 */ ··· 462 PTR sys_fadvise64_64 463 PTR compat_sys_statfs64 /* 4255 */ 464 PTR compat_sys_fstatfs64 465 + PTR compat_sys_timer_create 466 PTR compat_sys_timer_settime 467 PTR compat_sys_timer_gettime 468 PTR sys_timer_getoverrun /* 4260 */
+8
arch/mips/kernel/setup.c
··· 525 { 526 cpu_probe(); 527 prom_init(); 528 cpu_report(); 529 530 #if defined(CONFIG_VT)
··· 525 { 526 cpu_probe(); 527 prom_init(); 528 + 529 + #ifdef CONFIG_EARLY_PRINTK 530 + { 531 + extern void setup_early_printk(void); 532 + 533 + setup_early_printk(); 534 + } 535 + #endif 536 cpu_report(); 537 538 #if defined(CONFIG_VT)
+8 -5
arch/mips/lasat/lasat_board.c
··· 110 sizeof(struct lasat_eeprom_struct) - 4); 111 112 if (crc != lasat_board_info.li_eeprom_info.crc32) { 113 - prom_printf("WARNING...\nWARNING...\nEEPROM CRC does not match calculated, attempting to soldier on...\n"); 114 } 115 116 - if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) 117 - { 118 - prom_printf("WARNING...\nWARNING...\nEEPROM version %d, wanted version %d, attempting to soldier on...\n", 119 (unsigned int)lasat_board_info.li_eeprom_info.version, 120 LASAT_EEPROM_VERSION); 121 } ··· 125 cfg1 = lasat_board_info.li_eeprom_info.cfg[1]; 126 127 if ( LASAT_W0_DSCTYPE(cfg0) != 1) { 128 - prom_printf("WARNING...\nWARNING...\nInvalid configuration read from EEPROM, attempting to soldier on..."); 129 } 130 /* We have a valid configuration */ 131
··· 110 sizeof(struct lasat_eeprom_struct) - 4); 111 112 if (crc != lasat_board_info.li_eeprom_info.crc32) { 113 + printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM CRC does " 114 + "not match calculated, attempting to soldier on...\n"); 115 } 116 117 + if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) { 118 + printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM version " 119 + "%d, wanted version %d, attempting to soldier on...\n", 120 (unsigned int)lasat_board_info.li_eeprom_info.version, 121 LASAT_EEPROM_VERSION); 122 } ··· 124 cfg1 = lasat_board_info.li_eeprom_info.cfg[1]; 125 126 if ( LASAT_W0_DSCTYPE(cfg0) != 1) { 127 + printk(KERN_WARNING "WARNING...\nWARNING...\n" 128 + "Invalid configuration read from EEPROM, attempting to " 129 + "soldier on..."); 130 } 131 /* We have a valid configuration */ 132
+11 -36
arch/mips/lasat/prom.c
··· 23 #define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1) 24 #define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2) 25 26 - static void null_prom_printf(const char * fmt, ...) 27 - { 28 - } 29 - 30 static void null_prom_display(const char *string, int pos, int clear) 31 { 32 } ··· 36 } 37 38 /* these are functions provided by the bootloader */ 39 - static void (* prom_putc)(char c) = null_prom_putc; 40 - void (* prom_printf)(const char * fmt, ...) = null_prom_printf; 41 void (* prom_display)(const char *string, int pos, int clear) = 42 null_prom_display; 43 void (* prom_monitor)(void) = null_prom_monitor; 44 45 unsigned int lasat_ndelay_divider; 46 - 47 - #define PROM_PRINTFBUF_SIZE 256 48 - static char prom_printfbuf[PROM_PRINTFBUF_SIZE]; 49 - 50 - static void real_prom_printf(const char * fmt, ...) 51 - { 52 - va_list ap; 53 - int len; 54 - char *c = prom_printfbuf; 55 - int i; 56 - 57 - va_start(ap, fmt); 58 - len = vsnprintf(prom_printfbuf, PROM_PRINTFBUF_SIZE, fmt, ap); 59 - va_end(ap); 60 - 61 - /* output overflowed the buffer */ 62 - if (len < 0 || len > PROM_PRINTFBUF_SIZE) 63 - len = PROM_PRINTFBUF_SIZE; 64 - 65 - for (i=0; i < len; i++) { 66 - if (*c == '\n') 67 - prom_putc('\r'); 68 - prom_putc(*c++); 69 - } 70 - } 71 72 static void setup_prom_vectors(void) 73 { ··· 55 56 if (version >= 307) { 57 prom_display = (void *)PROM_DISPLAY_ADDR; 58 - prom_putc = (void *)PROM_PUTC_ADDR; 59 - prom_printf = real_prom_printf; 60 prom_monitor = (void *)PROM_MONITOR_ADDR; 61 } 62 - prom_printf("prom vectors set up\n"); 63 } 64 65 static struct at93c_defs at93c_defs[N_MACHTYPES] = { ··· 76 setup_prom_vectors(); 77 78 if (current_cpu_data.cputype == CPU_R5000) { 79 - prom_printf("LASAT 200 board\n"); 80 mips_machtype = MACH_LASAT_200; 81 lasat_ndelay_divider = LASAT_200_DIVIDER; 82 } else { 83 - prom_printf("LASAT 100 board\n"); 84 mips_machtype = MACH_LASAT_100; 85 lasat_ndelay_divider = LASAT_100_DIVIDER; 86 }
··· 23 #define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1) 24 #define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2) 25 26 static void null_prom_display(const char *string, int pos, int clear) 27 { 28 } ··· 40 } 41 42 /* these are functions provided by the bootloader */ 43 + static void (* __prom_putc)(char c) = null_prom_putc; 44 + 45 + void prom_putchar(char c) 46 + { 47 + __prom_putc(c); 48 + } 49 + 50 void (* prom_display)(const char *string, int pos, int clear) = 51 null_prom_display; 52 void (* prom_monitor)(void) = null_prom_monitor; 53 54 unsigned int lasat_ndelay_divider; 55 56 static void setup_prom_vectors(void) 57 { ··· 79 80 if (version >= 307) { 81 prom_display = (void *)PROM_DISPLAY_ADDR; 82 + __prom_putc = (void *)PROM_PUTC_ADDR; 83 prom_monitor = (void *)PROM_MONITOR_ADDR; 84 } 85 + printk("prom vectors set up\n"); 86 } 87 88 static struct at93c_defs at93c_defs[N_MACHTYPES] = { ··· 101 setup_prom_vectors(); 102 103 if (current_cpu_data.cputype == CPU_R5000) { 104 + printk("LASAT 200 board\n"); 105 mips_machtype = MACH_LASAT_200; 106 lasat_ndelay_divider = LASAT_200_DIVIDER; 107 } else { 108 + printk("LASAT 100 board\n"); 109 mips_machtype = MACH_LASAT_100; 110 lasat_ndelay_divider = LASAT_100_DIVIDER; 111 }
-1
arch/mips/lasat/prom.h
··· 2 #define PROM_H 3 extern void (* prom_display)(const char *string, int pos, int clear); 4 extern void (* prom_monitor)(void); 5 - extern void (* prom_printf)(const char * fmt, ...); 6 #endif
··· 2 #define PROM_H 3 extern void (* prom_display)(const char *string, int pos, int clear); 4 extern void (* prom_monitor)(void); 5 #endif
+1 -2
arch/mips/lasat/setup.c
··· 116 117 void __init plat_timer_setup(struct irqaction *irq) 118 { 119 - write_c0_compare( read_c0_count() + mips_hpt_frequency / HZ); 120 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); 121 } 122 ··· 178 /* Switch from prom exception handler to normal mode */ 179 change_c0_status(ST0_BEV,0); 180 181 - prom_printf("Lasat specific initialization complete\n"); 182 }
··· 116 117 void __init plat_timer_setup(struct irqaction *irq) 118 { 119 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); 120 } 121 ··· 179 /* Switch from prom exception handler to normal mode */ 180 change_c0_status(ST0_BEV,0); 181 182 + pr_info("Lasat specific initialization complete\n"); 183 }
+2 -2
arch/mips/lib/Makefile
··· 2 # Makefile for MIPS-specific library files.. 3 # 4 5 - lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o promlib.o \ 6 - strlen_user.o strncpy_user.o strnlen_user.o uncached.o 7 8 obj-y += iomap.o 9 obj-$(CONFIG_PCI) += iomap-pci.o
··· 2 # Makefile for MIPS-specific library files.. 3 # 4 5 + lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o strlen_user.o \ 6 + strncpy_user.o strnlen_user.o uncached.o 7 8 obj-y += iomap.o 9 obj-$(CONFIG_PCI) += iomap-pci.o
-24
arch/mips/lib/promlib.c
··· 1 - #include <stdarg.h> 2 - #include <linux/kernel.h> 3 - 4 - extern void prom_putchar(char); 5 - 6 - void prom_printf(char *fmt, ...) 7 - { 8 - va_list args; 9 - char ppbuf[1024]; 10 - char *bptr; 11 - 12 - va_start(args, fmt); 13 - vsprintf(ppbuf, fmt, args); 14 - 15 - bptr = ppbuf; 16 - 17 - while (*bptr != 0) { 18 - if (*bptr == '\n') 19 - prom_putchar('\r'); 20 - 21 - prom_putchar(*bptr++); 22 - } 23 - va_end(args); 24 - }
···
+3 -1
arch/mips/mips-boards/generic/Makefile
··· 18 # Makefile for the MIPS boards generic routines under Linux. 19 # 20 21 - obj-y := reset.o display.o init.o memory.o printf.o \ 22 cmdline.o time.o 23 obj-$(CONFIG_PCI) += pci.o 24 obj-$(CONFIG_KGDB) += gdb_hook.o
··· 18 # Makefile for the MIPS boards generic routines under Linux. 19 # 20 21 + obj-y := reset.o display.o init.o memory.o \ 22 cmdline.o time.o 23 + 24 + obj-$(CONFIG_EARLY_PRINTK) += console.o 25 obj-$(CONFIG_PCI) += pci.o 26 obj-$(CONFIG_KGDB) += gdb_hook.o
+5 -4
arch/mips/mips-boards/generic/init.c
··· 167 flow = 'r'; 168 sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 169 strcat (prom_getcmdline(), console_string); 170 - prom_printf("Config serial console:%s\n", console_string); 171 } 172 } 173 #endif ··· 210 generic_getDebugChar = rs_getDebugChar; 211 } 212 213 - prom_printf("KGDB: Using serial line /dev/ttyS%d at %d for session, " 214 - "please connect your debugger\n", line ? 1 : 0, speed); 215 216 { 217 char *s; ··· 383 board_nmi_handler_setup = mips_nmi_setup; 384 board_ejtag_handler_setup = mips_ejtag_setup; 385 386 - prom_printf("\nLINUX started...\n"); 387 prom_init_cmdline(); 388 prom_meminit(); 389 #ifdef CONFIG_SERIAL_8250_CONSOLE
··· 167 flow = 'r'; 168 sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 169 strcat (prom_getcmdline(), console_string); 170 + pr_info("Config serial console:%s\n", console_string); 171 } 172 } 173 #endif ··· 210 generic_getDebugChar = rs_getDebugChar; 211 } 212 213 + pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " 214 + "session, please connect your debugger\n", 215 + line ? 1 : 0, speed); 216 217 { 218 char *s; ··· 382 board_nmi_handler_setup = mips_nmi_setup; 383 board_ejtag_handler_setup = mips_ejtag_setup; 384 385 + pr_info("\nLINUX started...\n"); 386 prom_init_cmdline(); 387 prom_meminit(); 388 #ifdef CONFIG_SERIAL_8250_CONSOLE
+6 -5
arch/mips/mips-boards/generic/memory.c
··· 59 /* otherwise look in the environment */ 60 memsize_str = prom_getenv("memsize"); 61 if (!memsize_str) { 62 - prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); 63 physical_memsize = 0x02000000; 64 } else { 65 #ifdef DEBUG 66 - prom_printf("prom_memsize = %s\n", memsize_str); 67 #endif 68 physical_memsize = simple_strtol(memsize_str, NULL, 0); 69 } ··· 142 struct prom_pmemblock *p; 143 144 #ifdef DEBUG 145 - prom_printf("YAMON MEMORY DESCRIPTOR dump:\n"); 146 p = prom_getmdesc(); 147 while (p->size) { 148 int i = 0; 149 - prom_printf("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", 150 - i, p, p->base, p->size, mtypes[p->type]); 151 p++; 152 i++; 153 }
··· 59 /* otherwise look in the environment */ 60 memsize_str = prom_getenv("memsize"); 61 if (!memsize_str) { 62 + printk(KERN_WARNING 63 + "memsize not set in boot prom, set to default (32Mb)\n"); 64 physical_memsize = 0x02000000; 65 } else { 66 #ifdef DEBUG 67 + pr_debug("prom_memsize = %s\n", memsize_str); 68 #endif 69 physical_memsize = simple_strtol(memsize_str, NULL, 0); 70 } ··· 141 struct prom_pmemblock *p; 142 143 #ifdef DEBUG 144 + pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); 145 p = prom_getmdesc(); 146 while (p->size) { 147 int i = 0; 148 + pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", 149 + i, p, p->base, p->size, mtypes[p->type]); 150 p++; 151 i++; 152 }
+1 -11
arch/mips/mips-boards/generic/printf.c arch/mips/mips-boards/generic/console.c
··· 17 * 18 * Putting things on the screen/serial line using YAMONs facilities. 19 */ 20 #include <linux/init.h> 21 - #include <linux/kernel.h> 22 #include <linux/serial_reg.h> 23 - #include <linux/spinlock.h> 24 #include <asm/io.h> 25 26 #ifdef CONFIG_MIPS_ATLAS ··· 66 67 return 1; 68 } 69 - 70 - char prom_getchar(void) 71 - { 72 - while (!(serial_in(UART_LSR) & UART_LSR_DR)) 73 - ; 74 - 75 - return serial_in(UART_RX); 76 - } 77 -
··· 17 * 18 * Putting things on the screen/serial line using YAMONs facilities. 19 */ 20 + #include <linux/console.h> 21 #include <linux/init.h> 22 #include <linux/serial_reg.h> 23 #include <asm/io.h> 24 25 #ifdef CONFIG_MIPS_ATLAS ··· 67 68 return 1; 69 }
-3
arch/mips/mips-boards/generic/time.c
··· 295 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 296 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 297 #endif 298 - 299 - /* to generate the first timer interrupt */ 300 - write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); 301 }
··· 295 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 296 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 297 #endif 298 }
+5 -1
arch/mips/mips-boards/sim/Makefile
··· 1 # 2 # Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 3 # 4 # This program is free software; you can distribute it and/or modify it 5 # under the terms of the GNU General Public License (Version 2) as ··· 17 # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 # 19 20 - obj-y := sim_setup.o sim_mem.o sim_time.o sim_printf.o sim_int.o sim_cmdline.o 21 obj-$(CONFIG_SMP) += sim_smp.o
··· 1 # 2 # Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 3 + # Copyright (C) 2007 MIPS Technologies, Inc. 4 + # written by Ralf Baechle (ralf@linux-mips.org) 5 # 6 # This program is free software; you can distribute it and/or modify it 7 # under the terms of the GNU General Public License (Version 2) as ··· 15 # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 # 17 18 + obj-y := sim_setup.o sim_mem.o sim_time.o sim_int.o sim_cmdline.o 19 + 20 + obj-$(CONFIG_EARLY_PRINTK) += sim_console.o 21 obj-$(CONFIG_SMP) += sim_smp.o
+1 -1
arch/mips/mips-boards/sim/sim_mem.c
··· 46 unsigned int memsize; 47 48 memsize = 0x02000000; 49 - prom_printf("Setting default memory size 0x%08x\n", memsize); 50 51 memset(mdesc, 0, sizeof(mdesc)); 52
··· 46 unsigned int memsize; 47 48 memsize = 0x02000000; 49 + pr_info("Setting default memory size 0x%08x\n", memsize); 50 51 memset(mdesc, 0, sizeof(mdesc)); 52
+5 -39
arch/mips/mips-boards/sim/sim_printf.c arch/mips/mips-boards/sim/sim_console.c
··· 1 /* 2 - * Carsten Langgaard, carstenl@mips.com 3 - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 4 - * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. ··· 12 * with this program; if not, write to the Free Software Foundation, Inc., 13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 14 * 15 - * Putting things on the screen/serial line using YAMONs facilities. 16 */ 17 #include <linux/init.h> 18 - #include <linux/kernel.h> 19 #include <linux/serial_reg.h> 20 - #include <linux/spinlock.h> 21 #include <asm/io.h> 22 - #include <asm/system.h> 23 24 static inline unsigned int serial_in(int offset) 25 { ··· 31 outb(value, 0x3f8 + offset); 32 } 33 34 - int putPromChar(char c) 35 { 36 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) 37 ; 38 39 serial_out(UART_TX, c); 40 - 41 - return 1; 42 - } 43 - 44 - char getPromChar(void) 45 - { 46 - while (!(serial_in(UART_LSR) & 1)) 47 - ; 48 - 49 - return serial_in(UART_RX); 50 - } 51 - 52 - void prom_printf(char *fmt, ...) 53 - { 54 - va_list args; 55 - int l; 56 - char *p, *buf_end; 57 - char buf[1024]; 58 - 59 - va_start(args, fmt); 60 - l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */ 61 - va_end(args); 62 - 63 - buf_end = buf + l; 64 - 65 - for (p = buf; p < buf_end; p++) { 66 - /* Crude cr/nl handling is better than none */ 67 - if (*p == '\n') 68 - putPromChar('\r'); 69 - putPromChar(*p); 70 - } 71 }
··· 1 /* 2 * This program is free software; you can distribute it and/or modify it 3 * under the terms of the GNU General Public License (Version 2) as 4 * published by the Free Software Foundation. ··· 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 18 + * Carsten Langgaard, carstenl@mips.com 19 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 20 + * Copyright (C) 2007 MIPS Technologies, Inc. 21 + * written by Ralf Baechle 22 */ 23 #include <linux/init.h> 24 #include <linux/serial_reg.h> 25 #include <asm/io.h> 26 27 static inline unsigned int serial_in(int offset) 28 { ··· 34 outb(value, 0x3f8 + offset); 35 } 36 37 + void __init prom_putchar(char c) 38 { 39 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) 40 ; 41 42 serial_out(UART_TX, c); 43 }
+3 -3
arch/mips/mips-boards/sim/sim_setup.c
··· 55 serial_init(); 56 57 board_time_init = sim_time_init; 58 - prom_printf("Linux started...\n"); 59 60 #ifdef CONFIG_MIPS_MT_SMP 61 sanitize_tlb_entries(); ··· 66 { 67 set_io_port_base(0xbfd00000); 68 69 - prom_printf("\nLINUX started...\n"); 70 prom_init_cmdline(); 71 prom_meminit(); 72 } ··· 91 s.timeout = 4; 92 93 if (early_serial_setup(&s) != 0) { 94 - prom_printf(KERN_ERR "Serial setup failed!\n"); 95 } 96 97 #endif
··· 55 serial_init(); 56 57 board_time_init = sim_time_init; 58 + pr_info("Linux started...\n"); 59 60 #ifdef CONFIG_MIPS_MT_SMP 61 sanitize_tlb_entries(); ··· 66 { 67 set_io_port_base(0xbfd00000); 68 69 + pr_info("\nLINUX started...\n"); 70 prom_init_cmdline(); 71 prom_meminit(); 72 } ··· 91 s.timeout = 4; 92 93 if (early_serial_setup(&s) != 0) { 94 + printk(KERN_ERR "Serial setup failed!\n"); 95 } 96 97 #endif
-3
arch/mips/mips-boards/sim/sim_time.c
··· 199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; 200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 201 #endif 202 - 203 - /* to generate the first timer interrupt */ 204 - write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); 205 }
··· 199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; 200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 201 #endif 202 }
+62 -62
arch/mips/mm/cerr-sb1.c
··· 77 static inline void breakout_errctl(unsigned int val) 78 { 79 if (val & CP0_ERRCTL_RECOVERABLE) 80 - prom_printf(" recoverable"); 81 if (val & CP0_ERRCTL_DCACHE) 82 - prom_printf(" dcache"); 83 if (val & CP0_ERRCTL_ICACHE) 84 - prom_printf(" icache"); 85 if (val & CP0_ERRCTL_MULTIBUS) 86 - prom_printf(" multiple-buserr"); 87 - prom_printf("\n"); 88 } 89 90 static inline void breakout_cerri(unsigned int val) 91 { 92 if (val & CP0_CERRI_TAG_PARITY) 93 - prom_printf(" tag-parity"); 94 if (val & CP0_CERRI_DATA_PARITY) 95 - prom_printf(" data-parity"); 96 if (val & CP0_CERRI_EXTERNAL) 97 - prom_printf(" external"); 98 - prom_printf("\n"); 99 } 100 101 static inline void breakout_cerrd(unsigned int val) 102 { 103 switch (val & CP0_CERRD_CAUSES) { 104 case CP0_CERRD_LOAD: 105 - prom_printf(" load,"); 106 break; 107 case CP0_CERRD_STORE: 108 - prom_printf(" store,"); 109 break; 110 case CP0_CERRD_FILLWB: 111 - prom_printf(" fill/wb,"); 112 break; 113 case CP0_CERRD_COHERENCY: 114 - prom_printf(" coherency,"); 115 break; 116 case CP0_CERRD_DUPTAG: 117 - prom_printf(" duptags,"); 118 break; 119 default: 120 - prom_printf(" NO CAUSE,"); 121 break; 122 } 123 if (!(val & CP0_CERRD_TYPES)) 124 - prom_printf(" NO TYPE"); 125 else { 126 if (val & CP0_CERRD_MULTIPLE) 127 - prom_printf(" multi-err"); 128 if (val & CP0_CERRD_TAG_STATE) 129 - prom_printf(" tag-state"); 130 if (val & CP0_CERRD_TAG_ADDRESS) 131 - prom_printf(" tag-address"); 132 if (val & CP0_CERRD_DATA_SBE) 133 - prom_printf(" data-SBE"); 134 if (val & CP0_CERRD_DATA_DBE) 135 - prom_printf(" data-DBE"); 136 if (val & CP0_CERRD_EXTERNAL) 137 - prom_printf(" external"); 138 } 139 - prom_printf("\n"); 140 } 141 142 #ifndef CONFIG_SIBYTE_BUS_WATCHER ··· 157 l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG); 158 #endif 159 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); 160 - prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); 161 - prom_printf("\nLast recorded signature:\n"); 162 - prom_printf("Request %02x from %d, answered by %d with Dcode %d\n", 163 (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), 164 (int)(G_SCD_BERR_TID(status) >> 6), 165 (int)G_SCD_BERR_RID(status), 166 (int)G_SCD_BERR_DCODE(status)); 167 #ifdef DUMP_L2_ECC_TAG_ON_ERROR 168 - prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag); 169 #endif 170 } else { 171 - prom_printf("Bus watcher indicates no error\n"); 172 } 173 } 174 #else ··· 187 #else 188 csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); 189 #endif 190 - prom_printf("Trace buffer frozen\n"); 191 #endif 192 193 - prom_printf("Cache error exception on CPU %x:\n", 194 - (read_c0_prid() >> 25) & 0x7); 195 196 __asm__ __volatile__ ( 197 " .set push\n\t" ··· 209 "=r" (dpahi), "=r" (dpalo), "=r" (eepc)); 210 211 cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo; 212 - prom_printf(" c0_errorepc == %08x\n", eepc); 213 - prom_printf(" c0_errctl == %08x", errctl); 214 breakout_errctl(errctl); 215 if (errctl & CP0_ERRCTL_ICACHE) { 216 - prom_printf(" c0_cerr_i == %08x", cerr_i); 217 breakout_cerri(cerr_i); 218 if (CP0_CERRI_IDX_VALID(cerr_i)) { 219 /* Check index of EPC, allowing for delay slot */ 220 if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) && 221 ((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4))) 222 - prom_printf(" cerr_i idx doesn't match eepc\n"); 223 else { 224 res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK, 225 (cerr_i & CP0_CERRI_DATA) != 0); 226 if (!(res & cerr_i)) 227 - prom_printf("...didn't see indicated icache problem\n"); 228 } 229 } 230 } 231 if (errctl & CP0_ERRCTL_DCACHE) { 232 - prom_printf(" c0_cerr_d == %08x", cerr_d); 233 breakout_cerrd(cerr_d); 234 if (CP0_CERRD_DPA_VALID(cerr_d)) { 235 - prom_printf(" c0_cerr_dpa == %010llx\n", cerr_dpa); 236 if (!CP0_CERRD_IDX_VALID(cerr_d)) { 237 res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK, 238 (cerr_d & CP0_CERRD_DATA) != 0); 239 if (!(res & cerr_d)) 240 - prom_printf("...didn't see indicated dcache problem\n"); 241 } else { 242 if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK)) 243 - prom_printf(" cerr_d idx doesn't match cerr_dpa\n"); 244 else { 245 res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK, 246 (cerr_d & CP0_CERRD_DATA) != 0); 247 if (!(res & cerr_d)) 248 - prom_printf("...didn't see indicated problem\n"); 249 } 250 } 251 } ··· 334 uint8_t lru; 335 int res = 0; 336 337 - prom_printf("Icache index 0x%04x ", addr); 338 for (way = 0; way < 4; way++) { 339 /* Index-load-tag-I */ 340 __asm__ __volatile__ ( ··· 354 taglo = ((unsigned long long)taglohi << 32) | taglolo; 355 if (way == 0) { 356 lru = (taghi >> 14) & 0xff; 357 - prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", 358 ((addr >> 5) & 0x3), /* bank */ 359 ((addr >> 7) & 0x3f), /* index */ 360 (lru & 0x3), ··· 369 if (valid) { 370 tlo_tmp = taglo & 0xfff3ff; 371 if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) { 372 - prom_printf(" ** bad parity in VTag0/G/ASID\n"); 373 res |= CP0_CERRI_TAG_PARITY; 374 } 375 if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) { 376 - prom_printf(" ** bad parity in R/VTag1\n"); 377 res |= CP0_CERRI_TAG_PARITY; 378 } 379 } 380 if (valid ^ ((taghi >> 27) & 1)) { 381 - prom_printf(" ** bad parity for valid bit\n"); 382 res |= CP0_CERRI_TAG_PARITY; 383 } 384 - prom_printf(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n", 385 way, va, valid, taghi, taglo); 386 387 if (data) { ··· 407 : "r" ((way << 13) | addr | (offset << 3))); 408 predecode = (datahi >> 8) & 0xff; 409 if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { 410 - prom_printf(" ** bad parity in predecode\n"); 411 res |= CP0_CERRI_DATA_PARITY; 412 } 413 /* XXXKW should/could check predecode bits themselves */ 414 if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) { 415 - prom_printf(" ** bad parity in instruction a\n"); 416 res |= CP0_CERRI_DATA_PARITY; 417 } 418 if ((datahi & 0xf) ^ inst_parity(instb)) { 419 - prom_printf(" ** bad parity in instruction b\n"); 420 res |= CP0_CERRI_DATA_PARITY; 421 } 422 - prom_printf(" %05X-%08X%08X", datahi, insta, instb); 423 } 424 - prom_printf("\n"); 425 } 426 } 427 return res; ··· 489 uint8_t ecc, lru; 490 int res = 0; 491 492 - prom_printf("Dcache index 0x%04x ", addr); 493 for (way = 0; way < 4; way++) { 494 __asm__ __volatile__ ( 495 " .set push\n\t" ··· 509 pa = (taglo & 0xFFFFFFE000ULL) | addr; 510 if (way == 0) { 511 lru = (taghi >> 14) & 0xff; 512 - prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", 513 ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ 514 ((addr >> 6) & 0x3f), /* index */ 515 (lru & 0x3), ··· 519 } 520 state = (taghi >> 25) & 0x1f; 521 valid = DC_TAG_VALID(state); 522 - prom_printf(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n", 523 way, pa, dc_state_str(state), state, taghi, taglo); 524 if (valid) { 525 if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) { 526 - prom_printf(" ** bad parity in PTag1\n"); 527 res |= CP0_CERRD_TAG_ADDRESS; 528 } 529 if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) { 530 - prom_printf(" ** bad parity in PTag0\n"); 531 res |= CP0_CERRD_TAG_ADDRESS; 532 } 533 } else { ··· 567 } 568 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; 569 } 570 - prom_printf(" %02X-%016llX", datahi, datalo); 571 } 572 - prom_printf("\n"); 573 if (bad_ecc) 574 - prom_printf(" dwords w/ bad ECC: %d %d %d %d\n", 575 - !!(bad_ecc & 8), !!(bad_ecc & 4), 576 - !!(bad_ecc & 2), !!(bad_ecc & 1)); 577 } 578 } 579 return res;
··· 77 static inline void breakout_errctl(unsigned int val) 78 { 79 if (val & CP0_ERRCTL_RECOVERABLE) 80 + printk(" recoverable"); 81 if (val & CP0_ERRCTL_DCACHE) 82 + printk(" dcache"); 83 if (val & CP0_ERRCTL_ICACHE) 84 + printk(" icache"); 85 if (val & CP0_ERRCTL_MULTIBUS) 86 + printk(" multiple-buserr"); 87 + printk("\n"); 88 } 89 90 static inline void breakout_cerri(unsigned int val) 91 { 92 if (val & CP0_CERRI_TAG_PARITY) 93 + printk(" tag-parity"); 94 if (val & CP0_CERRI_DATA_PARITY) 95 + printk(" data-parity"); 96 if (val & CP0_CERRI_EXTERNAL) 97 + printk(" external"); 98 + printk("\n"); 99 } 100 101 static inline void breakout_cerrd(unsigned int val) 102 { 103 switch (val & CP0_CERRD_CAUSES) { 104 case CP0_CERRD_LOAD: 105 + printk(" load,"); 106 break; 107 case CP0_CERRD_STORE: 108 + printk(" store,"); 109 break; 110 case CP0_CERRD_FILLWB: 111 + printk(" fill/wb,"); 112 break; 113 case CP0_CERRD_COHERENCY: 114 + printk(" coherency,"); 115 break; 116 case CP0_CERRD_DUPTAG: 117 + printk(" duptags,"); 118 break; 119 default: 120 + printk(" NO CAUSE,"); 121 break; 122 } 123 if (!(val & CP0_CERRD_TYPES)) 124 + printk(" NO TYPE"); 125 else { 126 if (val & CP0_CERRD_MULTIPLE) 127 + printk(" multi-err"); 128 if (val & CP0_CERRD_TAG_STATE) 129 + printk(" tag-state"); 130 if (val & CP0_CERRD_TAG_ADDRESS) 131 + printk(" tag-address"); 132 if (val & CP0_CERRD_DATA_SBE) 133 + printk(" data-SBE"); 134 if (val & CP0_CERRD_DATA_DBE) 135 + printk(" data-DBE"); 136 if (val & CP0_CERRD_EXTERNAL) 137 + printk(" external"); 138 } 139 + printk("\n"); 140 } 141 142 #ifndef CONFIG_SIBYTE_BUS_WATCHER ··· 157 l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG); 158 #endif 159 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); 160 + printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); 161 + printk("\nLast recorded signature:\n"); 162 + printk("Request %02x from %d, answered by %d with Dcode %d\n", 163 (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), 164 (int)(G_SCD_BERR_TID(status) >> 6), 165 (int)G_SCD_BERR_RID(status), 166 (int)G_SCD_BERR_DCODE(status)); 167 #ifdef DUMP_L2_ECC_TAG_ON_ERROR 168 + printk("Last L2 tag w/ bad ECC: %016llx\n", l2_tag); 169 #endif 170 } else { 171 + printk("Bus watcher indicates no error\n"); 172 } 173 } 174 #else ··· 187 #else 188 csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); 189 #endif 190 + printk("Trace buffer frozen\n"); 191 #endif 192 193 + printk("Cache error exception on CPU %x:\n", 194 + (read_c0_prid() >> 25) & 0x7); 195 196 __asm__ __volatile__ ( 197 " .set push\n\t" ··· 209 "=r" (dpahi), "=r" (dpalo), "=r" (eepc)); 210 211 cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo; 212 + printk(" c0_errorepc == %08x\n", eepc); 213 + printk(" c0_errctl == %08x", errctl); 214 breakout_errctl(errctl); 215 if (errctl & CP0_ERRCTL_ICACHE) { 216 + printk(" c0_cerr_i == %08x", cerr_i); 217 breakout_cerri(cerr_i); 218 if (CP0_CERRI_IDX_VALID(cerr_i)) { 219 /* Check index of EPC, allowing for delay slot */ 220 if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) && 221 ((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4))) 222 + printk(" cerr_i idx doesn't match eepc\n"); 223 else { 224 res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK, 225 (cerr_i & CP0_CERRI_DATA) != 0); 226 if (!(res & cerr_i)) 227 + printk("...didn't see indicated icache problem\n"); 228 } 229 } 230 } 231 if (errctl & CP0_ERRCTL_DCACHE) { 232 + printk(" c0_cerr_d == %08x", cerr_d); 233 breakout_cerrd(cerr_d); 234 if (CP0_CERRD_DPA_VALID(cerr_d)) { 235 + printk(" c0_cerr_dpa == %010llx\n", cerr_dpa); 236 if (!CP0_CERRD_IDX_VALID(cerr_d)) { 237 res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK, 238 (cerr_d & CP0_CERRD_DATA) != 0); 239 if (!(res & cerr_d)) 240 + printk("...didn't see indicated dcache problem\n"); 241 } else { 242 if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK)) 243 + printk(" cerr_d idx doesn't match cerr_dpa\n"); 244 else { 245 res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK, 246 (cerr_d & CP0_CERRD_DATA) != 0); 247 if (!(res & cerr_d)) 248 + printk("...didn't see indicated problem\n"); 249 } 250 } 251 } ··· 334 uint8_t lru; 335 int res = 0; 336 337 + printk("Icache index 0x%04x ", addr); 338 for (way = 0; way < 4; way++) { 339 /* Index-load-tag-I */ 340 __asm__ __volatile__ ( ··· 354 taglo = ((unsigned long long)taglohi << 32) | taglolo; 355 if (way == 0) { 356 lru = (taghi >> 14) & 0xff; 357 + printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", 358 ((addr >> 5) & 0x3), /* bank */ 359 ((addr >> 7) & 0x3f), /* index */ 360 (lru & 0x3), ··· 369 if (valid) { 370 tlo_tmp = taglo & 0xfff3ff; 371 if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) { 372 + printk(" ** bad parity in VTag0/G/ASID\n"); 373 res |= CP0_CERRI_TAG_PARITY; 374 } 375 if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) { 376 + printk(" ** bad parity in R/VTag1\n"); 377 res |= CP0_CERRI_TAG_PARITY; 378 } 379 } 380 if (valid ^ ((taghi >> 27) & 1)) { 381 + printk(" ** bad parity for valid bit\n"); 382 res |= CP0_CERRI_TAG_PARITY; 383 } 384 + printk(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n", 385 way, va, valid, taghi, taglo); 386 387 if (data) { ··· 407 : "r" ((way << 13) | addr | (offset << 3))); 408 predecode = (datahi >> 8) & 0xff; 409 if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { 410 + printk(" ** bad parity in predecode\n"); 411 res |= CP0_CERRI_DATA_PARITY; 412 } 413 /* XXXKW should/could check predecode bits themselves */ 414 if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) { 415 + printk(" ** bad parity in instruction a\n"); 416 res |= CP0_CERRI_DATA_PARITY; 417 } 418 if ((datahi & 0xf) ^ inst_parity(instb)) { 419 + printk(" ** bad parity in instruction b\n"); 420 res |= CP0_CERRI_DATA_PARITY; 421 } 422 + printk(" %05X-%08X%08X", datahi, insta, instb); 423 } 424 + printk("\n"); 425 } 426 } 427 return res; ··· 489 uint8_t ecc, lru; 490 int res = 0; 491 492 + printk("Dcache index 0x%04x ", addr); 493 for (way = 0; way < 4; way++) { 494 __asm__ __volatile__ ( 495 " .set push\n\t" ··· 509 pa = (taglo & 0xFFFFFFE000ULL) | addr; 510 if (way == 0) { 511 lru = (taghi >> 14) & 0xff; 512 + printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", 513 ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ 514 ((addr >> 6) & 0x3f), /* index */ 515 (lru & 0x3), ··· 519 } 520 state = (taghi >> 25) & 0x1f; 521 valid = DC_TAG_VALID(state); 522 + printk(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n", 523 way, pa, dc_state_str(state), state, taghi, taglo); 524 if (valid) { 525 if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) { 526 + printk(" ** bad parity in PTag1\n"); 527 res |= CP0_CERRD_TAG_ADDRESS; 528 } 529 if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) { 530 + printk(" ** bad parity in PTag0\n"); 531 res |= CP0_CERRD_TAG_ADDRESS; 532 } 533 } else { ··· 567 } 568 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; 569 } 570 + printk(" %02X-%016llX", datahi, datalo); 571 } 572 + printk("\n"); 573 if (bad_ecc) 574 + printk(" dwords w/ bad ECC: %d %d %d %d\n", 575 + !!(bad_ecc & 8), !!(bad_ecc & 4), 576 + !!(bad_ecc & 2), !!(bad_ecc & 1)); 577 } 578 } 579 return res;
+1 -1
arch/mips/mm/dma-default.c
··· 295 296 /* Make sure that gcc doesn't leave the empty loop body. */ 297 for (i = 0; i < nelems; i++, sg++) { 298 - if (!plat_device_is_coherent(dev)) 299 __dma_sync((unsigned long)page_address(sg->page), 300 sg->length, direction); 301 plat_unmap_dma_mem(sg->dma_address);
··· 295 296 /* Make sure that gcc doesn't leave the empty loop body. */ 297 for (i = 0; i < nelems; i++, sg++) { 298 + if (cpu_is_noncoherent_r10000(dev)) 299 __dma_sync((unsigned long)page_address(sg->page), 300 sg->length, direction); 301 plat_unmap_dma_mem(sg->dma_address);
-5
arch/mips/momentum/jaguar_atx/ja-console.c
··· 74 uart->iu_thr = c; 75 } 76 77 - char __init prom_getchar(void) 78 - { 79 - return 0; 80 - } 81 - 82 static void inline ja_console_probe(void) 83 { 84 struct uart_port up;
··· 74 uart->iu_thr = c; 75 } 76 77 static void inline ja_console_probe(void) 78 { 79 struct uart_port up;
+2
arch/mips/oprofile/op_model_mipsxx.c
··· 223 switch (current_cpu_data.cputype) { 224 case CPU_R10000: 225 counters = 2; 226 227 case CPU_R12000: 228 case CPU_R14000: 229 counters = 4; 230 231 default: 232 counters = __n_counters();
··· 223 switch (current_cpu_data.cputype) { 224 case CPU_R10000: 225 counters = 2; 226 + break; 227 228 case CPU_R12000: 229 case CPU_R14000: 230 counters = 4; 231 + break; 232 233 default: 234 counters = __n_counters();
+4 -10
arch/mips/pci/fixup-jmr3927.c
··· 38 { 39 unsigned char irq = pin; 40 41 /* IRQ rotation (PICMG) */ 42 irq--; /* 0-3 */ 43 if (dev->bus->parent == NULL && ··· 96 int pcibios_plat_dev_init(struct pci_dev *dev) 97 { 98 return 0; 99 - } 100 - 101 - int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 102 - { 103 - /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ 104 - if (!(dev->vendor == PCI_VENDOR_ID_EFAR && 105 - dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)) 106 - return pci_get_irq(dev, pin); 107 - 108 - dev->irq = irq; 109 }
··· 38 { 39 unsigned char irq = pin; 40 41 + /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ 42 + if (dev->vendor == PCI_VENDOR_ID_EFAR && 43 + dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1) 44 + return irq; 45 /* IRQ rotation (PICMG) */ 46 irq--; /* 0-3 */ 47 if (dev->bus->parent == NULL && ··· 92 int pcibios_plat_dev_init(struct pci_dev *dev) 93 { 94 return 0; 95 }
+2
arch/mips/pci/fixup-sni.c
··· 14 #include <asm/mipsregs.h> 15 #include <asm/sni.h> 16 17 /* 18 * PCIMT Shortcuts ... 19 */
··· 14 #include <asm/mipsregs.h> 15 #include <asm/sni.h> 16 17 + #include <irq.h> 18 + 19 /* 20 * PCIMT Shortcuts ... 21 */
+5 -1
arch/mips/pci/ops-au1000.c
··· 172 error = -1; 173 DBG("Au1x Master Abort\n"); 174 } else if ((status >> 28) & 0xf) { 175 - DBG("PCI ERR detected: status %x\n", status); 176 *data = 0xffffffff; 177 error = -1; 178 }
··· 172 error = -1; 173 DBG("Au1x Master Abort\n"); 174 } else if ((status >> 28) & 0xf) { 175 + DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf)); 176 + 177 + /* clear errors */ 178 + au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); 179 + 180 *data = 0xffffffff; 181 error = -1; 182 }
+1 -1
arch/mips/philips/pnx8550/common/prom.c
··· 112 113 extern int pnx8550_console_port; 114 115 - /* used by prom_printf */ 116 void prom_putchar(char c) 117 { 118 if (pnx8550_console_port != -1) {
··· 112 113 extern int pnx8550_console_port; 114 115 + /* used by early printk */ 116 void prom_putchar(char c) 117 { 118 if (pnx8550_console_port != -1) {
+3 -6
arch/mips/philips/pnx8550/common/setup.c
··· 41 #include <uart.h> 42 #include <nand.h> 43 44 - extern void prom_printf(char *fmt, ...); 45 - 46 extern void __init board_setup(void); 47 extern void pnx8550_machine_restart(char *); 48 extern void pnx8550_machine_halt(void); ··· 49 extern struct resource iomem_resource; 50 extern void pnx8550_time_init(void); 51 extern void rs_kgdb_hook(int tty_no); 52 - extern void prom_printf(char *fmt, ...); 53 extern char *prom_getcmdline(void); 54 55 struct resource standard_io_resources[] = { ··· 138 argptr += strlen("console=ttyS"); 139 pnx8550_console_port = *argptr == '0' ? 0 : 1; 140 141 - /* We must initialize the UART (console) before prom_printf */ 142 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ 143 ip3106_lcr(UART_BASE, pnx8550_console_port) = 144 PNX8XXX_UART_LCR_8BIT; ··· 152 argptr += strlen("kgdb=ttyS"); 153 line = *argptr == '0' ? 0 : 1; 154 rs_kgdb_hook(line); 155 - prom_printf("KGDB: Using ttyS%i for session, " 156 - "please connect your debugger\n", line ? 1 : 0); 157 } 158 #endif 159 return;
··· 41 #include <uart.h> 42 #include <nand.h> 43 44 extern void __init board_setup(void); 45 extern void pnx8550_machine_restart(char *); 46 extern void pnx8550_machine_halt(void); ··· 51 extern struct resource iomem_resource; 52 extern void pnx8550_time_init(void); 53 extern void rs_kgdb_hook(int tty_no); 54 extern char *prom_getcmdline(void); 55 56 struct resource standard_io_resources[] = { ··· 141 argptr += strlen("console=ttyS"); 142 pnx8550_console_port = *argptr == '0' ? 0 : 1; 143 144 + /* We must initialize the UART (console) before early printk */ 145 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ 146 ip3106_lcr(UART_BASE, pnx8550_console_port) = 147 PNX8XXX_UART_LCR_8BIT; ··· 155 argptr += strlen("kgdb=ttyS"); 156 line = *argptr == '0' ? 0 : 1; 157 rs_kgdb_hook(line); 158 + pr_info("KGDB: Using ttyS%i for session, " 159 + "please connect your debugger\n", line ? 1 : 0); 160 } 161 #endif 162 return;
-5
arch/mips/pmc-sierra/yosemite/py-console.c
··· 107 while ((readb_outer_space(lsr) & 0x20) == 0); 108 writeb_outer_space(thr, c); 109 } 110 - 111 - char __init prom_getchar(void) 112 - { 113 - return 0; 114 - }
··· 107 while ((readb_outer_space(lsr) & 0x20) == 0); 108 writeb_outer_space(thr, c); 109 }
+1 -34
arch/mips/sgi-ip27/ip27-console.c
··· 6 * Copyright (C) 2001, 2002 Ralf Baechle 7 */ 8 #include <linux/init.h> 9 - #include <linux/console.h> 10 - #include <linux/kdev_t.h> 11 - #include <linux/major.h> 12 - #include <linux/termios.h> 13 - #include <linux/sched.h> 14 - #include <linux/tty.h> 15 16 #include <asm/page.h> 17 #include <asm/semaphore.h> ··· 32 return &ioc3->sregs.uarta; 33 } 34 35 - void prom_putchar(char c) 36 { 37 struct ioc3_uartregs *uart = console_uart(); 38 39 while ((uart->iu_lsr & 0x20) == 0); 40 uart->iu_thr = c; 41 - } 42 - 43 - static void ioc3_console_write(struct console *con, const char *s, unsigned n) 44 - { 45 - while (n-- && *s) { 46 - if (*s == '\n') 47 - prom_putchar('\r'); 48 - prom_putchar(*s); 49 - s++; 50 - } 51 - } 52 - 53 - static struct console ioc3_console = { 54 - .name = "ioc3", 55 - .write = ioc3_console_write, 56 - .flags = CON_PRINTBUFFER | CON_BOOT, 57 - .index = -1 58 - }; 59 - 60 - __init void ip27_setup_console(void) 61 - { 62 - register_console(&ioc3_console); 63 - } 64 - 65 - void __init disable_early_printk(void) 66 - { 67 - unregister_console(&ioc3_console); 68 }
··· 6 * Copyright (C) 2001, 2002 Ralf Baechle 7 */ 8 #include <linux/init.h> 9 10 #include <asm/page.h> 11 #include <asm/semaphore.h> ··· 38 return &ioc3->sregs.uarta; 39 } 40 41 + void __init prom_putchar(char c) 42 { 43 struct ioc3_uartregs *uart = console_uart(); 44 45 while ((uart->iu_lsr & 0x20) == 0); 46 uart->iu_thr = c; 47 }
+2
arch/mips/sibyte/Kconfig
··· 116 config SIBYTE_CFE 117 bool "Booting from CFE" 118 depends on SIBYTE_SB1xxx_SOC 119 help 120 Make use of the CFE API for enumerating available memory, 121 controlling secondary CPUs, and possibly console output. ··· 132 config SIBYTE_STANDALONE 133 bool 134 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE 135 default y 136 137 config SIBYTE_STANDALONE_RAM_SIZE
··· 116 config SIBYTE_CFE 117 bool "Booting from CFE" 118 depends on SIBYTE_SB1xxx_SOC 119 + select SYS_HAS_EARLY_PRINTK 120 help 121 Make use of the CFE API for enumerating available memory, 122 controlling secondary CPUs, and possibly console output. ··· 131 config SIBYTE_STANDALONE 132 bool 133 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE 134 + select SYS_HAS_EARLY_PRINTK 135 default y 136 137 config SIBYTE_STANDALONE_RAM_SIZE
+1 -1
arch/mips/sibyte/bcm1480/irq.c
··· 420 #ifdef CONFIG_GDB_CONSOLE 421 register_gdb_console(); 422 #endif 423 - prom_printf("Waiting for GDB on UART port %d\n", kgdb_port); 424 set_debug_traps(); 425 breakpoint(); 426 }
··· 420 #ifdef CONFIG_GDB_CONSOLE 421 register_gdb_console(); 422 #endif 423 + printk("Waiting for GDB on UART port %d\n", kgdb_port); 424 set_debug_traps(); 425 breakpoint(); 426 }
+5 -5
arch/mips/sibyte/bcm1480/setup.c
··· 69 break; 70 71 default: 72 - prom_printf("Unknown part type %x\n", part_type); 73 ret = 1; 74 break; 75 } ··· 102 pass_str = "B0 (pass2)"; 103 break; 104 default: 105 - prom_printf("Unknown %s rev %x\n", soc_str, soc_pass); 106 periph_rev = 1; 107 pass_str = "Unknown Revision"; 108 break; ··· 122 soc_pass = G_SYS_REVISION(sys_rev); 123 124 if (sys_rev_decode()) { 125 - prom_printf("Restart after failure to identify SiByte chip\n"); 126 machine_restart(NULL); 127 } 128 129 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 130 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); 131 132 - prom_printf("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n", 133 soc_str, pass_str, zbbus_mhz * 2, sb1_pass); 134 - prom_printf("Board type: %s\n", get_system_type()); 135 }
··· 69 break; 70 71 default: 72 + printk("Unknown part type %x\n", part_type); 73 ret = 1; 74 break; 75 } ··· 102 pass_str = "B0 (pass2)"; 103 break; 104 default: 105 + printk("Unknown %s rev %x\n", soc_str, soc_pass); 106 periph_rev = 1; 107 pass_str = "Unknown Revision"; 108 break; ··· 122 soc_pass = G_SYS_REVISION(sys_rev); 123 124 if (sys_rev_decode()) { 125 + printk("Restart after failure to identify SiByte chip\n"); 126 machine_restart(NULL); 127 } 128 129 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 130 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); 131 132 + printk("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n", 133 soc_str, pass_str, zbbus_mhz * 2, sb1_pass); 134 + printk("Board type: %s\n", get_system_type()); 135 }
+4 -4
arch/mips/sibyte/cfe/setup.c
··· 221 goto fail; 222 } 223 initrd_end = initrd_start + initrd_size; 224 - prom_printf("Found initrd of %lx@%lx\n", initrd_size, initrd_start); 225 return 1; 226 fail: 227 - prom_printf("Bad initrd argument. Disabling initrd\n"); 228 initrd_start = 0; 229 initrd_end = 0; 230 return 1; ··· 281 } 282 if (cfe_eptseal != CFE_EPTSEAL) { 283 /* too early for panic to do any good */ 284 - prom_printf("CFE's entrypoint seal doesn't match. Spinning."); 285 while (1) ; 286 } 287 cfe_init(cfe_handle, cfe_ept); ··· 303 } else { 304 /* The loader should have set the command line */ 305 /* too early for panic to do any good */ 306 - prom_printf("LINUX_CMDLINE not defined in cfe."); 307 while (1) ; 308 } 309 }
··· 221 goto fail; 222 } 223 initrd_end = initrd_start + initrd_size; 224 + printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start); 225 return 1; 226 fail: 227 + printk("Bad initrd argument. Disabling initrd\n"); 228 initrd_start = 0; 229 initrd_end = 0; 230 return 1; ··· 281 } 282 if (cfe_eptseal != CFE_EPTSEAL) { 283 /* too early for panic to do any good */ 284 + printk("CFE's entrypoint seal doesn't match. Spinning."); 285 while (1) ; 286 } 287 cfe_init(cfe_handle, cfe_ept); ··· 303 } else { 304 /* The loader should have set the command line */ 305 /* too early for panic to do any good */ 306 + printk("LINUX_CMDLINE not defined in cfe."); 307 while (1) ; 308 } 309 }
+12 -12
arch/mips/sibyte/sb1250/setup.c
··· 67 ret = setup_bcm112x(); 68 break; 69 default: 70 - prom_printf("Unknown SOC type %x\n", soc_type); 71 ret = 1; 72 break; 73 } ··· 112 pass_str = "A0-A6"; 113 war_pass = K_SYS_REVISION_BCM1250_PASS2; 114 } else { 115 - prom_printf("Unknown BCM1250 rev %x\n", soc_pass); 116 ret = 1; 117 } 118 break; ··· 140 pass_str = "A2"; 141 break; 142 default: 143 - prom_printf("Unknown %s rev %x\n", soc_str, soc_pass); 144 ret = 1; 145 } 146 return ret; ··· 158 soc_pass = G_SYS_REVISION(sys_rev); 159 160 if (sys_rev_decode()) { 161 - prom_printf("Restart after failure to identify SiByte chip\n"); 162 machine_restart(NULL); 163 } 164 165 plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 166 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); 167 168 - prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", 169 soc_str, pass_str, zbbus_mhz * 2, sb1_pass); 170 - prom_printf("Board type: %s\n", get_system_type()); 171 172 switch (war_pass) { 173 case K_SYS_REVISION_BCM1250_PASS1: 174 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS 175 - prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, " 176 "and the kernel doesn't have the proper " 177 "workarounds compiled in. @@@@\n"); 178 bad_config = 1; ··· 182 /* Pass 2 - easiest as default for now - so many numbers */ 183 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \ 184 !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) 185 - prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the " 186 "kernel doesn't have the proper workarounds " 187 "compiled in. @@@@\n"); 188 bad_config = 1; 189 #endif 190 #ifdef CONFIG_CPU_HAS_PREFETCH 191 - prom_printf("@@@@ Prefetches may be enabled in this kernel, " 192 "but are buggy on this board. @@@@\n"); 193 bad_config = 1; 194 #endif 195 break; 196 case K_SYS_REVISION_BCM1250_PASS2_2: 197 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS 198 - prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the " 199 "kernel doesn't have the proper workarounds " 200 "compiled in. @@@@\n"); 201 bad_config = 1; 202 #endif 203 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \ 204 !defined(CONFIG_CPU_HAS_PREFETCH) 205 - prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is " 206 "conservatively configured for an 'A' stepping. " 207 "@@@@\n"); 208 #endif ··· 211 break; 212 } 213 if (bad_config) { 214 - prom_printf("Invalid configuration for this chip.\n"); 215 machine_restart(NULL); 216 } 217 }
··· 67 ret = setup_bcm112x(); 68 break; 69 default: 70 + printk("Unknown SOC type %x\n", soc_type); 71 ret = 1; 72 break; 73 } ··· 112 pass_str = "A0-A6"; 113 war_pass = K_SYS_REVISION_BCM1250_PASS2; 114 } else { 115 + printk("Unknown BCM1250 rev %x\n", soc_pass); 116 ret = 1; 117 } 118 break; ··· 140 pass_str = "A2"; 141 break; 142 default: 143 + printk("Unknown %s rev %x\n", soc_str, soc_pass); 144 ret = 1; 145 } 146 return ret; ··· 158 soc_pass = G_SYS_REVISION(sys_rev); 159 160 if (sys_rev_decode()) { 161 + printk("Restart after failure to identify SiByte chip\n"); 162 machine_restart(NULL); 163 } 164 165 plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 166 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); 167 168 + printk("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", 169 soc_str, pass_str, zbbus_mhz * 2, sb1_pass); 170 + printk("Board type: %s\n", get_system_type()); 171 172 switch (war_pass) { 173 case K_SYS_REVISION_BCM1250_PASS1: 174 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS 175 + printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, " 176 "and the kernel doesn't have the proper " 177 "workarounds compiled in. @@@@\n"); 178 bad_config = 1; ··· 182 /* Pass 2 - easiest as default for now - so many numbers */ 183 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \ 184 !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) 185 + printk("@@@@ This is a BCM1250 A3-A10 board, and the " 186 "kernel doesn't have the proper workarounds " 187 "compiled in. @@@@\n"); 188 bad_config = 1; 189 #endif 190 #ifdef CONFIG_CPU_HAS_PREFETCH 191 + printk("@@@@ Prefetches may be enabled in this kernel, " 192 "but are buggy on this board. @@@@\n"); 193 bad_config = 1; 194 #endif 195 break; 196 case K_SYS_REVISION_BCM1250_PASS2_2: 197 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS 198 + printk("@@@@ This is a BCM1250 B1/B2. board, and the " 199 "kernel doesn't have the proper workarounds " 200 "compiled in. @@@@\n"); 201 bad_config = 1; 202 #endif 203 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \ 204 !defined(CONFIG_CPU_HAS_PREFETCH) 205 + printk("@@@@ This is a BCM1250 B1/B2, but the kernel is " 206 "conservatively configured for an 'A' stepping. " 207 "@@@@\n"); 208 #endif ··· 211 break; 212 } 213 if (bad_config) { 214 + printk("Invalid configuration for this chip.\n"); 215 machine_restart(NULL); 216 } 217 }
+16 -35
arch/mips/sni/sniprom.c
··· 9 * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/string.h> ··· 34 #define PROM_ENTRY(x) (PROM_VEC + (x)) 35 36 37 - #define DEBUG 38 - #ifdef DEBUG 39 - #define DBG_PRINTF(x...) prom_printf(x) 40 - #else 41 - #define DBG_PRINTF(x...) 42 - #endif 43 - 44 static int *(*__prom_putchar)(int) = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR); 45 static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); 46 static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); 47 48 char *prom_getenv (char *s) 49 { 50 return __prom_getenv(s); 51 - } 52 - 53 - void prom_printf(char *fmt, ...) 54 - { 55 - va_list args; 56 - char ppbuf[1024]; 57 - char *bptr; 58 - 59 - va_start(args, fmt); 60 - vsprintf(ppbuf, fmt, args); 61 - 62 - bptr = ppbuf; 63 - 64 - while (*bptr != 0) { 65 - if (*bptr == '\n') 66 - __prom_putchar('\r'); 67 - 68 - __prom_putchar(*bptr++); 69 - } 70 - va_end(args); 71 } 72 73 void __init prom_free_prom_memory(void) ··· 75 { 76 int i; 77 78 - prom_printf("SNI IDProm dump:\n"); 79 for (i = 0; i < 256; i++) { 80 if (i%16 == 0) 81 - prom_printf("%04x ", i); 82 83 - prom_printf("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i)); 84 85 if (i % 16 == 15) 86 - prom_printf("\n"); 87 } 88 } 89 #endif ··· 102 /* MemSIZE from prom in 16MByte chunks */ 103 memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16; 104 105 - DBG_PRINTF("IDProm memsize: %lu MByte\n", memsize); 106 107 /* get memory bank layout from prom */ 108 __prom_get_memconf(&memconf); 109 110 - DBG_PRINTF("prom_get_mem_conf memory configuration:\n"); 111 for (i = 0;i < 8 && memconf[i].size; i++) { 112 if (sni_brd_type == SNI_BRD_PCI_TOWER || 113 sni_brd_type == SNI_BRD_PCI_TOWER_CPLUS) { ··· 116 memconf[i].base -= 0x20000000; 117 } 118 } 119 - DBG_PRINTF("Bank%d: %08x @ %08x\n", i, 120 memconf[i].size, memconf[i].base); 121 add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM); 122 } ··· 229 systype = "RM300-Exx"; 230 break; 231 } 232 - DBG_PRINTF("Found SNI brdtype %02x name %s\n", sni_brd_type,systype); 233 234 #ifdef DEBUG 235 sni_idprom_dump();
··· 9 * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) 10 */ 11 12 + #define DEBUG 13 + 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/string.h> ··· 32 #define PROM_ENTRY(x) (PROM_VEC + (x)) 33 34 35 static int *(*__prom_putchar)(int) = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR); 36 + 37 + void prom_putchar(char c) 38 + { 39 + __prom_putchar(c); 40 + } 41 + 42 static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); 43 static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); 44 45 char *prom_getenv (char *s) 46 { 47 return __prom_getenv(s); 48 } 49 50 void __init prom_free_prom_memory(void) ··· 94 { 95 int i; 96 97 + pr_debug("SNI IDProm dump:\n"); 98 for (i = 0; i < 256; i++) { 99 if (i%16 == 0) 100 + pr_debug("%04x ", i); 101 102 + printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i)); 103 104 if (i % 16 == 15) 105 + printk("\n"); 106 } 107 } 108 #endif ··· 121 /* MemSIZE from prom in 16MByte chunks */ 122 memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16; 123 124 + pr_debug("IDProm memsize: %lu MByte\n", memsize); 125 126 /* get memory bank layout from prom */ 127 __prom_get_memconf(&memconf); 128 129 + pr_debug("prom_get_mem_conf memory configuration:\n"); 130 for (i = 0;i < 8 && memconf[i].size; i++) { 131 if (sni_brd_type == SNI_BRD_PCI_TOWER || 132 sni_brd_type == SNI_BRD_PCI_TOWER_CPLUS) { ··· 135 memconf[i].base -= 0x20000000; 136 } 137 } 138 + pr_debug("Bank%d: %08x @ %08x\n", i, 139 memconf[i].size, memconf[i].base); 140 add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM); 141 } ··· 248 systype = "RM300-Exx"; 249 break; 250 } 251 + pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type,systype); 252 253 #ifdef DEBUG 254 sni_idprom_dump();
-10
arch/mips/tx4927/common/tx4927_setup.c
··· 81 82 void __init plat_timer_setup(struct irqaction *irq) 83 { 84 - u32 count; 85 - u32 c1; 86 - u32 c2; 87 - 88 setup_irq(TX4927_IRQ_CPU_TIMER, irq); 89 - 90 - /* to generate the first timer interrupt */ 91 - c1 = read_c0_count(); 92 - count = c1 + (mips_hpt_frequency / HZ); 93 - write_c0_compare(count); 94 - c2 = read_c0_count(); 95 96 #ifdef CONFIG_TOSHIBA_RBTX4927 97 {
··· 81 82 void __init plat_timer_setup(struct irqaction *irq) 83 { 84 setup_irq(TX4927_IRQ_CPU_TIMER, irq); 85 86 #ifdef CONFIG_TOSHIBA_RBTX4927 87 {
-3
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
··· 132 #include <asm/wbflush.h> 133 #include <linux/bootmem.h> 134 #include <linux/blkdev.h> 135 - #ifdef CONFIG_RTC_DS1742 136 - #include <linux/ds1742rtc.h> 137 - #endif 138 #ifdef CONFIG_TOSHIBA_FPCIB0 139 #include <asm/tx4927/smsc_fdc37m81x.h> 140 #endif
··· 132 #include <asm/wbflush.h> 133 #include <linux/bootmem.h> 134 #include <linux/blkdev.h> 135 #ifdef CONFIG_TOSHIBA_FPCIB0 136 #include <asm/tx4927/smsc_fdc37m81x.h> 137 #endif
+15 -61
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
··· 53 #include <linux/pci.h> 54 #include <linux/timex.h> 55 #include <linux/pm.h> 56 57 #include <asm/bootinfo.h> 58 #include <asm/page.h> ··· 65 #include <asm/time.h> 66 #include <linux/bootmem.h> 67 #include <linux/blkdev.h> 68 - #ifdef CONFIG_RTC_DS1742 69 - #include <linux/ds1742rtc.h> 70 - #endif 71 #ifdef CONFIG_TOSHIBA_FPCIB0 72 #include <asm/tx4927/smsc_fdc37m81x.h> 73 #endif ··· 1018 "+\n"); 1019 } 1020 1021 - #ifdef CONFIG_RTC_DS1742 1022 - extern unsigned long rtc_ds1742_get_time(void); 1023 - extern int rtc_ds1742_set_time(unsigned long); 1024 - extern void rtc_ds1742_wait(void); 1025 - #endif 1026 - 1027 void __init 1028 toshiba_rbtx4927_time_init(void) 1029 { 1030 - u32 c1; 1031 - u32 c2; 1032 - 1033 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n"); 1034 1035 - #ifdef CONFIG_RTC_DS1742 1036 - 1037 - rtc_mips_get_time = rtc_ds1742_get_time; 1038 - rtc_mips_set_time = rtc_ds1742_set_time; 1039 - 1040 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1041 - ":rtc_ds1742_init()-\n"); 1042 - rtc_ds1742_init(0xbc010000); 1043 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1044 - ":rtc_ds1742_init()+\n"); 1045 - 1046 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1047 - ":Calibrate mips_hpt_frequency-\n"); 1048 - rtc_ds1742_wait(); 1049 - 1050 - /* get the count */ 1051 - c1 = read_c0_count(); 1052 - 1053 - /* wait for the seconds to change again */ 1054 - rtc_ds1742_wait(); 1055 - 1056 - /* get the count again */ 1057 - c2 = read_c0_count(); 1058 - 1059 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1060 - ":Calibrate mips_hpt_frequency+\n"); 1061 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1062 - ":c1=%12u\n", c1); 1063 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1064 - ":c2=%12u\n", c2); 1065 - 1066 - /* this diff is as close as we are going to get to counter ticks per sec */ 1067 - mips_hpt_frequency = abs(c2 - c1); 1068 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1069 - ":f1=%12u\n", mips_hpt_frequency); 1070 - 1071 - /* round to 1/10th of a MHz */ 1072 - mips_hpt_frequency /= (100 * 1000); 1073 - mips_hpt_frequency *= (100 * 1000); 1074 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, 1075 - ":f2=%12u\n", mips_hpt_frequency); 1076 - 1077 - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO, 1078 - ":mips_hpt_frequency=%uHz (%uMHz)\n", 1079 - mips_hpt_frequency, 1080 - mips_hpt_frequency / 1000000); 1081 - #else 1082 - mips_hpt_frequency = 100000000; 1083 - #endif 1084 1085 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n"); 1086 ··· 1036 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP, 1037 "+\n"); 1038 }
··· 53 #include <linux/pci.h> 54 #include <linux/timex.h> 55 #include <linux/pm.h> 56 + #include <linux/platform_device.h> 57 58 #include <asm/bootinfo.h> 59 #include <asm/page.h> ··· 64 #include <asm/time.h> 65 #include <linux/bootmem.h> 66 #include <linux/blkdev.h> 67 #ifdef CONFIG_TOSHIBA_FPCIB0 68 #include <asm/tx4927/smsc_fdc37m81x.h> 69 #endif ··· 1020 "+\n"); 1021 } 1022 1023 void __init 1024 toshiba_rbtx4927_time_init(void) 1025 { 1026 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n"); 1027 1028 + mips_hpt_frequency = tx4927_cpu_clock / 2; 1029 1030 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n"); 1031 ··· 1095 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP, 1096 "+\n"); 1097 } 1098 + 1099 + static int __init toshiba_rbtx4927_rtc_init(void) 1100 + { 1101 + struct resource res = { 1102 + .start = 0x1c010000, 1103 + .end = 0x1c010000 + 0x800 - 1, 1104 + .flags = IORESOURCE_MEM, 1105 + }; 1106 + struct platform_device *dev = 1107 + platform_device_register_simple("ds1742", -1, &res, 1); 1108 + return IS_ERR(dev) ? PTR_ERR(dev) : 0; 1109 + } 1110 + device_initcall(toshiba_rbtx4927_rtc_init);
-9
arch/mips/tx4938/common/setup.c
··· 55 56 void __init plat_timer_setup(struct irqaction *irq) 57 { 58 - u32 count; 59 - u32 c1; 60 - u32 c2; 61 - 62 setup_irq(TX4938_IRQ_CPU_TIMER, irq); 63 - 64 - c1 = read_c0_count(); 65 - count = c1 + (mips_hpt_frequency / HZ); 66 - write_c0_compare(count); 67 - c2 = read_c0_count(); 68 }
··· 55 56 void __init plat_timer_setup(struct irqaction *irq) 57 { 58 setup_irq(TX4938_IRQ_CPU_TIMER, irq); 59 }
-13
include/asm-mips/ds1742.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org) 7 - */ 8 - #ifndef _ASM_DS1742_H 9 - #define _ASM_DS1742_H 10 - 11 - #include <ds1742.h> 12 - 13 - #endif /* _ASM_DS1742_H */
···
-6
include/asm-mips/jmr3927/jmr3927.h
··· 179 #define jmr3927_have_nvram() \ 180 ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT) 181 182 - /* NVRAM macro */ 183 - #define jmr3927_nvram_in(ofs) \ 184 - jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1)) 185 - #define jmr3927_nvram_out(d, ofs) \ 186 - jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1)) 187 - 188 /* LED macro */ 189 #define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) 190 #define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
··· 179 #define jmr3927_have_nvram() \ 180 ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT) 181 182 /* LED macro */ 183 #define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) 184 #define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
-2
include/asm-mips/lasat/lasat.h
··· 237 __delay(ns / lasat_ndelay_divider); 238 } 239 240 - extern void (* prom_printf)(const char *fmt, ...); 241 - 242 #endif /* !defined (_LANGUAGE_ASSEMBLY) */ 243 244 #define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
··· 237 __delay(ns / lasat_ndelay_divider); 238 } 239 240 #endif /* !defined (_LANGUAGE_ASSEMBLY) */ 241 242 #define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
+1 -1
include/asm-mips/mach-atlas/mc146818rtc.h
··· 55 56 #define RTC_ALWAYS_BCD 0 57 58 - #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) 59 60 #endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
··· 55 56 #define RTC_ALWAYS_BCD 0 57 58 + #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) 59 60 #endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
+6 -4
include/asm-mips/mach-generic/dma-coherence.h
··· 11 12 struct device; 13 14 - static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) 15 { 16 return virt_to_phys(addr); 17 } 18 19 - static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) 20 { 21 return page_to_phys(page); 22 } 23 24 - static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 25 { 26 return dma_addr; 27 } 28 29 - static void plat_unmap_dma_mem(dma_addr_t dma_addr) 30 { 31 } 32
··· 11 12 struct device; 13 14 + static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, 15 + size_t size) 16 { 17 return virt_to_phys(addr); 18 } 19 20 + static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, 21 + struct page *page) 22 { 23 return page_to_phys(page); 24 } 25 26 + static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 27 { 28 return dma_addr; 29 } 30 31 + static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 32 { 33 } 34
+1 -1
include/asm-mips/mach-generic/mc146818rtc.h
··· 30 #define RTC_ALWAYS_BCD 1 31 32 #ifndef mc146818_decode_year 33 - #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) 34 #endif 35 36 #endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
··· 30 #define RTC_ALWAYS_BCD 1 31 32 #ifndef mc146818_decode_year 33 + #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) 34 #endif 35 36 #endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
-16
include/asm-mips/mach-jmr3927/ds1742.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2003, 06 by Ralf Baechle 7 - */ 8 - #ifndef __ASM_MACH_JMR3927_DS1742_H 9 - #define __ASM_MACH_JMR3927_DS1742_H 10 - 11 - #include <asm/jmr3927/jmr3927.h> 12 - 13 - #define rtc_read(reg) (jmr3927_nvram_in(reg)) 14 - #define rtc_write(data, reg) (jmr3927_nvram_out((data),(reg))) 15 - 16 - #endif /* __ASM_MACH_JMR3927_DS1742_H */
···
+18
include/asm-mips/mach-jmr3927/mangle-port.h
···
··· 1 + #ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H 2 + #define __ASM_MACH_JMR3927_MANGLE_PORT_H 3 + 4 + extern unsigned long __swizzle_addr_b(unsigned long port); 5 + #define __swizzle_addr_w(port) (port) 6 + #define __swizzle_addr_l(port) (port) 7 + #define __swizzle_addr_q(port) (port) 8 + 9 + #define ioswabb(a,x) (x) 10 + #define __mem_ioswabb(a,x) (x) 11 + #define ioswabw(a,x) le16_to_cpu(x) 12 + #define __mem_ioswabw(a,x) (x) 13 + #define ioswabl(a,x) le32_to_cpu(x) 14 + #define __mem_ioswabl(a,x) (x) 15 + #define ioswabq(a,x) le64_to_cpu(x) 16 + #define __mem_ioswabq(a,x) (x) 17 + 18 + #endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */
+1 -1
include/asm-mips/mach-mips/mc146818rtc.h
··· 43 44 #define RTC_ALWAYS_BCD 0 45 46 - #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) 47 48 #endif /* __ASM_MACH_MALTA_MC146818RTC_H */
··· 43 44 #define RTC_ALWAYS_BCD 0 45 46 + #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) 47 48 #endif /* __ASM_MACH_MALTA_MC146818RTC_H */
+7 -3
include/asm-mips/mach-rm/mc146818rtc.h
··· 7 * 8 * RTC routines for PC style attached Dallas chip with ARC epoch. 9 */ 10 - #ifndef __ASM_MACH_RM200_MC146818RTC_H 11 - #define __ASM_MACH_RM200_MC146818RTC_H 12 13 #define mc146818_decode_year(year) ((year) + 1980) 14 15 #include_next <mc146818rtc.h> 16 17 - #endif /* __ASM_MACH_RM200_MC146818RTC_H */
··· 7 * 8 * RTC routines for PC style attached Dallas chip with ARC epoch. 9 */ 10 + #ifndef __ASM_MACH_RM_MC146818RTC_H 11 + #define __ASM_MACH_RM_MC146818RTC_H 12 13 + #ifdef CONFIG_CPU_BIG_ENDIAN 14 + #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) 15 + #else 16 #define mc146818_decode_year(year) ((year) + 1980) 17 + #endif 18 19 #include_next <mc146818rtc.h> 20 21 + #endif /* __ASM_MACH_RM_MC146818RTC_H */
-2
include/asm-mips/mips-boards/prom.h
··· 28 29 extern char *prom_getcmdline(void); 30 extern char *prom_getenv(char *name); 31 - extern void setup_prom_printf(int tty_no); 32 - extern void prom_printf(char *fmt, ...); 33 extern void prom_init_cmdline(void); 34 extern void prom_meminit(void); 35 extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
··· 28 29 extern char *prom_getcmdline(void); 30 extern char *prom_getenv(char *name); 31 extern void prom_init_cmdline(void); 32 extern void prom_meminit(void); 33 extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-3
include/asm-mips/sgialib.h
··· 33 extern void prom_putchar(char c); 34 extern char prom_getchar(void); 35 36 - /* Generic printf() using ARCS console I/O. */ 37 - extern void prom_printf(char *fmt, ...); 38 - 39 /* Memory descriptor management. */ 40 #define PROM_MAX_PMEMBLOCKS 32 41 struct prom_pmemblock {
··· 33 extern void prom_putchar(char c); 34 extern char prom_getchar(void); 35 36 /* Memory descriptor management. */ 37 #define PROM_MAX_PMEMBLOCKS 32 38 struct prom_pmemblock {
-2
include/asm-mips/sibyte/sb1250.h
··· 57 extern void bcm1480_unmask_irq(int cpu, int irq); 58 extern void bcm1480_smp_finish(void); 59 60 - extern void prom_printf(char *fmt, ...); 61 - 62 #define AT_spin \ 63 __asm__ __volatile__ ( \ 64 ".set noat\n" \
··· 57 extern void bcm1480_unmask_irq(int cpu, int irq); 58 extern void bcm1480_smp_finish(void); 59 60 #define AT_spin \ 61 __asm__ __volatile__ ( \ 62 ".set noat\n" \
-53
include/linux/ds1742rtc.h
··· 1 - /* 2 - * ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM 3 - * 4 - * Copyright (C) 1999-2001 Toshiba Corporation 5 - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) 6 - * 7 - * Permission is hereby granted to copy, modify and redistribute this code 8 - * in terms of the GNU Library General Public License, Version 2 or later, 9 - * at your option. 10 - */ 11 - #ifndef __LINUX_DS1742RTC_H 12 - #define __LINUX_DS1742RTC_H 13 - 14 - #include <asm/ds1742.h> 15 - 16 - #define RTC_BRAM_SIZE 0x800 17 - #define RTC_OFFSET 0x7f8 18 - 19 - /* 20 - * Register summary 21 - */ 22 - #define RTC_CONTROL (RTC_OFFSET + 0) 23 - #define RTC_CENTURY (RTC_OFFSET + 0) 24 - #define RTC_SECONDS (RTC_OFFSET + 1) 25 - #define RTC_MINUTES (RTC_OFFSET + 2) 26 - #define RTC_HOURS (RTC_OFFSET + 3) 27 - #define RTC_DAY (RTC_OFFSET + 4) 28 - #define RTC_DATE (RTC_OFFSET + 5) 29 - #define RTC_MONTH (RTC_OFFSET + 6) 30 - #define RTC_YEAR (RTC_OFFSET + 7) 31 - 32 - #define RTC_CENTURY_MASK 0x3f 33 - #define RTC_SECONDS_MASK 0x7f 34 - #define RTC_DAY_MASK 0x07 35 - 36 - /* 37 - * Bits in the Control/Century register 38 - */ 39 - #define RTC_WRITE 0x80 40 - #define RTC_READ 0x40 41 - 42 - /* 43 - * Bits in the Seconds register 44 - */ 45 - #define RTC_STOP 0x80 46 - 47 - /* 48 - * Bits in the Day register 49 - */ 50 - #define RTC_BATT_FLAG 0x80 51 - #define RTC_FREQ_TEST 0x40 52 - 53 - #endif /* __LINUX_DS1742RTC_H */
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