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ARM: 9004/1: debug: Split waituart to CTS and TXRDY

This patch was triggered by a remark from Russell that
introducing a call to the waituart (needed to fix debug prints
on the Qualcomm platforms) was dangerous because in some cases
this will involve waiting for a modem CTS (clear to send)
signal, and debug messages would maybe not work on platforms
with no modem connected to the UART port: they will just
hang waiting for the modem to assert CTS and this might never
happen.

Looking through all UART debug drivers implementing the waituart
macro I discovered that all users except two actually use this
macro to check if the UART is ready for TX, let's call this
TXRDY.

Only two debug UART drivers actually check for CTS:
- arch/arm/include/debug/8250.S
- arch/arm/include/debug/tegra.S

The former is very significant since the 8250 is possibly
the most common UART on the planet.

We have the following problem: the semantics of waituart are
ambiguous making it dangerous to introduce the macro to debug
code fixing debug prints for Qualcomm. To start to pry this
problem apart, this patch does the following:

- Convert all debug UART drivers to define two macros:

- waituartcts with the clear semantic to wait for CTS
to be asserted

- waituarttxrdy with the clear semantic to wait for the TX
capability of the UART to be ready

- When doing this take care to assign the right function to
each drivers macro, so they now do exactly the above.

- Update the three sites in the kernel invoking the waituart
macro to call waituartcts/waituarttxrdy in sequence, so that
the functional impact on the kernel should be zero.

After this we can start to change the code sites using this
code to do the right thing.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

authored by

Linus Walleij and committed by
Russell King 2c50a570 6428ea27

+114 -30
+2 -1
arch/arm/boot/compressed/debug.S
··· 8 8 9 9 ENTRY(putc) 10 10 addruart r1, r2, r3 11 - waituart r3, r1 11 + waituartcts r3, r1 12 + waituarttxrdy r3, r1 12 13 senduart r0, r1 13 14 busyuart r3, r1 14 15 mov pc, lr
+4 -1
arch/arm/include/debug/8250.S
··· 45 45 bne 1002b 46 46 .endm 47 47 48 - .macro waituart,rd,rx 48 + .macro waituarttxrdy,rd,rx 49 + .endm 50 + 51 + .macro waituartcts,rd,rx 49 52 #ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL 50 53 1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] 51 54 tst \rd, #UART_MSR_CTS
+4 -1
arch/arm/include/debug/asm9260.S
··· 11 11 ldr \rv, = CONFIG_DEBUG_UART_VIRT 12 12 .endm 13 13 14 - .macro waituart,rd,rx 14 + .macro waituarttxrdy,rd,rx 15 + .endm 16 + 17 + .macro waituartcts,rd,rx 15 18 .endm 16 19 17 20 .macro senduart,rd,rx
+4 -1
arch/arm/include/debug/at91.S
··· 19 19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register 20 20 .endm 21 21 22 - .macro waituart,rd,rx 22 + .macro waituarttxrdy,rd,rx 23 23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 24 24 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit 25 25 beq 1001b 26 + .endm 27 + 28 + .macro waituartcts,rd,rx 26 29 .endm 27 30 28 31 .macro busyuart,rd,rx
+4 -1
arch/arm/include/debug/bcm63xx.S
··· 17 17 strb \rd, [\rx, #UART_FIFO_REG] 18 18 .endm 19 19 20 - .macro waituart, rd, rx 20 + .macro waituarttxrdy, rd, rx 21 21 1001: ldr \rd, [\rx, #UART_IR_REG] 22 22 tst \rd, #(1 << UART_IR_TXEMPTY) 23 23 beq 1001b 24 + .endm 25 + 26 + .macro waituartcts, rd, rx 24 27 .endm 25 28 26 29 .macro busyuart, rd, rx
+4 -1
arch/arm/include/debug/brcmstb.S
··· 142 142 bne 1002b 143 143 .endm 144 144 145 - .macro waituart,rd,rx 145 + .macro waituarttxrdy,rd,rx 146 + .endm 147 + 148 + .macro waituartcts,rd,rx 146 149 .endm 147 150 148 151 /*
+4 -1
arch/arm/include/debug/clps711x.S
··· 20 20 ldr \rp, =CLPS711X_UART_PADDR 21 21 .endm 22 22 23 - .macro waituart,rd,rx 23 + .macro waituartcts,rd,rx 24 + .endm 25 + 26 + .macro waituarttxrdy,rd,rx 24 27 .endm 25 28 26 29 .macro senduart,rd,rx
+4 -1
arch/arm/include/debug/dc21285.S
··· 34 34 bne 1001b 35 35 .endm 36 36 37 - .macro waituart,rd,rx 37 + .macro waituartcts,rd,rx 38 + .endm 39 + 40 + .macro waituarttxrdy,rd,rx 38 41 .endm
+4 -1
arch/arm/include/debug/digicolor.S
··· 21 21 strb \rd, [\rx, #UA0_EMI_REC] 22 22 .endm 23 23 24 - .macro waituart,rd,rx 24 + .macro waituartcts,rd,rx 25 + .endm 26 + 27 + .macro waituarttxrdy,rd,rx 25 28 .endm 26 29 27 30 .macro busyuart,rd,rx
+4 -1
arch/arm/include/debug/efm32.S
··· 29 29 strb \rd, [\rx, #UARTn_TXDATA] 30 30 .endm 31 31 32 - .macro waituart,rd,rx 32 + .macro waituartcts,rd,rx 33 + .endm 34 + 35 + .macro waituarttxrdy,rd,rx 33 36 1001: ldr \rd, [\rx, #UARTn_STATUS] 34 37 tst \rd, #UARTn_STATUS_TXBL 35 38 beq 1001b
+12 -3
arch/arm/include/debug/icedcc.S
··· 23 23 beq 1001b 24 24 .endm 25 25 26 - .macro waituart, rd, rx 26 + .macro waituartcts, rd, rx 27 + .endm 28 + 29 + .macro waituarttxrdy, rd, rx 27 30 mov \rd, #0x2000000 28 31 1001: 29 32 subs \rd, \rd, #1 ··· 50 47 beq 1001b 51 48 .endm 52 49 53 - .macro waituart, rd, rx 50 + .macro waituartcts, rd, rx 51 + .endm 52 + 53 + .macro waituarttxrdy, rd, rx 54 54 mov \rd, #0x10000000 55 55 1001: 56 56 subs \rd, \rd, #1 ··· 78 72 79 73 .endm 80 74 81 - .macro waituart, rd, rx 75 + .macro waituartcts, rd, rx 76 + .endm 77 + 78 + .macro waituarttxrdy, rd, rx 82 79 mov \rd, #0x2000000 83 80 1001: 84 81 subs \rd, \rd, #1
+4 -1
arch/arm/include/debug/imx.S
··· 35 35 str \rd, [\rx, #0x40] @ TXDATA 36 36 .endm 37 37 38 - .macro waituart,rd,rx 38 + .macro waituartcts,rd,rx 39 + .endm 40 + 41 + .macro waituarttxrdy,rd,rx 39 42 .endm 40 43 41 44 .macro busyuart,rd,rx
+4 -1
arch/arm/include/debug/meson.S
··· 25 25 beq 1002b 26 26 .endm 27 27 28 - .macro waituart,rd,rx 28 + .macro waituartcts,rd,rx 29 + .endm 30 + 31 + .macro waituarttxrdy,rd,rx 29 32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] 30 33 tst \rd, #MESON_AO_UART_TX_FIFO_FULL 31 34 bne 1001b
+4 -1
arch/arm/include/debug/msm.S
··· 17 17 str \rd, [\rx, #0x70] 18 18 .endm 19 19 20 - .macro waituart, rd, rx 20 + .macro waituartcts,rd,rx 21 + .endm 22 + 23 + .macro waituarttxrdy, rd, rx 21 24 @ check for TX_EMT in UARTDM_SR 22 25 ldr \rd, [\rx, #0x08] 23 26 ARM_BE8(rev \rd, \rd )
+4 -1
arch/arm/include/debug/omap2plus.S
··· 75 75 bne 1001b 76 76 .endm 77 77 78 - .macro waituart,rd,rx 78 + .macro waituartcts,rd,rx 79 + .endm 80 + 81 + .macro waituarttxrdy,rd,rx 79 82 .endm
+4 -1
arch/arm/include/debug/pl01x.S
··· 26 26 strb \rd, [\rx, #UART01x_DR] 27 27 .endm 28 28 29 - .macro waituart,rd,rx 29 + .macro waituartcts,rd,rx 30 + .endm 31 + 32 + .macro waituarttxrdy,rd,rx 30 33 1001: ldr \rd, [\rx, #UART01x_FR] 31 34 ARM_BE8( rev \rd, \rd ) 32 35 tst \rd, #UART01x_FR_TXFF
+4 -1
arch/arm/include/debug/renesas-scif.S
··· 33 33 ldr \rv, =SCIF_VIRT 34 34 .endm 35 35 36 - .macro waituart, rd, rx 36 + .macro waituartcts,rd,rx 37 + .endm 38 + 39 + .macro waituarttxrdy, rd, rx 37 40 1001: ldrh \rd, [\rx, #FSR] 38 41 tst \rd, #TDFE 39 42 beq 1001b
+4 -1
arch/arm/include/debug/sa1100.S
··· 51 51 str \rd, [\rx, #UTDR] 52 52 .endm 53 53 54 - .macro waituart,rd,rx 54 + .macro waituartcts,rd,rx 55 + .endm 56 + 57 + .macro waituarttxrdy,rd,rx 55 58 1001: ldr \rd, [\rx, #UTSR1] 56 59 tst \rd, #UTSR1_TNF 57 60 beq 1001b
+4 -1
arch/arm/include/debug/samsung.S
··· 69 69 1002: @ exit busyuart 70 70 .endm 71 71 72 - .macro waituart,rd,rx 72 + .macro waituartcts,rd,rx 73 + .endm 74 + 75 + .macro waituarttxrdy,rd,rx 73 76 ldr \rd, [\rx, # S3C2410_UFCON] 74 77 ARM_BE8(rev \rd, \rd) 75 78 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
+4 -1
arch/arm/include/debug/sirf.S
··· 29 29 .macro busyuart,rd,rx 30 30 .endm 31 31 32 - .macro waituart,rd,rx 32 + .macro waituartcts,rd,rx 33 + .endm 34 + 35 + .macro waituarttxrdy,rd,rx 33 36 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS] 34 37 tst \rd, #SIRF_LLUART_TXFIFO_EMPTY 35 38 beq 1001b
+4 -1
arch/arm/include/debug/sti.S
··· 45 45 strb \rd, [\rx, #ASC_TX_BUF_OFF] 46 46 .endm 47 47 48 - .macro waituart,rd,rx 48 + .macro waituartcts,rd,rx 49 + .endm 50 + 51 + .macro waituarttxrdy,rd,rx 49 52 1001: ldr \rd, [\rx, #ASC_STA_OFF] 50 53 tst \rd, #ASC_STA_TX_FULL 51 54 bne 1001b
+4 -1
arch/arm/include/debug/stm32.S
··· 27 27 strb \rd, [\rx, #STM32_USART_TDR_OFF] 28 28 .endm 29 29 30 - .macro waituart,rd,rx 30 + .macro waituartcts,rd,rx 31 + .endm 32 + 33 + .macro waituarttxrdy,rd,rx 31 34 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register 32 35 tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty 33 36 beq 1001b
+4 -1
arch/arm/include/debug/tegra.S
··· 178 178 1002: 179 179 .endm 180 180 181 - .macro waituart, rd, rx 181 + .macro waituartcts, rd, rx 182 182 #ifdef FLOW_CONTROL 183 183 cmp \rx, #0 184 184 beq 1002f ··· 187 187 beq 1001b 188 188 1002: 189 189 #endif 190 + .endm 191 + 192 + .macro waituarttxrdy,rd,rx 190 193 .endm 191 194 192 195 /*
+4 -1
arch/arm/include/debug/vf.S
··· 29 29 beq 1001b @ wait until transmit done 30 30 .endm 31 31 32 - .macro waituart,rd,rx 32 + .macro waituartcts,rd,rx 33 + .endm 34 + 35 + .macro waituarttxrdy,rd,rx 33 36 .endm
+4 -1
arch/arm/include/debug/vt8500.S
··· 28 28 bne 1001b 29 29 .endm 30 30 31 - .macro waituart,rd,rx 31 + .macro waituartcts,rd,rx 32 + .endm 33 + 34 + .macro waituarttxrdy,rd,rx 32 35 .endm 33 36 34 37 #endif
+4 -1
arch/arm/include/debug/zynq.S
··· 33 33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 34 34 .endm 35 35 36 - .macro waituart,rd,rx 36 + .macro waituartcts,rd,rx 37 + .endm 38 + 39 + .macro waituarttxrdy,rd,rx 37 40 1001: ldr \rd, [\rx, #UART_SR_OFFSET] 38 41 ARM_BE8( rev \rd, \rd ) 39 42 tst \rd, #UART_SR_TXEMPTY
+4 -2
arch/arm/kernel/debug.S
··· 89 89 2: teq r1, #'\n' 90 90 bne 3f 91 91 mov r1, #'\r' 92 - waituart r2, r3 92 + waituartcts r2, r3 93 + waituarttxrdy r2, r3 93 94 senduart r1, r3 94 95 busyuart r2, r3 95 96 mov r1, #'\n' 96 - 3: waituart r2, r3 97 + 3: waituartcts r2, r3 98 + waituarttxrdy r2, r3 97 99 senduart r1, r3 98 100 busyuart r2, r3 99 101 b 1b