Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

cxl/test: Skip cxl_setup_parent_dport() for emulated dports

The cxl_test unit test environment on qemu always hits below call trace
with KASAN enabled:

BUG: KASAN: slab-out-of-bounds in cxl_setup_parent_dport+0x480/0x530 [cxl_core]
Read of size 1 at addr ff110000676014f8 by task (udev-worker)/676[ 24.424403] CPU: 2 PID: 676 Comm: (udev-worker) Tainted: G O N 6.10.0-qemucxl #1
Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS edk2-20240214-2.el9 02/14/2024
Call Trace:
<TASK>
dump_stack_lvl+0xea/0x150
print_report+0xce/0x610
? kasan_complete_mode_report_info+0x40/0x200
kasan_report+0xcc/0x110
__asan_report_load1_noabort+0x18/0x20
cxl_setup_parent_dport+0x480/0x530 [cxl_core]
cxl_mem_probe+0x49b/0xaa0 [cxl_mem]

cxl_test module models a CXL topology for testing, it creates some
emulated dports with platform devices in the CXL topology, so the
dport_dev of an emulated dport points to a platform device rather than a
pci device or a pci host bridge in the case. Currently,
cxl_setup_parent_dport() is used to set up RAS and AER capability on the
dport connected to the CXL memory device, but cxl_test does not support
RAS or AER functionality yet, so the fix is implementing a
__wrap_cxl_setup_parent_dport() to filter out all emulated dports,
guarantees only real dports can be handled by cxl_setup_parent_dport().

Fixes: f05fd10d138d ("cxl/pci: Add RCH downstream port AER register discovery")
Reported-by: Pengfei Xu <pengfei.xu@intel.com>
Closes: https://lore.kernel.org/linux-cxl/ZrHTBp2O+HtUe6kt@xpf.sh.intel.com/T/#t
Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Tested-by: Ira Weiny <ira.weiny@intel.com>
Tested-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240809082750.3015641-3-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Li Ming and committed by
Dave Jiang
2c402bd2 8c251c5a

+13
+1
tools/testing/cxl/Kbuild
··· 14 14 ldflags-y += --wrap=devm_cxl_add_rch_dport 15 15 ldflags-y += --wrap=cxl_rcd_component_reg_phys 16 16 ldflags-y += --wrap=cxl_endpoint_parse_cdat 17 + ldflags-y += --wrap=cxl_setup_parent_dport 17 18 18 19 DRIVERS := ../../../drivers 19 20 CXL_SRC := $(DRIVERS)/cxl
+12
tools/testing/cxl/test/mock.c
··· 299 299 } 300 300 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_endpoint_parse_cdat, CXL); 301 301 302 + void __wrap_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport) 303 + { 304 + int index; 305 + struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); 306 + 307 + if (!ops || !ops->is_mock_port(dport->dport_dev)) 308 + cxl_setup_parent_dport(host, dport); 309 + 310 + put_cxl_mock_ops(index); 311 + } 312 + EXPORT_SYMBOL_NS_GPL(__wrap_cxl_setup_parent_dport, CXL); 313 + 302 314 MODULE_LICENSE("GPL v2"); 303 315 MODULE_IMPORT_NS(ACPI); 304 316 MODULE_IMPORT_NS(CXL);