tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
parisc: Imporove debug info about space registers and TLB configuration
Signed-off-by: Helge Deller <deller@gmx.de>
+23
-5
+1
-1
arch/parisc/include/asm/pdc.h
+1
-1
arch/parisc/include/asm/pdc.h
···
63
63
tc_page : 1, /* 0 = 2K page-size-machine, 1 = 4k page size */
64
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tc_cst : 3, /* 0 = incoherent operations, else coherent operations */
65
65
tc_aid : 5, /* ITLB: width of access ids of processor (encoded!) */
66
-
tc_pad1 : 8; /* ITLB: width of space-registers (encoded) */
66
+
tc_sr : 8; /* ITLB: width of space-registers (encoded) */
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};
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68
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struct pdc_cache_info { /* main-PDC_CACHE-structure (caches & TLB's) */
+22
-4
arch/parisc/kernel/cache.c
+22
-4
arch/parisc/kernel/cache.c
···
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cache_info.ic_count,
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cache_info.ic_loop);
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+
printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
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+
cache_info.it_sp_base,
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+
cache_info.it_sp_stride,
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+
cache_info.it_sp_count,
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+
cache_info.it_loop,
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+
cache_info.it_off_base,
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+
cache_info.it_off_stride,
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+
cache_info.it_off_count);
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+
184
+
printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
185
+
cache_info.dt_sp_base,
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+
cache_info.dt_sp_stride,
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+
cache_info.dt_sp_count,
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+
cache_info.dt_loop,
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+
cache_info.dt_off_base,
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+
cache_info.dt_off_stride,
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+
cache_info.dt_off_count);
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+
175
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printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.ic_conf),
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cache_info.ic_conf.cc_alias,
···
202
184
cache_info.ic_conf.cc_cst,
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185
cache_info.ic_conf.cc_hv);
204
186
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-
printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
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+
printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
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cache_info.dt_conf.tc_sh,
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189
cache_info.dt_conf.tc_page,
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cache_info.dt_conf.tc_cst,
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191
cache_info.dt_conf.tc_aid,
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-
cache_info.dt_conf.tc_pad1);
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+
cache_info.dt_conf.tc_sr);
211
193
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-
printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
194
+
printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
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195
cache_info.it_conf.tc_sh,
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cache_info.it_conf.tc_page,
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cache_info.it_conf.tc_cst,
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cache_info.it_conf.tc_aid,
217
-
cache_info.it_conf.tc_pad1);
199
+
cache_info.it_conf.tc_sr);
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#endif
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split_tlb = 0;