Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks

Currently, attempting to enable the UBI clocks will cause the stuck at
off warning to be printed and clk_enable will fail.

[ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off'

Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
flag on UBI clocks, so lets do the same.

Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com

authored by

Robert Marko and committed by
Bjorn Andersson
2bd357e6 74521205

+10
+10
drivers/clk/qcom/gcc-ipq8074.c
··· 3372 3372 3373 3373 static struct clk_branch gcc_ubi0_ahb_clk = { 3374 3374 .halt_reg = 0x6820c, 3375 + .halt_check = BRANCH_HALT_DELAY, 3375 3376 .clkr = { 3376 3377 .enable_reg = 0x6820c, 3377 3378 .enable_mask = BIT(0), ··· 3390 3389 3391 3390 static struct clk_branch gcc_ubi0_axi_clk = { 3392 3391 .halt_reg = 0x68200, 3392 + .halt_check = BRANCH_HALT_DELAY, 3393 3393 .clkr = { 3394 3394 .enable_reg = 0x68200, 3395 3395 .enable_mask = BIT(0), ··· 3408 3406 3409 3407 static struct clk_branch gcc_ubi0_nc_axi_clk = { 3410 3408 .halt_reg = 0x68204, 3409 + .halt_check = BRANCH_HALT_DELAY, 3411 3410 .clkr = { 3412 3411 .enable_reg = 0x68204, 3413 3412 .enable_mask = BIT(0), ··· 3426 3423 3427 3424 static struct clk_branch gcc_ubi0_core_clk = { 3428 3425 .halt_reg = 0x68210, 3426 + .halt_check = BRANCH_HALT_DELAY, 3429 3427 .clkr = { 3430 3428 .enable_reg = 0x68210, 3431 3429 .enable_mask = BIT(0), ··· 3444 3440 3445 3441 static struct clk_branch gcc_ubi0_mpt_clk = { 3446 3442 .halt_reg = 0x68208, 3443 + .halt_check = BRANCH_HALT_DELAY, 3447 3444 .clkr = { 3448 3445 .enable_reg = 0x68208, 3449 3446 .enable_mask = BIT(0), ··· 3462 3457 3463 3458 static struct clk_branch gcc_ubi1_ahb_clk = { 3464 3459 .halt_reg = 0x6822c, 3460 + .halt_check = BRANCH_HALT_DELAY, 3465 3461 .clkr = { 3466 3462 .enable_reg = 0x6822c, 3467 3463 .enable_mask = BIT(0), ··· 3480 3474 3481 3475 static struct clk_branch gcc_ubi1_axi_clk = { 3482 3476 .halt_reg = 0x68220, 3477 + .halt_check = BRANCH_HALT_DELAY, 3483 3478 .clkr = { 3484 3479 .enable_reg = 0x68220, 3485 3480 .enable_mask = BIT(0), ··· 3498 3491 3499 3492 static struct clk_branch gcc_ubi1_nc_axi_clk = { 3500 3493 .halt_reg = 0x68224, 3494 + .halt_check = BRANCH_HALT_DELAY, 3501 3495 .clkr = { 3502 3496 .enable_reg = 0x68224, 3503 3497 .enable_mask = BIT(0), ··· 3516 3508 3517 3509 static struct clk_branch gcc_ubi1_core_clk = { 3518 3510 .halt_reg = 0x68230, 3511 + .halt_check = BRANCH_HALT_DELAY, 3519 3512 .clkr = { 3520 3513 .enable_reg = 0x68230, 3521 3514 .enable_mask = BIT(0), ··· 3534 3525 3535 3526 static struct clk_branch gcc_ubi1_mpt_clk = { 3536 3527 .halt_reg = 0x68228, 3528 + .halt_check = BRANCH_HALT_DELAY, 3537 3529 .clkr = { 3538 3530 .enable_reg = 0x68228, 3539 3531 .enable_mask = BIT(0),