tjh.dev / kernel
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mv643xx_eth: Check ETH_INT_CAUSE_STATE bit

Commit 468d09f8946d40228c56de26fe4874b2f98067ed masked the "state"
interrupt (bit 20 of the cause register). This results in Radstone's
PPC7D repeatedly re-entering the interrupt routine, locking up the
board. The following patch returns the required handling for this
interrupt.

Signed-off-by: Martyn Welch <martyn.welch@radstone.co.uk>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

authored by Dale Farnsworth and committed by Jeff Garzik 2bcff60f 1bef7dc0

+4 -2
unified split
+1 -1
drivers/net/mv643xx_eth.c
··· 534 } 535 536 /* PHY status changed */ 537 - if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) { 538 struct ethtool_cmd cmd; 539 540 if (mii_link_ok(&mp->mii)) {
··· 534 } 535 536 /* PHY status changed */ 537 + if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) { 538 struct ethtool_cmd cmd; 539 540 if (mii_link_ok(&mp->mii)) {
+3 -1
drivers/net/mv643xx_eth.h
··· 64 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) 65 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) 66 #define ETH_INT_CAUSE_PHY 0x00010000 67 - #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY) 68 69 #define ETH_INT_MASK_ALL 0x00000000 70 #define ETH_INT_MASK_ALL_EXT 0x00000000
··· 64 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) 65 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) 66 #define ETH_INT_CAUSE_PHY 0x00010000 67 + #define ETH_INT_CAUSE_STATE 0x00100000 68 + #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \ 69 + ETH_INT_CAUSE_STATE) 70 71 #define ETH_INT_MASK_ALL 0x00000000 72 #define ETH_INT_MASK_ALL_EXT 0x00000000