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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
phy: cadence: sierra: Fix for USB3 U1/U2 state
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar <sparmar@cadence.com>
Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.com
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
authored by
Sanket Parmar
and committed by
Kishon Vijay Abraham I
2bcf14ca
257d0be3
+14
-13
+14
-13
drivers/phy/cadence/phy-cadence-sierra.c
+14
-13
drivers/phy/cadence/phy-cadence-sierra.c
···
685
685
static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
686
686
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
687
687
{0x000F, SIERRA_DET_STANDEC_B_PREG},
688
-
{0x00A5, SIERRA_DET_STANDEC_C_PREG},
688
+
{0x55A5, SIERRA_DET_STANDEC_C_PREG},
689
689
{0x69ad, SIERRA_DET_STANDEC_D_PREG},
690
690
{0x0241, SIERRA_DET_STANDEC_E_PREG},
691
-
{0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
691
+
{0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
692
692
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
693
693
{0xCF00, SIERRA_PSM_DIAG_PREG},
694
694
{0x001F, SIERRA_PSC_TX_A0_PREG},
···
696
696
{0x0003, SIERRA_PSC_TX_A2_PREG},
697
697
{0x0003, SIERRA_PSC_TX_A3_PREG},
698
698
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
699
-
{0x0619, SIERRA_PSC_RX_A1_PREG},
699
+
{0x0003, SIERRA_PSC_RX_A1_PREG},
700
700
{0x0003, SIERRA_PSC_RX_A2_PREG},
701
701
{0x0001, SIERRA_PSC_RX_A3_PREG},
702
702
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
···
705
705
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
706
706
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
707
707
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
708
-
{0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
709
-
{0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
710
-
{0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
708
+
{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
709
+
{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
710
+
{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
711
711
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
712
-
{0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
712
+
{0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
713
713
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
714
714
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
715
-
{0x8000, SIERRA_CREQ_SPARE_PREG},
715
+
{0x0000, SIERRA_CREQ_SPARE_PREG},
716
716
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
717
-
{0x8453, SIERRA_CTLELUT_CTRL_PREG},
718
-
{0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
719
-
{0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
720
-
{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
717
+
{0x8452, SIERRA_CTLELUT_CTRL_PREG},
718
+
{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
719
+
{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
720
+
{0x0003, SIERRA_DEQ_PHALIGN_CTRL},
721
721
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
722
722
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
723
723
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
···
725
725
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
726
726
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
727
727
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
728
-
{0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
728
+
{0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
729
729
{0x0014, SIERRA_DEQ_GLUT0},
730
730
{0x0014, SIERRA_DEQ_GLUT1},
731
731
{0x0014, SIERRA_DEQ_GLUT2},
···
772
772
{0x000F, SIERRA_LFPSFILT_NS_PREG},
773
773
{0x0009, SIERRA_LFPSFILT_RD_PREG},
774
774
{0x0001, SIERRA_LFPSFILT_MP_PREG},
775
+
{0x6013, SIERRA_SIGDET_SUPPORT_PREG},
775
776
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
776
777
{0x8009, SIERRA_SDFILT_L2H_PREG},
777
778
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},