tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: rockchip: make tightly bound armclk child-clocks read-only

Rockchip SoCs contain clocks tightly bound to the armclk, where the best
rate / divider is supplied by the vendor after careful measuring.
Often this ideal rate may be greater than the current rate.

Therefore prevent the ccf from trying to set these dividers itself by
setting them to read-only.

In the case of the rk3066, this also includes the aclk_cpu, which makes it
necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...)
into individual definitions for rk3066 and rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

Heiko Stuebner 2b9bceea f5f7004f

+27 -17
+18 -8
drivers/clk/rockchip/clk-rk3188.c
··· 174 174 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, 175 175 RK2928_CLKGATE_CON(0), 3, GFLAGS), 176 176 177 - DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 178 - RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 179 177 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, 180 178 RK2928_CLKGATE_CON(0), 6, GFLAGS), 181 179 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, 182 180 RK2928_CLKGATE_CON(0), 5, GFLAGS), 183 - DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 184 - RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 185 - COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 186 - RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 187 - RK2928_CLKGATE_CON(4), 9, GFLAGS), 188 181 GATE(0, "hclk_cpu", "hclk_cpu_pre", 0, 189 182 RK2928_CLKGATE_CON(0), 4, GFLAGS), 190 183 ··· 409 416 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0, 410 417 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 0, 5, DFLAGS), 411 418 DIVTBL(0, "aclk_cpu_pre", "armclk", 0, 412 - RK2928_CLKSEL_CON(1), 0, 3, DFLAGS, div_aclk_cpu_t), 419 + RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), 420 + DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 421 + RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 422 + | CLK_DIVIDER_READ_ONLY), 423 + DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 424 + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 425 + | CLK_DIVIDER_READ_ONLY), 426 + COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 427 + RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 428 + | CLK_DIVIDER_READ_ONLY, 429 + RK2928_CLKGATE_CON(4), 9, GFLAGS), 413 430 414 431 GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0, 415 432 RK2928_CLKGATE_CON(9), 4, GFLAGS), ··· 537 534 /* do not source aclk_cpu_pre from the apll, to keep complexity down */ 538 535 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, 539 536 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), 537 + DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 538 + RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 539 + DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 540 + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 541 + COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 542 + RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 543 + RK2928_CLKGATE_CON(4), 9, GFLAGS), 540 544 541 545 GATE(CORE_L2C, "core_l2c", "armclk", 0, 542 546 RK2928_CLKGATE_CON(9), 4, GFLAGS),
+9 -9
drivers/clk/rockchip/clk-rk3288.c
··· 170 170 RK3288_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), 171 171 172 172 COMPOSITE_NOMUX(0, "armcore0", "armclk", 0, 173 - RK3288_CLKSEL_CON(36), 0, 3, DFLAGS, 173 + RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 174 174 RK3288_CLKGATE_CON(12), 0, GFLAGS), 175 175 COMPOSITE_NOMUX(0, "armcore1", "armclk", 0, 176 - RK3288_CLKSEL_CON(36), 4, 3, DFLAGS, 176 + RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 177 177 RK3288_CLKGATE_CON(12), 1, GFLAGS), 178 178 COMPOSITE_NOMUX(0, "armcore2", "armclk", 0, 179 - RK3288_CLKSEL_CON(36), 8, 3, DFLAGS, 179 + RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 180 180 RK3288_CLKGATE_CON(12), 2, GFLAGS), 181 181 COMPOSITE_NOMUX(0, "armcore3", "armclk", 0, 182 - RK3288_CLKSEL_CON(36), 12, 3, DFLAGS, 182 + RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 183 183 RK3288_CLKGATE_CON(12), 3, GFLAGS), 184 184 COMPOSITE_NOMUX(0, "l2ram", "armclk", 0, 185 - RK3288_CLKSEL_CON(37), 0, 3, DFLAGS, 185 + RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 186 186 RK3288_CLKGATE_CON(12), 4, GFLAGS), 187 187 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0, 188 - RK3288_CLKSEL_CON(0), 0, 4, DFLAGS, 188 + RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 189 189 RK3288_CLKGATE_CON(12), 5, GFLAGS), 190 190 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0, 191 - RK3288_CLKSEL_CON(0), 4, 4, DFLAGS, 191 + RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 192 192 RK3288_CLKGATE_CON(12), 6, GFLAGS), 193 193 COMPOSITE_NOMUX(0, "atclk", "armclk", 0, 194 - RK3288_CLKSEL_CON(37), 4, 5, DFLAGS, 194 + RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 195 195 RK3288_CLKGATE_CON(12), 7, GFLAGS), 196 196 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0, 197 - RK3288_CLKSEL_CON(37), 9, 5, DFLAGS, 197 + RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 198 198 RK3288_CLKGATE_CON(12), 8, GFLAGS), 199 199 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0, 200 200 RK3288_CLKGATE_CON(12), 9, GFLAGS),